Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-28 23:51:33 +00:00
Code Issues Projects Releases Packages Wiki Activity

spi: fsl_qspi: Copy 16 byte aligned data in TX FIFO

Browse source 
In some of the QSPI controller version, there must be atleast
128bit data available in TX FIFO for any pop operation otherwise
error bit will be set. The code will not make any behavior change
for previous controller as the transfer data size in ipcr register
is still the same.

Patch is tested on LS1046A which do not require 16 bytes aligned and
LS1088A which require 16 bytes aligned data in TX FIFO

Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Anupam Kumar <anupam.kumar_1@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This commit is contained in:
Suresh Gupta 2017-06-05 14:37:20 +05:30 committed by Jagan Teki
parent db10809c17
commit 1050998728
1 changed files with 8 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

18
drivers/spi/fsl_qspi.c
View file

@ -664,22 +664,20 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
tx_size = (len > TX_BUFFER_SIZE) ?
TX_BUFFER_SIZE : len;
size = tx_size / 4;
for (i = 0; i < size; i++) {
size = tx_size / 16;
/*
* There must be atleast 128bit data
* available in TX FIFO for any pop operation
*/
if (tx_size % 16)
size++;
for (i = 0; i < size * 4; i++) {
memcpy(&data, txbuf, 4);
data = qspi_endian_xchg(data);
qspi_write32(priv->flags, &regs->tbdr, data);
txbuf += 4;
}
size = tx_size % 4;
if (size) {
data = 0;
memcpy(&data, txbuf, size);
data = qspi_endian_xchg(data);
qspi_write32(priv->flags, &regs->tbdr, data);
}
qspi_write32(priv->flags, &regs->ipcr,
(seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)