TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a
bunch on on-chip integrated peripherals. This is an initial commit with
basic functionality, more commits with drivers, etc. to follow.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The current ARM1176 CPU specific code is too specific to the SMDK6400
architecture. The following changes were necessary prerequisites for the
addition of other SoCs based on ARM1176.
Existing board's (SMDK6400) configuration has been modified to keep behavior
unchanged despite these changes.
1. Peripheral port remap configurability
The earlier code had hardcoded remap values specific to s3c64xx in start.S.
This change makes the peripheral port remap addresses and sizes configurable.
2. U-Boot code relocation support
Most architectures allow u-boot code to run initially at a different
address (possibly in NOR) and then get relocated to its final resting place
in RAM. Added support for this capability in ARM1176 architecture.
3. Disable TCM if necessary
If a ROM based bootloader happened to have initialized TCM, we disable it here
to keep things sane.
4. Remove unnecessary SoC specific includes
ARM1176 code does not really need this SoC specific include. The presence
of this include prevents builds on other ARM1176 archs.
5. Modified virt-to-phys conversion during MMU disable
The original MMU disable code masks out too many bits from the load address
when it tries to figure out the physical address of the jump target label.
Consequently, it ends up branching to the wrong address after disabling the
MMU.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0"
instruction which means "Invalidate Both Caches" when in fact the intent
is to clean and invalidate all caches. So add an "mcr p15, 0, %0, c7,
c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate
Both Caches" instruction to insure that memory is consistent with any
dirty cache lines.
Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so
that they correctly describe the actual ARM1136 CP15 C7 Cache Operations
used.
Signed-off-by: George G. Davis <gdavis@mvista.com>
Add the 'clkdvdr' and 'pmuxcr2' registers to the 85xx definition of
struct ccsr_gur.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch allows users to override default STANDALONE_LOAD_ADDR.
The gcclibdir path was duplicated in the standalone Makefile and
can be removed.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
This patch fixes the run-time error on div64 when built with
gcc4, which was reported by jhwu0625 on nios forum. It merges
math support from libgcc of gcc4. This patch is copied from
nios2-linux.
It works with both gcc3 and gcc4. The old mult.c, divmod.c and
math.h are removed.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
The "-ffixed-r15" option doesn't work well for gcc4. Since we
don't use gp for small data with option "-G0", we can use gp
as global data pointer. This allows compiler to use r15. It
is necessary for gcc4 to work properly.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
This patch adds driver for a trivial gpio core, which is described
in http://nioswiki.com/GPIO. It is used for gpio led and nand flash
interface in u-boot.
When CONFIG_SYS_GPIO_BASE is not defined, board may provide
its own driver.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Tested-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
This patch adds support for full MII interface on MCF5445x (in contrast
to RMII as used on the evaluation boards).
Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
This patch adds the possibility to handle seperate PHYs to MCF5445x.
Naming is chosen to resemble the contrary CONFIG_FEC_SHARED_PHY in the
linux kernel.
Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
For CONFIG_SYS_BOOTCOUNT_SINGLEWORD the code had an endianness problem.
Signed-off-by: Michael Weiss <michael.weiss@ifm.com>
Signed-off-by: Detlev Zundel <dzu@denx.de>
Fix the following compiler problems:
arch/arm/cpu/arm920t/a320/liba320.a(timer.o): In function `udelay':
/home/wd/git/u-boot/work/arch/arm/cpu/arm920t/a320/timer.c:160: multiple definition of `udelay'
lib/libgeneric.a(time.o):/home/wd/git/u-boot/work/lib/time.c:34: first defined here
lib/libgeneric.a(time.o): In function `udelay':
time.c:(.text+0x1c): undefined reference to `__udelay'
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit c7190f028f "mpc83xx:
retain POR values of non-configured ACR, SPCR, SCCR, and LCRR
bitfields" incorrectly shifted <register>_<bitfield> (e.g.
ACR_PIPE_DEP) values that were preshifted by their
definition in mpc83xx.h.
this patch removes the unnecessary shifting for the newly
utilized mask values in cpu_init.c, and prevents seemingly
unrelated symptoms such as an mpc8379erdb board from
locking up whilst performing a networking operation,
e.g. a tftp.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
commit 167cdad137 "SERIAL: Enable
port-mapped access" inadvertently broke 83xx nand boards by
converting NS16550_init to use io accessors, which expanded
the size of the generated code.
this patch fixes the problem by removing icache functions from
the nand builds, which somewhat follows commit
1a2e203b31 "mpc83xx: turn on icache
in core initialization to improve u-boot boot time"
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
SPD has minor change from Rev 1.2 to 1.3. This patch enables Rev 1.3.
The difference has ben examined and the code is compatible.
Speed bins is not verified on hardware for CL7 at this moment.
This patch also enables SPD Rev 1.x where x is up to "F". According to SPD
spec, the lower nibble is optionally used to determine which additinal bytes
or attribute bits have been defined. Software can safely use defaults. However,
the upper nibble should always be checked.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
On the MPC85xx platform if we have SATA its connected on SERDES.
Determing if SATA is enabled via sata_initialize should not be board
specific and thus we move it out of the MPC8536DS board code.
Additionally, now that we have is_serdes_configured() we can determine
if the given SATA port is enabled and error out if its not in the
driver.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The new is_serdes_configured covers a broader range of devices than the
PCI specific code. Use it instead as we convert away from the
is_fsl_pci_cfg() code.
Additionally move to setting LAWs for PCI based on if its configured.
Also updated PCI FDT fixup code to remove PCI controllers from dtb if
they are configured.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Added UPM array table, upmconfig, and Local Bus configuration support for SIMPC8313
Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
With the cpu include paths moved, the gitignore paths need updating.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Tested-by: Tom Rix <tom@bumblecow.com>
This patch consolidates bootcount_{store|load} for PowerPC by
implementing a common version in arch/powerpc/lib/bootcount.c. This
code is now used by all PowerPC variants that currently have these
functions implemented.
The functions now use the proper IO-accessor functions to read/write the
values.
This code also supports two different bootcount versions:
a) Use 2 separate words (2 * 32bit) to store the bootcounter
b) Use only 1 word (2 * 16bit) to store the bootcounter
Version b) was already used by MPC5xxx.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
for 83xx parts
Cc: Michael Zaidman <michael.zaidman@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: Anatolij Gustschin <agust@denx.de>
AMD recently changed the licensing of the RAM sizing code to the
GPLv2 (or at your option any later version)
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
If the board has a high precision mico-second timer, it maked sense to use
it instead of the on-chip one
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Add support for newer (up to 2.6.33) kernels
Add zboot command which takes the address of a bzImage as its first
argument and (optionally) the size of the bzImage as the second argument
(the second argument is needed for older kernels which do not include
the bzImage size in the header)
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
It is possibly to setup x86 boards to use non-PC/AT configurations. For
example, the sc520 is an x86 CPU with PC/AT and non-PC/AT peripherals.
This function allows the board to set itself up for maximum PC/AT
compatibility just before booting the Linux kernel (the Linux kernel
'just works' if everything is PC/AT compliant)
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Currently, the GDT is either located in FLASH or in the non-relocated
U-Boot image in RAM. Both of these locations are unsafe as those
locations can be erased during a U-Boot update. Move the GDT into the
highest available memory location and relocate U-Boot to just below it
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Add a parameter to the 32-bit entry to indicate if entry is from Real
Mode or not. If entry is from Real Mode, execute the destructive 'sizer'
routine to determine memory size as we are booting cold and running in
Flash. If not entering from Real Mode, we are executing a U-Boot image
from RAM and therefore the memory size is already known (and running
'sizer' will destroy the running image)
There are now two 32-bit entry points. The first is the 'in RAM' entry
point which exists at the start of the U-Boot binary image. As such,
you can load u-boot.bin in RAM and jump directly to the load address
without needing to calculate any offsets. The second entry point is
used by the real-to-protected mode switch
This patch also changes TEXT_BASE to 0x6000000 (in RAM). You can load
the resulting image at 0x6000000 and simple go 0x6000000 from the u-boot
prompt
Hopefully a later patch will completely elliminate any dependency on
TEXT_BASE like a relocatable linux kernel (perfect world)
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
This patch allows the low-level assembler boot-strap to obtain the RAM
size without calling the destructive 'sizer' routine. This allows
boot-strapping from a U-Boot image loaded in RAM
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
There is an error in how the assembler version of the sc520 memory size
reporting code works. As a result, it will only ever report at most the
size of one bank of RAM
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Shamelessly steal the Linux x86 crash handling code and shove it into
U-Boot (cool - it fits). Be sure to include suitable attribution to
Linus
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
This avoids a possible overwrite of the (end of) ramdisk by u-boot.
The unused memory region for ppc boot currently starts 1k below the
do_bootm->bootm_start->arch_lmb_reserve stack ptr. This isn't enough since
do_bootm->do_bootm_linux->boot_relocate_fdt calls printf which may
very well use more than 1k stack space.
Signed-off-by: Norbert van Bolhuis <nvbolhuis@aimvalley.nl>
Fix MX51 CPU detect message.
Original string was:
CPU: Freescale i.MX51 family 3.0V at 800 MHz
which can be misinterpreted as 3.0 Volts instead of the silicon revision.
,change it to:
CPU: Freescale i.MX51 family rev3.0 at 800 MHz
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
For code archeologists, this is a nice example of copy and paste history.
Signed-off-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
The QONG module can be downsized and delivered
with 128MB instead of 256MB. The patch adds
run time support for the two different memory
configurations.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Replace call to imx_get_mpllclk with imx_get_armclk
to show frequency of ARM core instead of mpll internal
bus in print_cpuinfo.
Signed-off-by: John Rigby <jcrigby@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
The lowlevel_init file contained some hard-coded values
to setup the RAM. These board related values are moved into
the board configuration file.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Because of s5pc1xx gpio is same as s5p seires SoC,
move gpio functions to drvier/gpio/
and modify structure's name from s5pc1xx_ to s5p_.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Because of other s5p series SoC will use these serial functions,
modify function's name and structure's name.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The MPC83xx SERDES control is different from the other FSL PPC chips.
For now lets split it out so we can standardize on interfaces for
determining of a device on SERDES is configured.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Lan Chunhe <b25806@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
clean up the wrong io_sel for PCI express according to latest manual.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add an extra cycle turnaround time to read->write to ensure stability
at high DDR frequencies.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
add the macro definition for Rtt_Nom termination value for DDR3
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Extend pin control and clock control to GUTS memory map
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
When DDR is in synchronous mode, the existing code assigns sysclk
frequency to DDR frequency. It should be synchronous with the platform
frequency. CPU frequency is based on platform frequency in synchronous
mode.
Also fix:
* Fixes the bit mask for DDR_SYNC (RCWSR5[184])
* Corrects the detection of synchronous mode.
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch fixes error when CONFIG_SYS_NO_FLASH. And adds
nand flash and mmc initialization, which should go before
env initialization.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
Global interrupt should be disabled from the beginning.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
This function return cache-line aligned allocation which is mapped
to uncached io region.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
This patch adds 64 bits swab support. Most 32 bits processors use
this. We need 64 bits swab for UBI.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
This patch allow boards to override the default link script.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
Add common post_word_load/post_word_store routines
for all mpc5121 boards. pdm360ng board POST support
added by subsequent patch needs them.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
PDM360NG is a MPC5121E based board by ifm ecomatic gmbh.
Signed-off-by: Michael Weiss <michael.weiss@ifm.com>
Signed-off-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Configure CONFIG_SYS_MAX_RAM_SIZE address range in
DDR Local Access Window and determine the RAM size.
Fix DDR LAW afterwards using detected RAM size.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Extend mpc512x serial driver to support multiple PSC ports.
Subsequent patches for PDM360NG board support make use of this
functionality by defining CONFIG_SERIAL_MULTI in the board config
file. Additionally the used PSC devices are specified by defining
e.g. CONFIG_SYS_PSC1, CONFIG_SYS_PSC4 and CONFIG_SYS_PSC6.
Support for PSC devices other than 1, 3, 4 and 6 is not added
by this patch because these aren't used currently. In the future
it can be easily added using DECLARE_PSC_SERIAL_FUNCTIONS(N) and
INIT_PSC_SERIAL_STRUCTURE(N) macros in cpu/mpc512x/serial.c.
Additionally you have to add code for registering added
devices in serial_initialize() in common/serial.c.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Subsequent patch extends mpc512x serial driver to support
multiple PSC ports. The driver will provide an uninit()
function to stop the serial controller and to disable the
controller's clock. Adding uninit() entry to struct serial_device
allows disabling the serial controller after usage of
a stdio serial device.
This patch adds uninit() entry to the struct serial_device
and fixes initialization of this structure in the code
accordingly.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
before, MPC8349ITX boots u-boot in 4.3sec:
column1 is elapsed time since first message
column2 is elapsed time since previous message
column3 is the message
0.000 0.000: U-Boot 2010.03-00126-gfd4e49c (Apr 11 2010 - 17:25:29) MPC83XX
0.000 0.000:
0.000 0.000: Reset Status:
0.000 0.000:
0.032 0.032: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.032 0.000: Board: Freescale MPC8349E-mITX
0.032 0.000: UPMA: Configured for compact flash
0.032 0.000: I2C: ready
0.061 0.028: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
1.516 1.456: FLASH: 16 MB
2.641 1.125: PCI: Bus Dev VenId DevId Class Int
2.652 0.011: 00 10 1095 3114 0180 00
2.652 0.000: PCI: Bus Dev VenId DevId Class Int
2.652 0.000: In: serial
2.652 0.000: Out: serial
2.652 0.000: Err: serial
2.682 0.030: Board revision: 1.0 (PCF8475A)
3.080 0.398: Net: TSEC1: No support for PHY id ffffffff; assuming generic
3.080 0.000: TSEC0, TSEC1
4.300 1.219: IDE: Bus 0: .** Timeout **
after, MPC8349ITX boots u-boot in 3.0sec:
0.010 0.010: U-Boot 2010.03-00127-g4b468cc-dirty (Apr 11 2010 - 17:47:29) MPC83XX
0.010 0.000:
0.010 0.000: Reset Status:
0.010 0.000:
0.017 0.007: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.017 0.000: Board: Freescale MPC8349E-mITX
0.038 0.020: UPMA: Configured for compact flash
0.038 0.000: I2C: ready
0.038 0.000: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
0.260 0.222: FLASH: 16 MB
1.390 1.130: PCI: Bus Dev VenId DevId Class Int
1.390 0.000: 00 10 1095 3114 0180 00
1.390 0.000: PCI: Bus Dev VenId DevId Class Int
1.400 0.010: In: serial
1.400 0.000: Out: serial
1.400 0.000: Err: serial
1.400 0.000: Board revision: 1.0 (PCF8475A)
1.832 0.432: Net: TSEC1: No support for PHY id ffffffff; assuming generic
1.832 0.000: TSEC0, TSEC1
3.038 1.205: IDE: Bus 0: .** Timeout **
also tested on these boards (albeit with a less accurate
boottime measurement method):
seconds: before after
8349MDS ~2.6 ~2.2
8360MDS ~2.8 ~2.6
8313RDB ~2.5 ~2.3 #nand boot
837xRDB ~3.1 ~2.3
also tested on an 8323ERDB.
v2: also remove the delayed icache enablement assumption in arch ppc's
board.c, and add a CONFIG_MPC83xx define in the ITX config file for
consistency (even though it was already being defined in 83xx'
config.mk).
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
marketing didn't extend their postpend-with-an-A naming strategy
on rev.2's and higher beyond the first two 83xx families. This
patch stops us from misreporting we're running e.g., on an MPC8313EA,
when such a name doesn't exist.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Enable eSDHC Clock based on generic CONFIG_FSL_ESDHC define
instead of a platform define. This will enable all the 83xx
platforms to use sdhc_clk based on CONFIG_FSL_ESDHC. It's
the same patch as commit 6b9ea08c50
for the ppc/85xx.
Signed-off-by: Rini <rini@arvoo.nl>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
As discussed on the list, move "arch/ppc" to "arch/powerpc" to
better match the Linux directory structure.
Please note that this patch also changes the "ppc" target in
MAKEALL to "powerpc" to match this new infrastructure. But "ppc"
is kept as an alias for now, to not break compatibility with
scripts using this name.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Anatolij Gustschin <agust@denx.de>
This patch adds new macros, with frequently used combinations of the
4xx TLB access control and storage attibutes. Additionally the 4xx init.S
files are updated to make use of these new macros. Resulting in easier
to read TLB definitions.
Additionally some init.S files are updated to use the mmu header for the
TLB defines, instead of defining their own macros.
Signed-off-by: Stefan Roese <sr@denx.de>
WB cache use different instruction that WT cache but the major code
is that same. That means that wdc.flush on system with WT cache
do the same thing as before.
You need newer toolchain with wdc.flush support.
Signed-off-by: Michal Simek <monstr@monstr.eu>
It is better to read ivr and react on it than do long parsing from
two regs. Interrupt controller returs actual irq number.
Signed-off-by: Michal Simek <monstr@monstr.eu>
I would like to handle case where system doesn't contain
intc that's why I need timer initialization out of intc code.
Signed-off-by: Michal Simek <monstr@monstr.eu>
It is ancient code. There is possible to save several instructions
just if we use offset instead of addik
Signed-off-by: Michal Simek <monstr@monstr.eu>
This patch adds FDT (flattened device tree) support to microblaze arch.
Tested with Linux arch/microblaze kernels with and without compiled in
FDT on Xilinx ML506 board.
Signed-off-by: Arun Bhanu <arun@bhanu.net>
Signed-off-by: Michal Simek <monstr@monstr.eu>
The 440SPe Rev. A is quite old and newer 440SPe boards don't need support
for this CPU revision. Since removing support for this older version
simplifies the creation for newer U-Boot ports, this patch now enables
440SPe > Rev. A support by creating the CONFIG_440SPE_REVA define. By
defining this in the board config header, Rev. A will still be supported.
Otherwise (default for newer board ports), Rev. A will not be supported.
Signed-off-by: Stefan Roese <sr@denx.de>
This helps to clean up the include/ directory so that it only contains
non-architecture-specific headers and also matches Linux's directory
layout which many U-Boot developers are already familiar with.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Also move lib_$ARCH/config.mk to arch/$ARCH/config.mk
This change is intended to clean up the top-level directory structure
and more closely mimic Linux's directory organization.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
