To support the SPI MEM API, instead of modifying the existing U-Boot
driver, this patch adds a port of the existing Linux driver.
This also has the advantage that porting changes and fixes from Linux will
be easier.
Porting of driver left most of the functions unchanged while few of the
changes are:
-Remove lock(mutexes) and irq handler as u-boot is a single core execution.
-Remove invalid masterid as it was required specially for multicore
execution in LS2088ARDB which is not the case in u-boot.
-Remove clock support as changing spi speed is not supported in uboot and
nor in linux.
Currently tested on LS1088ARDB, LS1012ARDB, LS1046ARDB, LS1046AFRWY,
LS1043AQDS, LS1021ATWR, LS2088ARDB, I.MX6ULL EVK.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
The write data size can be overwritten by writing to the IDATSZ
field of IPCR register. Since the driver always updates the IDATSZ
in page program operation. Set the LUT data size to 0 to align
the codes with iMX.
Signed-off-by: Ye Li <ye.li@nxp.com>
On latest iMX platforms like iMX7D/iMX6UL/iMX8MQ, the QSPI controller
is updated to have TDH field in FLSHCR register. According to reference
manual, this TDH must be set to 1 when DDR_EN is set. Otherwise, the TX
DDR delay logic won't be enabled.
Another issue in DDR mode is the MCR register will be overwritten in
every read/write/erase operation. This causes DDR_EN been cleared while
TDH=1, then no clk2x output for TX data shift and all operations will
fail.
Signed-off-by: Ye Li <ye.li@nxp.com>
Use readl_poll_timeout instead of explicit calculation
Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
During QSPI reads, current is_controller_busy function sporadically
fails with -ETIMEDOUT due to fixed number of 5 test loops. Using
timer functions to wait 1000 us instead will fix this.
Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Convert fsl_qspi.c to complete DM mode.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Tested-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Tested-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
In
void *rx_addr = NULL;
rx_add = A;
the first assignment has no effect. Remove it.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Some SoCs have different endianness of QSPI IP if compared
to endianness of core. The function is_controller_busy()
checks if the QSPI controller is busy or not, considering
the endianness of the QSPI IP.
Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.
Signed-off-by: Tom Rini <trini@konsulko.com>
wait_for_bit callers use the 32 bit LE version
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The QSPI module on i.MX7D is modified from i.MX6SX. The module used on
i.MX6UL/6ULL is reused from i.MX7D. They share same tx buffer size.
The endianness is not set at qspi driver initialization. So if we don't
boot from QSPI, we will get wrong endianness when accessing from AHB
address directly.
Add the compatible entry for 6ul/7d.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
In some of the QSPI controller version, there must be atleast
128bit data available in TX FIFO for any pop operation otherwise
error bit will be set. The code will not make any behavior change
for previous controller as the transfer data size in ipcr register
is still the same.
Patch is tested on LS1046A which do not require 16 bytes aligned and
LS1088A which require 16 bytes aligned data in TX FIFO
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Anupam Kumar <anupam.kumar_1@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
It is recommended to check either controller is free to take
new spi action. The IP_ACC and AHB_ACC bits indicates that
the controller is busy in IP or AHB mode respectively.
And the BUSY bit indicates that controller is currently
busy handling a transaction to an external flash device
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Pet the watchdog once upon each command call (qspi_xfer) and during
each loop iteration in several commands.
This fixes a watchdog reset especially during erase command.
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Reviewed-by: York Sun <york.sun@nxp.com>
SOC’s like LS1012A has only one chip select signal for QSPI flash.
Avoid scanning other flash.
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.
Signed-off-by: Simon Glass <sjg@chromium.org>
The signature for this macro has changed. Bring in the upstream version and
adjust U-Boot's usages to suit.
Signed-off-by: Simon Glass <sjg@chromium.org>
Update to drivers/power/pmic/palmas.c:
Signed-off-by: Keerthy <j-keerthy@ti.com>
Change-Id: I6cc9021339bfe686f9df21d61a1095ca2b3776e8
The endianness can be changed by RCW + PBI sequence. It may have
other than power on reset value.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Yuan Yao <yao.yuan@nxp.com>
CC: Peng Fan <peng.fan@nxp.com>
CC: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Warnins log:
drivers/spi/fsl_qspi.c: In function ‘qspi_ahb_read’:
drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The flash type of LS2085AQDS QSPI is S25FS256S. It has special write
any device register command and read any device register command.
This patch enable support for those commands.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
QSPI controller automatic enable the chipselect signal according the
dest AMBA memory address. Now we distribute the AMBA memory zone
averagely to every chipselect slave device according chipselect
numbers got from dts node.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The address value and size value get from dts "reg" property have
type of u64 on arm64. If we assign those values to "u32" variables,
driver can't work correctly. Converting the type of those variables
to fdt_xxx_t.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
In current driver, we always copy 4 bytes to the dest memory.
Actually the dest memory may be shorter than 4 bytes.
Add an argument to indicate the dest memory length.
Avoid writing memory outside of the bounds.
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
In current driver everytime we memcpy 4 bytes to the dest memory
regardless of the remaining length.
This patch adds checking the remaining length before memcpy.
If the length is shorter than 4 bytes, memcpy the actual length of data
to the dest memory.
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch fixes the following compile warning:
drivers/spi/fsl_qspi.c: In function 'fsl_qspi_probe':
drivers/spi/fsl_qspi.c:937:15:
warning: cast to pointer from integer of different size
[-Wint-to-pointer-cast]
priv->regs = (struct fsl_qspi_regs *)plat->reg_base;
^
Just make the cast explicit.
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit fixes the change of below commit
"spi: fsl_qspi: Use GENMASK"
(sha1 :bad490a24212c068c5b718b9189f47ea4075d078)
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
When reading a large blob. e.g. a linux kernel (several MiBs) a watchdog
timeout might occur meanwhile. So pet the watchdog while operating on
the flash.
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Replace numeric mask hexcodes with GENMASK macro
in fsl_qspi
Cc: York Sun <yorksun@freescale.com>
Cc: Haikun Wang <Haikun.Wang@freescale.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Replace numerical bit shift with BIT macro
in fsl_*spi.c
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: York Sun <yorksun@freescale.com>
Cc: Haikun Wang <Haikun.Wang@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
The current name is inconsistent with other driver model data access
functions. Rename it and fix up all users.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Move the Freescale QSPI driver over to driver model.
Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Tested-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>
The QSPI controller in i.MX 6SoloX and Vybrid supports reading data using
IP register and AHB bus.
The original driver only supports reading data from IP interface. The IC
team suggests to use AHB read which is faster then IP read. Using AHB read,
we can directly memcpy, a "missed" access to the buffer will cause the
controller to clear the buffer and use the SEQID stored in bfgencr register
to initiate a read from flash device.
Since AHB bus is 64 bit width, we can not set MCR register using 32bit. In
order to minimize code change, redefine QSPI_MCR_END_CFD_LE to 64bit Little
endian but not 32bit Little endia.
Introduce a new configuration option CONFIG_SYS_FSL_QSPI_AHB. If want to
use AHB read, just define CONFIG_SYS_FSL_QSPI_AHB. If not, just ignore it.
Actually if Vybrid is migrated to use AHB read, this option can be removed and
IP read function can be discared. The reason to introduce this option
is that only i.MX SOC is tested in my side, no Vybrid platform for me.
In spi_setup_slave, the original piece code to set AHB is deleted, since
Vybrid platform does not use this to intiate AHB read. Instead, add
qspi_init_ahb_read function if defined CONFIG_SYS_FSL_QSPI_AHB.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
To support bigger than 16MB size qspi flashes, spi framework uses bank
switch to access higher bank or lower bank.
In this patch, QSPI_CMD_BRRD, QSPI_CMD_BRWR, QSPI_CMD_WREAR, QSPI_CMD_RDEAR
is initialized in LUT register with related pad and length configuration.
qspi_op_pp is originally for page programming, this patch reuses this function
for bank register switch and renamed it with qspi_op_write.
Since bank or EAR register is only 1 byte length, however original qspi_op_pp
or now renamed qspi_op_write only support 4 bytes lenght as the access unit,
this will trigger data abort exception when access EAR or bank register.
This is because upper framework passes a 1 bytes pointer to qspi_op_write,
however qspi_op_write treat it as an int pointer. This patch fixes this for
accessing EAR or bank register.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Add 4k erase command support for qspi driver. reuse the 64k erase function,
but change the function name from qspi_op_se to qspi_op_erase, since it
supports 64k and 4k erase.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
According cs, use different amba_base to choose the corresponding
flash devices. If not, `sf probe 1:0` and `sf probe 1:1` will
choose the same flash device, but not different flash devices.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Use QSPI_CMD_xx instead of flash opcodes
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
