From Sentinel FW v0.0.9-9df0f503, the response message of get info API
is changed to add OEM SRK and some states (IMEM, CSAL, TRNG).
With old structure, we get failure from sentinel due to the buffer
size can't fit with new response message. So update the API structure
to fix the issue.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This patch is used to support DBD owner fuse changed to S400 only.
The XRDC PDAC2 for LPAV pbridge5 and MSC1/2/3 for GPIO and LPAV are not
configured by S400 default setting. So these PDAC and MSC are invalid,
only DBD owner can access the corresponding resources.
We have to configure necessary PDAC and MSC for SPL before DDR
initialization.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
To clean the upower codes by aligning codes format, check err_code
and add detail bits list for the memory magic number
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The swton indicates the logic switch, magic number 0xfff80 is hard
to understand, so use macro.
Some board design may not have MIPI_CSI voltage input connected per
data sheet. In that case, the upower power on API may dead loop mu to wait
response, however there is no response. So remove MIPI_CSI here, let
linux power domain driver to runtime enable the power domain.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
At present, in cgc1_pll3_init we don't set the pll3pfd div values,
just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2
to 1 and pfd2div1 to 3.
This finally causes some clocks' rate decreased, for example USDHC.
So clear the PLL3DIV_PFD dividers to get correct rate.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Some space in SRAM0 will be protected by S400 to allow RX SecPriv mode
access only for boot purpose. Since SW will reuse the SRAM0 as SCMI
buffer and SPL container loading buffer, need to reconfigure MRC3.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Need to add DRAM access permission for S400, as S400 needs to access
it When SPL calls image authentication
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
To fit the DBD_EN fused part, we re-design the TRDC and XRDC assignment.
M33 will be the TRDC owner and needs to configure TRDC. A35 is the
XRDC owner, ATF will configure XRDC.
The handshake between U-boot and M33 image is used to sync TRDC and
XRDC configuration completion. Once the handshake is done, A35 and M33
can access the allowed resources in others domain.
The handshake is needed when M33 is booted or DBD_EN fused, because both
cases will enable the TRDC. If handshake is timeout, the boot will hang.
We use SIM GPR0 to pass the info from SPL to u-boot, because before the
handshake, u-boot can't access SEC SIM and FSB.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
As M33 is responsible for TRDC configuration, the settings for A35
nonsecure world access and DMA0 access are moved to M33 image.
So remove the codes to release TRDC and configure it. Just keep
the configurations for reference.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
iMX8ULP A1 S400 ROM removes the setting for MRC4/5. So we have to set
them in SPL to allow access to DDR from A35 and APD PER masters
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Since A1 ROM has fixed the ROM API eMMC issue, we should only use
the workaround for A0.1 part. Add a SOC revision check.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
In both SPL and u-boot, after probing the S400 MU, get the chip revision,
lifecycle and UID from Sentinel.
Update get_cpu_rev to use the chip revision not hard coded it for A0
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Since latest DTS has added multiple MU nodes, using compatible
string to find the device node is not proper. It finds the first
node with the compatible string matched even the node is disabled.
Signed-off-by: Ye Li <ye.li@nxp.com>
While this change is correct for v2023.04 it is not correct for next
(where this is right now) nor post-v2023.04.
This reverts commit 8653e5d3b7.
Signed-off-by: Tom Rini <trini@konsulko.com>
When we do not enable DISTRO_DEFAULTS (generally, to get distro_bootcmd)
we instea do want to imply BOOTSTD_DEFAULTS so that when using bootstd
the general distro boot functionality will still work.
Signed-off-by: Tom Rini <trini@konsulko.com>
These board have moved to standard boot but the old 'distro_bootcmd'
command is still active. Disable DISTRO_DEFAULTS to fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.
Fixes: e23cae3080 ("x86: som-db5800-som-6867: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.
Fixes: 5d1c8342ae ("x86: dfi-bt700: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.
Fixes: 388f93f963 ("x86: conga-qeval20-qa3-e3845: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.
Fixes: f38be30868 ("x86: bayleybay: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.
Add documentation on how to make this change safely.
Fixes: 66e2c665f3 ("x86: minnowmax: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Documenation:
* add man-page for efi command
UEFI:
* Let EFI app call ExitBootServices() before legacy booting kernel
* Support zboot and bootm in the EFI app
* Let efi command show configuration tables
* Support booting a 64-bit kernel from 64-bit EFI app
* Allocate device-tree copy from high memory
* simplify efi_str_to_u16()
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEbcT5xx8ppvoGt20zxIHbvCwFGsQFAmQfHDAACgkQxIHbvCwF
GsRCWg/8DOCb1igYd8D2nnCTfNEQRkkRvOyc8W3O687fX04e9N3eV8eEFvgBnecL
zF2OT+VmQPq2eWIopOfqCWrIFDr1sbSUAdcPT8aM3s/2/ONFTnnUsvt8G3Qp8vyY
nY+M466bl8Fh841aGtmqsuwBHTddjF8WFUcsj2FAG3laHbnSsVANHDPhSe7C6Fg+
g3FtXZf51SEudTTK8RLa/+df4tji/UX0BLOIr6JZ+xqb+y/Tg/P2N5DAqIQCBTL1
BZ7U/yVXs8M9MHU8T5TtshUL1WvFogbZYkx1kRAH3Rkg0ArD1rxV0Xd64Gmrdoyi
71filEFNV860ytsxBjCbE+YaczqRR1oteyPlak0ApmGf+FRKIU047hpuS2RBsJqv
g1xZg9EsoU4wbsOfVd7FHER63YGPfmH9pa5A5ULpq60tYuoTthToV1up2XVjxiZm
hSxWGmz7dzMlqtuJiKm1R2Nug4N6a+SPSA+l8JDWSBxXZ5Ld5HZaZ99DR+phYcbE
nzZfIePoPq8JCVb7vMpIi7m1MdUEjNUNAWEjHa1Gug71qbgULQ4mi+z192F+h51E
HQ8qs+T6GFzFBrNPrem4wxfNa3UeBQzyTbYiaAcQgSuY942jn9ZrZ78epZbBbPCI
r6LSgBlmtkQoyuPzgk6oX7NRU7Mqd9jOEQaWo7RF8LjdO5UgIrM=
=a5J7
-----END PGP SIGNATURE-----
Merge tag 'efi-next-20230325' of https://source.denx.de/u-boot/custodians/u-boot-efi into next
Pull request for efi-next-20230325
Documenation:
* add man-page for efi command
UEFI:
* Let EFI app call ExitBootServices() before legacy booting kernel
* Support zboot and bootm in the EFI app
* Let efi command show configuration tables
* Support booting a 64-bit kernel from 64-bit EFI app
* Allocate device-tree copy from high memory
* simplify efi_str_to_u16()
When running the EFI app, we need to exit boot services before jumping
to Linux.
At some point it may be possible to jump to Linux and pass on the system
table, and:
* install the device-tree as configuration table
* use LoadImage() to load the kernel image (e.g. from memory)
* start the image with StartImage()
This should allow the Linux efistub to be used. For now, this is not
implemented.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add the missing code to handle this. For a 64-bit kernel the entry
address is 0x200 bytes after the normal entry.
Rename the parameter to boot_linux_kernel() accordingly. Update the
comments to indicate that these are addresses, not pointers.
Signed-off-by: Simon Glass <sjg@chromium.org>
The U-Boot EFI app can run as a 64-bit program, so set the Kconfig
correctly in that case. Make sure it doesn't build SPL, since there is
no need to switch from 32 to 64 bit when running.
Signed-off-by: Simon Glass <sjg@chromium.org>
- Fixes for booting newer revs of the SoC in the Raspberry Pi 4
- Propagate some firmware DT properties to the loaded DT
- Update the Zero2W upstream DT name
Newer firmware can manage the SDCDIV clock divisor register, allowing
the divisor to scale with the core as necessary.
Leverage this ability if the firmware supports it.
Adapted from the following raspberrypi Linux kernel commit:
bcm2835-sdhost: Firmware manages the clock divisor
08532d242d
Signed-off-by: Vincent Fazio <vfazio@xes-inc.com>
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
In rpi-firmware 25e2b597ebfb2495eab4816a276758dcc6ea21f1,
the GET_CLOCK_RATE mailbox property was changed to return the last
value set by SET_CLOCK_RATE.
https://github.com/raspberrypi/firmware/issues/1619#issuecomment-917025502
Due to this change in firmware behavior, bcm2835_get_mmc_clock now
returns a clock rate of zero since we do not issue SET_CLOCK_RATE.
This results in degraded MMC performance.
SET_CLOCK_RATE fixes the clock to a specific value and disables scaling
so is not an ideal solution.
Instead, fallback to GET_MAX_CLOCK_RATE in bcm2835_get_mmc_clock if
GET_CLOCK_RATE returns zero.
Signed-off-by: Vincent Fazio <vfazio@xes-inc.com>
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Same change as was done for mvebu in commit 5bb2c550b1 ("arm: mvebu: Move
internal registers in arch_very_early_init() function") but for kirkwood.
Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
CONFIG_SF_DEFAULT_SPEED is used in SPL SPI to configure and probe the
flash device during DM SPI uclass probing process, if the
spi-max-frequency is not available in the DTB. Currently the max
frequency is not available, because of the probing mechanism in SPI
uclass has not been fully updated to DM.
The CONFIG_SF_DEFAULT_SPEED is set to 1Mhz if a board defconfig
does not specify it. This speed is too slow and result in a few
seconds delay while the u-boot image is loaded from flash. Based on a
survey of the device tree specifications for MVEBU boards, a sane default
value should be 10Mhz. The default of 10Mhz enables an almost
instantaneously loading of the u-boot image.
Note that this patch depends on this patch series (has been merged to
u-boot-marvell/next):
https://lists.denx.de/pipermail/u-boot/2023-March/511038.html
- RESEND: correct spelling of SF_DEFAULT_MODE
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
We did not add a prototype for spl_mmc_get_uboot_raw_sector to
include/spl.h before, so add and document one now. Correct the incorrect
prototype in board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c and
ensure that we have spl.h where we define a non-weak
spl_mmc_get_uboot_raw_sector as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
Some platforms were not including <cpu_func.h> which sets the prototype
for reset_cpu, and in turn had it set wrong. Correct these cases.
Signed-off-by: Tom Rini <trini@konsulko.com>
On high security devices, ROM enables firewalls to protect the OCSRAM
region access during bootup. Only after TIFS has started (and had
time to disable the OCSRAM firewall region) will we have write access to
the region.
So, move scratch board area to HSM RAM.
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
To make sure the panic and the reset messages will go out, console flush() should be used.
Sleep periods do not work in early u-boot phase when timer driver is not initialized yet.
Reference: https://lists.denx.de/pipermail/u-boot/2023-March/512233.html
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
The Rockchip timer driver has been renamed after the fall back compatible.
There's no need to replace the timer compatible in rk3188-radxarock-u-boot.dtsi
anymore, so remove.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable SPL on RK3588 to detect which device it was booted from.
Fixes use of same-as-spl in u-boot,spl-boot-order prop.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Running U-Boot from eMMC on a ROCK 3 Model A result in the following:
U-Boot SPL 2023.04-rc3 (Mar 11 2023 - 17:24:48 +0000)
Trying to boot from MMC1
Card did not respond to voltage select! : -110
spl: mmc init failed with error: -95
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
The sdhci node is missing in board device tree, sync device tree from
linux v6.3-rc1 to fix booting from eMMC. Also disable sdmmc2 and uart1
nodes related to using a WiFi and BT module in the M2 slot.
Fixes: b44c54f600 ("arm64: dts: rockchip: rk3568: Add Radxa ROCK 3 Model A board support")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The boot source node path for emmc is using the old sdhci name.
Replace with correct mmc name and also add same-as-spl to boot order.
Fixes: 0d61f8e5f1 ("rockchip: rk3568: add boot device detection")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Running U-Boot on a ROCK 3 Model A result in the following:
No serial driver found
resetting ...
no sysreset
### ERROR ### Please RESET the board ###
Replace bootph- props with u-boot,dm- props to fix this.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
There are multiple shared Kconfig options between R-Car Gen3 and Gen4.
Keep the common options in Kconfig.64 and move the R-Car Gen3 specific
options into separate Kconfig.rcar3 . The Kconfig.rcar3 contains SoC
and board list, which is limited to R-Car Gen3.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Introduce common Kconfig symbol for 64bit R-Car platforms and move
common configuration options into it. This is preparatory patch to
prevent duplication of Kconfig lists later on, when Gen4 is added.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Pull the SYS_SOC Kconfig option to avoid duplication of this option
in Kconfig.{32,64,rza1} . The default value is the same, so just set
it in one location.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Switch ifdef in rmobile_get_prr() to IS_ENABLED() macro.
The CONFIG_RCAR_GEN3 will never have SPL counterpart, so
the IS_ENABLED() macro is the right one here. No functional
change, except for improved build test coverage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
