Commit graph

18 commits

Author SHA1 Message Date
York Sun
3d75ec95f5 driver/ddr: Fix DDR register timing_cfg_8
The field wrtord_bg should add 2 clocks if on the fly chop is enabled,
according to DDR controller manual for DDR4.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:55 -07:00
York Sun
8340e7ac86 driver/ddr: Fix DDR4 driver for ARM
Previously the driver was only tested on Power SoCs. Different barrier
instructions are needed for ARM SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
York Sun
353527d527 driver/ddr/fsl: Fix printing unspecified module info for DDR4
The offset of module information is at 128, different from DDR3.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-06-05 13:45:07 -07:00
York Sun
9855b3beca powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-06-05 13:45:07 -07:00
Simon Glass
e1bf824dfd Add cli_ prefix to readline functions
This makes it clear where the code resides.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-05-29 17:45:31 -04:00
Simon Glass
18d66533ac move CLI prototypes to cli.h and add comments
Move the CLI prototypes from common.h to cli.h as part of an effort to
reduce the size of common.h.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-05-29 17:45:31 -04:00
Tang Yuantian
aade20046b mpc85xx/t104x: Add deep sleep framework support
When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
York Sun
349689b802 drivers/ddr: Fix possible out of bounds error
This is a theoretical possible out of bounds error in DDR driver. Adding
check before using array index. Also change some runtime conditions to
pre-compiling conditions.

Signed-off-by: York Sun <yorksun@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
York Sun
34e026f9b1 driver/ddr/fsl: Add DDR4 support to Freescale DDR driver
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
York Sun
6b1e1254f3 driver/ddr: Add 256 byte interleaving support
Freescale LayerScape SoCs support controller interleaving on 256 byte size.
This interleaving is mandoratory.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-02-21 11:06:13 -05:00
York Sun
6b9e309a8a Driver/ddr: Add support of different DDR base address
DDR base address has been the same from the view of core and DDR
controllers. This has changed for Freescale ARM-based SoCs. Controllers
setup DDR memory in a contiguous space and cores view it at separated
locations.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-02-21 11:06:13 -05:00
York Sun
4e5b1bd0df driver/ddr: Change Freescale ARM DDR driver to support both big and little endian
Initially it was believed the DDR controller on Freescale ARM would have
big endian. But some platform will have little endian.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-02-21 11:06:13 -05:00
York Sun
76356eb57c powerpc/mpc85xx: Revise workaround for DDR-A003
Existing workaround only handles one RDIMM on reference design. In case
of two RDIMMs being used, the workaround requires two separate writes to
DDR_SDRAM_MD_CNTL register.

This patch also restores two debug registers changed by the workaround.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Ben Collins <ben.c@servergy.com>
CC: James Yang <James.Yang@freescale.com>
2014-01-21 13:40:52 -08:00
York Sun
00ec3fd211 Driver/DDR: Update DDR driver to allow non-zero base address
The DRAM base has been zero for Power SoCs. It could be non-zero
for ARM SoCs. Use a macro instead of hard-coding to zero.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:47 -08:00
York Sun
d4263b8adb powerpc/mpc8xxx: Extend DDR registers' fields
Some DDR registers' fields have expanded to accommodate larger values.
These changes are backward compatible. Some fields are removed for newer
DDR controllers. Writing to those fields are safely ignored.

TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE
automatically. It was a misunderstanding in commit c360ceac.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:46 -08:00
York Sun
9ac4ffbde1 Driver/DDR: Add Freescale DDR driver for ARM
Make PowerPC specific code conditional so ARM SoCs can reuse
this driver. Add DDR3 driver for ARM.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:46 -08:00
York Sun
9a17eb5b7e Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx
Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3
structure for 83xx, 85xx and 86xx.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:46 -08:00
York Sun
5614e71b49 Driver/DDR: Moving Freescale DDR driver to a common driver
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:43 -08:00