Commit graph

321 commits

Author SHA1 Message Date
Stefano Babic
fb87a1ed92 MX51: Add register definitions
The patch add header files to support the Freescale i.MX51
processor, setting definitions for internal registers.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fred Fan <fanyefeng@gmail.com>
2010-03-07 12:36:35 -06:00
Stefano Babic
64fdf452a8 MX51: Add initial support for the Freescale MX51
The patch add initial support for the Freescale i.MX51 processor
(family arm cortex_a8).

Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fred Fan <fanyefeng@gmail.com>
2010-03-07 12:36:35 -06:00
Tom Rix
5f35348409 ARM Update mach-types
Fetched from http://www.arm.linux.org.uk/developer/machines/download.php
And built with

repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
commit aea187c46f7d03ce985e55eb1398d0776a15b928

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2010-03-07 12:36:35 -06:00
Achim Ehrlich
7c966a8bdf ARM change name of defines for AT91 arm926ejs
Configuration defines should be preceeded with CONFIG_SYS_. Renamed
some at91 specific defines to conform to this naming convention:

AT91_CPU_NAME to CONFIG_SYS_AT91_CPU_NAME
AT91_MAIN_CLOCK to CONFIG_SYS_AT91_MAIN_CLOCK

Signed-off-by: Achim Ehrlich <aehrlich@taskit.de>
2010-03-07 12:36:35 -06:00
Nick Thompson
37cffdad06 da830evm: Add support for TI EMAC
Adds support for ethernet networking on the da830evm platform.

This platform uses an SoC EMAC interface and a 3 port ethernet
switch as a PHY with an RMII interface. The PHY also has a i2c
interface for configuring the switch functions.

Signed-off-by: Nick Thompson <nick.thompson@ge.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-03-07 12:36:35 -06:00
Jens Scharsig
6799a80f76 new at91_emac network driver (NET_MULTI api)
* add's at91_emac (AT91RM9200) network driver (NET_MULTI api)
 * enable driver with CONFIG_DRIVER_AT91EMAC
 * generic PHY initialization
 * modify AT91RM9200 boards to use NET_MULTI driver
 * the drivers has been tested with LXT971 Phy and DM9161 Phy at MII and RMII
   interface

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
2010-02-12 12:36:04 -06:00
Jens Scharsig
98250e8e17 prepare joining at91rm9200 into at91
* prepare joining at91 and at91rm9200
 * add modified copy of soc files to cpu/arm920t/at91 to make
   possible to compile at91rm9200 boards in at91 tree instead
   of at91rm9200
 * add header files with c structure defs for AT91 MC, ST and TC
 * the new cpu files are using at91 c structure soc access
 * please read README.soc-at91 for details

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
2010-02-12 12:31:55 -06:00
Jens Scharsig
ea8fbba731 add a new AT91 GPIO driver
* add a real AT91 GPIO driver instead of header inline code
* resolve the mixing of port and pins
* change board config files to use new driver
* add macros to gpio to realize backward compatibility

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
2010-02-12 12:31:54 -06:00
Jens Scharsig
5d8e359c38 add c structures for SoC access
* add's c structures for SoC access to pheriperials head files

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
2010-02-12 12:31:54 -06:00
Nick Thompson
6228e6389e Davinci: Add EMIF-A macros for setting chip select parameters
The patch adds EMIF-A macros for setting chip select parameters

Signed-off-by: Nick Thompson <nick.thompson@ge.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-02-12 12:31:54 -06:00
Alessandro Rubini
c50a0f5039 EP93xx: fix syscon_regs definition
The structure was missing a reserved entry (not listed in the manual,
actually), so the last registers had a wrong offset. This prevented
all swlocked registers to be modified as swlock is last in the structure.

Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
2010-02-12 12:31:54 -06:00
Matthias Kaehlcke
fcfb632bd1 ARM: Add support for EP93xx SoCs
Add support for the Cirrus EP93xx platform

Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
Acked-by: Tom <Tom.Rix@windriver.com>
2010-02-12 12:31:54 -06:00
Tom Rix
632e1d9014 OMAP3 Move declaration of gpmc_cfg.
Every omap3 board config file declared the global variable gpmc_cfg.
This changes moves the declaration to a better location in the
arch dependent header file cpu.h.

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-02-12 12:31:53 -06:00
Jens Scharsig
c041e9d212 new at91_emac network driver (NET_MULTI api)
* add's at91_emac (AT91RM9200) network driver (NET_MULTI api)
* enable driver with CONFIG_DRIVER_AT91EMAC
* generic PHY initialization
* modify AT91RM9200 boards to use NET_MULTI driver
* the drivers has been tested with LXT971 Phy and DM9161 Phy at
  MII and RMII interface

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-01-31 22:37:12 -08:00
Nick Thompson
d7e354374c TI: DaVinci: Updating EMAC driver for DM365, DM646x and DA8XX
The EMAC IP on DM365, DM646x and DA830 is slightly different
from that on DM644x. This change updates the DaVinci EMAC driver
so that EMAC becomes operational on SOCs with EMAC v2.

Signed-off-by: Nick Thompson <nick.thompson@ge.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-01-31 22:37:12 -08:00
Vipin KUMAR
4bfacad4e7 SPEAr : emi controller initialization for CFI driver support
SPEAr310 and SPEAr320 SoCs contain an EMI controller to interface
Paraller NOR flashes. This patch adds the support for this IP

The standard CFI driver is used to interface with NOR flashes

Signed-off-by: Vipin <vipin.kumar@st.com>
2010-01-23 08:15:50 -06:00
Vipin KUMAR
f92994f0f7 SPEAr : Support for HW mac id read/write from i2c mem
This patch adds the  support to read and write mac id from i2c
memory.
For reading:
	if (env contains ethaddr)
		pick env ethaddr
	else
		pick ethaddr from i2c memory
For writing:
	chip_config ethaddr XX:XX:XX:XX:XX:XX writes the mac id
	in i2c memory

Signed-off-by: Vipin <vipin.kumar@st.com>
2010-01-23 08:15:49 -06:00
Vipin KUMAR
566c9c16fe SPEAr : Support added for SPEAr600 board
SPEAr600 SoC support contains basic spear600 support along with the
usage of following drivers
- serial driver(UART)
- i2c driver
- smi driver
- nand driver(FSMC)
- usbd driver

Signed-off-by: Vipin <vipin.kumar@st.com>
2010-01-23 08:15:49 -06:00
Vipin KUMAR
165fa406ad SPEAr : nand driver support for SPEAr SoCs
SPEAr SoCs contain an FSMC controller which can be used to interface
with a range of memories eg. NAND, SRAM, NOR.
Currently, this driver supports interfacing FSMC with NAND memories

Signed-off-by: Vipin <vipin.kumar@st.com>
2010-01-23 08:15:49 -06:00
Vipin KUMAR
a6e34f76c5 SPEAr : smi driver support for SPEAr SoCs
SPEAr SoCs contain a serial memory interface controller. This
controller is used to interface with spi based memories.
This patch adds the driver for this IP.

Signed-off-by: Vipin <vipin.kumar@st.com>
2010-01-23 08:15:49 -06:00
Vipin KUMAR
2403f8f417 SPEAr : i2c driver support added for SPEAr SoCs
SPEAr SoCs contain a synopsys i2c controller.
This patch adds the driver for this IP.

Signed-off-by: Vipin <vipin.kumar@st.com>
2010-01-23 08:15:49 -06:00
Vipin KUMAR
81c0ebf623 SPEAr : Adding basic SPEAr architecture support.
SPEAr Architecture support added. It contains the support for
following SPEAr blocks
- Timer
- System controller
- Misc registers

Signed-off-by: Vipin <vipin.kumar@st.com>
2010-01-23 08:15:49 -06:00
Tom Rix
e4c43c20b8 ARM Update mach-types
Fetched from http://www.arm.linux.org.uk/developer/machines/download.php
And built with

repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
commit 2045124ffd1a5e46d157349016a2c50f19c8c91d

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2010-01-23 08:15:49 -06:00
Prafulla Wadaskar
beca04dd24 Kirkwood: Upgated licencing for files imported from linux source to GPLv2 or later
These are few files directly imported from Linux kernel source.
Those are not modifyed at all ar per strategy.
These files contains source with GPLv2 only
whereas u-boot expects GPLv2 or latter

These files are updated for the same from prior permission from original writes

Acked-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2010-01-23 08:15:48 -06:00
Minkyu Kang
d8e5f55475 s5pc1xx: update cache routines
Because of v7_flush_dcache_all is moved to omap3/cache.S
and s5pc110 needs cache routines, update s5pc1xx cache routines.

l2_cache_enable and l2_caceh_disable are moved from cache.c to cache.S
and invalidate_dcache is modified for SoC specific.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2010-01-23 08:15:48 -06:00
Seunghyeon Rhee
17ef9104ae samsung: fix DMC1_MEM_CFG for s3c64xx
The MSB of DMC1_MEM_CFG can be set to '1' for separate CKE control
for S3C6400. In the configuration of SMDK6400, however, two 16-bit
mDDR (SAMSUNG K4X51163) chips are used in parallel to form 32-bit
memory bus and there is no need to control CKE for each chip
separately. AFAIK, CKE1 is not at all connected. Only CKE0 is
used. Futhermore, it should be '0' always for S3C6410. When tested
with a board which has a S3C6410 and the same memory configuration,
a side effect is observed that u-boot command "reset" doesn't work
leading to system hang. Leaving the bit clear is safe in most cases.

Signed-off-by: Seunghyeon Rhee <seunghyeon@lpmtec.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2010-01-23 08:15:48 -06:00
Magnus Lilja
c816dcb118 MX31: Add struct definition for clock control module in i.MX31.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
2010-01-19 17:08:12 -06:00
Wolfgang Denk
2ff6922280 Merge branch 'master' of git://git.denx.de/u-boot-arm 2010-01-12 23:47:03 +01:00
Ajay Kumar Gupta
0b232310b2 DA8xx: Add GPIO register definitions
Added DA8xx GPIO base addresses in gpio_defs.h and pointers
to different BANKs which can be used to program GPIOs.

Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
Signed-off-by: Swaminathan S <swami.iyer@ti.com>
2010-01-09 10:25:07 +01:00
Tom Rix
06f95959bc ARM Update mach-types
Fetched from http://www.arm.linux.org.uk/developer/machines/download.php
And built with

repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
commit c9f937e4a3f4ebf9924ec21d80632e5eb61d949c

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2010-01-06 09:36:24 -06:00
Nick Thompson
26be2c53d6 Davinci: NAND enable ECC even when not in NAND boot mode
Davinci: NAND enable ECC even when not in NAND boot mode

On Davinci platforms, the default NAND device is enabled (for ECC)
in low level boot code when NAND boot mode is used. If booting in
another mode, NAND ECC is not enabled. The driver should make
sure ECC is enabled regardless of boot mode if NAND is configured
in U-Boot.

Signed-off-by: Nick Thompson <nick.thompson@ge.com>
2010-01-04 08:48:17 -06:00
Nick Thompson
97f4eb8cfb Davinci: Configurable NAND chip selects
Davinci: Configurable NAND chip selects

Add a CONFIG_SYS_NAND_CS setting to all davinci configs and
use it to setup the NAND controller in the davinci_nand
mtd driver.

Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
2010-01-04 08:48:17 -06:00
Tom Rix
71636fa7c3 ARM Update mach-types
Fetched from http://www.arm.linux.org.uk/developer/machines/download.php
And built with

repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
commit 3fcca9ac6cbce35b3e81e247d375534117d5f4cd

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-11-29 17:56:36 -06:00
Po-Yu Chuang
43a5f0df2f arm: A320: Add support for Faraday A320 evaluation board
This patch adds support for A320 evaluation board from Faraday. This board
uses FA526 processor by default and has 512kB and 32MB NOR flash, 64M RAM.
FA526 is an ARMv4 processor and uses the ARM920T source in this patch.

Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
2009-11-27 16:26:17 -06:00
Nishanth Menon
d414aae552 OMAP3: Fix SDRC init
Defaults are for Infineon DDR timings.
Since none of the supported boards currently do
XIP boot, these seem to be faulty. fix the values
as per the calculations(ACTIMA,B), conf
the sdrc power with pwdnen and wakeupproc bits

Signed-off-by: Nishanth Menon <nm@ti.com>
2009-11-27 16:26:17 -06:00
Nishanth Menon
30563a04bf OMAP3:SDRC: introduce DDR types
Micron DDR timings based on:
http://www.sakoman.net/cgi-bin/gitweb.cgi?p=x-load-omap3.git;a=blob;f=include/asm/arch-omap3/mem.h;h=e6fbfe3947f5d0d85fea776e30821d4017316d86;hb=HEAD

Introduce Micron DDR timings and provide
CONFIG_OMAP3_INFINEON_DDR and CONFIG_OMAP3_MICRON_DDR config
options to allow for platform files to setup their timings as
per the type of DDR selected

Reported-by: Steve Sakoman in http://www.nabble.com/forum/Permalink.jtp?root=25779518&post=25959734&page=y

Signed-off-by: Nishanth Menon <nm@ti.com>
2009-11-27 16:26:16 -06:00
Nishanth Menon
169a4c804d OMAP3:SDRC: Cleanup references to SDP
Remove SDP referenced unused defines

Signed-off-by: Nishanth Menon <nm@ti.com>
2009-11-27 16:26:16 -06:00
Nick Thompson
bbed056e55 Add TI DA8xx support: DA8xx includes
Provides initial support for TI OMAP-L1x/DA8xx SoC devices.
See http://www.ti.com

The DA8xx devices are similar to DaVinci devices but have a differing
memory map and updated peripheral versions.

Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2009-11-27 16:26:14 -06:00
kevin.morfitt@fearnside-systems.co.uk
ac67804fbb Add a unified s3c24x0 header file
This patch adds a unified s3c24x0 cpu header file that selects the header
file for the specific s3c24x0 cpu from the SOC and CPU configs defined in
board config file. This removes the current chain of s3c24-type #ifdef's
from the s3c24x0 code.

Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2009-11-27 16:26:13 -06:00
kevin.morfitt@fearnside-systems.co.uk
9ebfdc2022 Clean-up of s3c24x0 header files
Cleans up the s3c24x0 header files:

s4c24x0.h: removes the use of 'volatile' from the S3C24X0_REG8,
S3C24X0_REG16 and S3C24X0_REG32 register typedef's. Registers are always
accessed using the IO accessor functions which cast the register address
as 'volatile' anyway so it isn't required here.

s3c2400.h and s3c2410.h: insert a blank line between the static inline
functions

Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
2009-11-27 16:26:13 -06:00
Minkyu Kang
47e801bec3 s3c64xx: move s3c64xx header files to asm-arm/arch-s3c64xx
This patch moves the s3c64xx header files from include/
to include/asm-arm/arch-s3c64xx

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2009-11-27 16:26:13 -06:00
kevin.morfitt@fearnside-systems.co.uk
492fb1fdbc Move s3c24x0 header files to asm-arm/arch-s3c24x0/
This patch moves the s3c24x0 header files from include/ to
include/asm-arm/arch-s3c24x0/.

checkpatch.pl showed 2 errors and 3 warnings. The 2 errors were both due
to a non-UTF8 character in David M?ller's name:

ERROR: Invalid UTF-8, patch and commit message should be encoded in UTF-8
#489: FILE: include/asm-arm/arch-s3c24x0/s3c2410.h:3:
+ * David M?ller ELSOFT AG Switzerland. d.mueller@elsoft.ch

As David's name correctly contains a non-UTF8 character I haven't fixed
these errors.

The 3 warnings were all because of the use of 'volatile' in s3c24x0.h:

WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt
#673: FILE: include/asm-arm/arch-s3c24x0/s3c24x0.h:35:
+typedef volatile u8	S3C24X0_REG8;
+typedef volatile u16	S3C24X0_REG16;
+typedef volatile u32	S3C24X0_REG32;

I'll fix these errors in another patch.

Tested by running MAKEALL for ARM8 targets and ensuring there were no new
errors or warnings.

Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2009-11-27 16:26:12 -06:00
Tom Rix
2d251ccaa9 ARM Update mach-types
Fetched from http://www.arm.linux.org.uk/developer/machines/download.php
And built with

repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
commit 156171c71a0dc4bce12b4408bb1591f8fe32dc1a

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-11-27 16:26:12 -06:00
Tom Rix
d5e2d625c7 ARM Update mach-types.h
From http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm

Commit id 0996391139f43d032335b5360db11da62a2cbb39

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-11-27 16:26:10 -06:00
Dirk Behme
1d2e96de56 OMAP2/3: I2C: Add support for second and third bus
Add support to use second and third I2C bus, too.

Bus 0 is still the default, but by calling i2c_set_bus_num(1/2) before doing
I2C accesses, code can switch to bus 1 and 2, too. Don't forget to switch
back afterwards, then.

Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
2009-11-16 07:25:15 +01:00
Remy Bohmer
25793f76bf ARM: Use Linux version for unaligned access code
The asm-arm/unaligned.h includes linux/unaligned/access_ok.h
This file is unsafe to be used on ARM, since it does an unaligned memory
accesses which fails on ARM.

Lookin at Linux the basic difference seems to be the header
"include/asm-arm/unaligned.h". The Linux version of "unaligned.h"
does *not* include "access_ok.h" at all. It includes "le_byteshift.h"
and "be_byteshift.h" instead.

Signed-off-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Stefan Roese <sr@denx.de>
--
 include/asm-arm/unaligned.h            |    3 -
 include/linux/unaligned/be_byteshift.h |   70 +++++++++++++++++++++++++++++++++
 include/linux/unaligned/le_byteshift.h |   70 +++++++++++++++++++++++++++++++++
 3 files changed, 142 insertions(+), 1 deletion(-)
 create mode 100644 include/linux/unaligned/be_byteshift.h
 create mode 100644 include/linux/unaligned/le_byteshift.h
2009-11-07 15:56:30 -06:00
Wolfgang Denk
4946775c6d Coding Style cleanup; update CHANGELOG, prepare -rc1
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-10-28 00:49:47 +01:00
Minkyu Kang
f380737478 s5pc1xx: SMDKC100: fix compile warnings
fix the following compile warnings
warning: dereferencing type-punned pointer will break strict-aliasing rules

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2009-10-24 09:55:25 -05:00
Sandeep Paulraj
11b0102218 TI DaVinci: Fix DM6467 EVM Compilation Warning
Due to new TI boards being added to U-Boot, the hardware.h
is getting very messy. The warning being fixed is due to
the EMIF addresses being redefined.

The long term solution(after 2009.11) to this is to
have SOC specific header files.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-10-24 09:55:24 -05:00
Nishanth Menon
f8a812aa65 TI OMAP3: make gpmc_config as const
gpmc_config should not be a variant as it is board specific
hence make it a const parameter

Fixes issues identified by Dirk:
- build issue for zoom2
- warnings for all other OMAP3 platforms using nand/onenand etc

Signed-off-by: Nishanth Menon <nm@ti.com>
2009-10-24 09:55:24 -05:00