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OMAP3: Fix SDRC init

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Defaults are for Infineon DDR timings.
Since none of the supported boards currently do
XIP boot, these seem to be faulty. fix the values
as per the calculations(ACTIMA,B), conf
the sdrc power with pwdnen and wakeupproc bits

Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Nishanth Menon 2009-11-09 09:29:34 -05:00 • committed by Tom Rix
parent 30563a04bf
commit d414aae552
2 changed files with 3 additions and 1 deletions
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3
cpu/arm_cortexa8/omap3/mem.c
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@ -164,7 +164,8 @@ void do_sdrc_init(u32 cs, u32 early)
writel(SDRC_SHARING, &sdrc_base->sharing);
/* Disable Power Down of CKE cuz of 1 CKE on combo part */
writel(SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power);
writel(WAKEUPPROC | PWDNEN | SRFRONRESET | PAGEPOLICY_HIGH,
&sdrc_base->power);
writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
sdelay(0x20000);

1
include/asm-arm/arch-omap3/cpu.h
View file

@ -222,6 +222,7 @@ struct sdrc {
#define PAGEPOLICY_HIGH (0x1 << 0)
#define SRFRONRESET (0x1 << 7)
#define PWDNEN (0x1 << 2)
#define WAKEUPPROC (0x1 << 26)
#define DDR_SDRAM (0x1 << 0)