early_board_init has been skipped to avoid SDRAM corruption in the case
that a fully relocatable image has been loaded into SDRAM and is being
executed from SDRAM. x86 is being aligned with other architectures (ARM
and PPC in particlar) and will be using Cache-As-RAM to run a C
environment from Flash (or SRAM if you have some). early_board_init may
be needed to assist in the setup of Cache-As-RAM and the early C
environment
Position independant functionality is due for removal from the x86
architecture, so create two distinct configurations - One for Flash and
one for SRAM
When DDR data rate is higher than 1200MT/s or controller interleaving is
enabled, additional cycle for write-to-read turnaround is needed to satisfy
dynamic ODT timing.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Board EEPROM is used to read/save Ethernet MAC addresses.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We should have been defining the actual board name in the options, not
the processor. Fix this for P1011RDB, P1020RDB, P2010RDB, and P2020RDB.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The "mac id" command is used to initialize the EEPROM data to a specific
format, but it was not updating the CRC. This didn't cause any real
problems, because writing the data to the EEPROM will always update the
CRC anyway, but it did result in a bogus CRC warning.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This is consistent with nios2-linux. And resolved the warning,
cmd_nvedit.c: In function `do_env_export':
cmd_nvedit.c:660: warning: size_t format, ssize_t arg (arg 3)
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
Added this for mmc_spi driver. Though altera spi core does not
support programmable speed. It is fixed when configured in
sopc-builder.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
Board support for the Guntermann & Drunck DLVision-10G.
Adds support for multiple FPGAs per board for gdsys 405ep
architecture.
Adds support for dual link osd hardware for gdsys 405ep.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Use SPMR instead of HRCWL when calculating clocks as HCRWL
may be changed and the CPU will not pick up all changes
until there is a POR. u-boot will think SPMF has changed and get
the clocks wrong.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This patch fix a problem for the pcie enumeration when the mpc83xx
pcie controller is connected with switch or we use both of the two
pcie controller.
Signed-off-by: Leo Liu <liucai.lfn@gmail.com>
fix codingstyle and compiler warning: 'pcie_priv' defined but not used
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
While debugging some USB stuff, I've first missed that there are actually
two defines necessary to get usefull output. The one needed to get debug output
for the communication with HUBs was burried somewhere deep inside the code.
Change that so that a #define DEBUG is enough while still leaving the possibility
to reduce unwanted debug output.
Signed-off-by: Alexander Holler <holler@ahsoftware.de>
I currently don't know if the error could have other consequences
than a wrong output when turning debug on.
Signed-off-by: Alexander Holler <holler@ahsoftware.de>
The P1013 is a single core version of P1022 and thus should use the
p1022_serdes.c code. It was acciently pointing to p1013_serdes.c which
doesn't exist.
Reported-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Using hwconfig to turn on/off ECC, without re-compiling.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Workaround for the following errata:
DDR111 - MCKE signal may not function correctly at assertion of HRESET
DDR134 - The automatic CAS-to-Preamble feature of the DDR controller can
calibrate to incorrect values
These two workarounds must be implemented together because they touch
common registers.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
