To disabled a clock in clock tree initialization for a mux of STM32MP15,
the selected clock source index is set with the latest possible index for
the number of bit used. Today this valid configuration cause a error
in U-Boot messages, for example with CLK_ETH_DISABLED, when this clock
is not needed for the used ETH PHY without crystal:
no parents defined for clk id 123
This patch change the level of this message to avoid this trace for
valid clock tree.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Once all the other drivers got torn down in preparation for the OS
to start, tear down the clock controller last. The clock controller
must be torn down last as some of the clock which get turned off
might have still been needed during the teardown stage of the other
drivers.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Add support to read RK3308 registers used to configure UART clocks, and
thus to get UART rate and baudrate. This fixes clock_get_rate returning
error on serial device probing. Moreover, there is no need anymore to
use 'clock-frequency' property for UART nodes in *-u-boot.dtsi files
for all cases where UART is not inited by U-Boot proper or by SPL o by
TPL code but by a preliminary external boot phase (for Rock PI S, UART
is inited by external TPL).
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
As per definitions of masks and shift offsets in cru_rk3308.h, values
read from registers must be first masked and then shifted. By the way,
this fix is binary invariant, because in all of fixed cases the shift
offset is zero.
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Pine64 Quartz64 boards DT reference SCLK_GMAC1_RGMII_SPEED in the
assigned-clocks property of the gmac1 node. This result in a ENOENT
error when driver core tries to set a parent for this clock.
The clock speed in rgmii/rmii mode is changed using clk_set_rate of the
tx_rx clock and not using clk_set_parent of the speed clock.
Add dummy support for SCLK_GMAC1_RGMII_SPEED and similar clocks to clk
driver to allow a driver for gmac node to probe.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The clock driver for RK3568 does not include support for UART clocks in
SPL. This result in the following message with high enough loglevel.
ns16550_serial serial@fe660000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19
Fix this by including support for UART clocks in SPL.
Fixes: 4a262feba3 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide,
not 5 bits wide as currently defined in CPLL_25M_DIV_MASK.
Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate.
Fixes: 4a262feba3 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Fix use of wrong clk selection for CLK_PWM1 on RK3568.
Fixes: 4a262feba3 ("rockchip: rk3568: add clock driver")
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Handle USB480M clock ID in set_rate() and set_parent()
to allow the dt assigned-clocks and assigned-clock-parents
work on rk3328.dtsi
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Drop the PLL part in SYSCRG driver and separate to be a single
PLL driver of which the compatible is "starfive,jh7110-pll".
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Add gem_tsu and gem0_rx till gem3_rx to return proper register from
zynqmp_clk_get_register. Otherwise firmware won't be able to set clock
for these due to incorrect register address.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230720072859.3724-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
gem0_rx till gem3_rx and gem_tsu are missing from set rate function.
Add them, so that they can be set from pmu firmware via clock framework.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230719084912.30209-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Without CONFIG_CLK, the build fails with the following message:
LD u-boot
aarch64-none-linux-gnu-ld.bfd: drivers/firmware/scmi/scmi_agent-uclass.o: \
in function `scmi_bind_protocols':
.../drivers/firmware/scmi/scmi_agent-uclass.c:79: undefined reference to \
`_u_boot_list_2_driver_2_scmi_clock'
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
There are some newer clocks added to the kernel recently,
so to fix prepare for resycing the device trees, update
the clock list. Since there are some minor changes to
the USB clocks, update which USB clocks are enabled
to match with the upstream kernel as well.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice-gw74xx
There is a problem that the rates of PLL0 and PLL1 are set incorrectly
because the postdiv1_mask value is incorrectly entered when setting
the pll clk reg. Modify postdiv1's mask value to be put correctly.
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
If we're building non FU540/FU740 SoC drivers, then the sifive-prci.o
is not needed. Only build this when CONFIG_CLK_SIFIVE_PRCI is selected.
Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Add fallthrough statement in switch case to fix the sparse warning.
In function 'zynqmp_clk_get_rate': warning: this statement may
fall through [-Wimplicit-fallthrough=]
Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20230519113816.22083-2-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Move imx8 sci header file to include/firmware/imx, then we could
use build macro to reuse some i.MX8 drivers for i.MX9, such as
drivers/cpu/imx8_cpu.c.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
The current DT bindings for the rk3588 clock use a different ID than the
one that is supposed to be written to the hardware registers.
Thus, we cannot use directly the id provided in the phandle, but rather
use a lookup table to correctly setup the hardware.
This approach has been implemented already in Linux, by commit :
f1c506d152ff ("clk: rockchip: add clock controller for the RK3588")
Hence, implement a similar approach using the lookup table, and adapt
the existing reset driver to work with SoCs using lookup table.
The file rst-rk3588.c has been copied as much as possible from Linux.
Adapt the clk rk3588 driver as well to bind the reset driver with the
lookup table.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Clock driver for the Renesas RZ/N1 SoC family. This is based on
Linux kernel 6.2.y drivers/clk/renesas/r9a06g032-clocks.c as found in
commit 02693e11611e ("clk: renesas: r9a06g032: Repair grave increment error"),
with the following additional patch series applied:
https://lore.kernel.org/linux-renesas-soc/20230301215520.828455-1-ralph.siemsen@linaro.org/
Notable difference: this version avoids allocating a 'struct clk'
for each clock source, as this is problematic before relocation.
Instead, it uses the same approach as existing Renesas R-Car Gen2/3
clock drivers, using a temporary structure filled on-the-fly.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add new CONFIG_CLK_RCAR to control compilation of shared code for R-Car
clock drivers (renesas-cpg-mssr.c). Enable this for R-Car Gen2 and 3.
This is necessary so that CONFIG_CLK_RENESAS can be enabled, allowing
recursion into the drivers/clk/reneasas directory, without bringing in
the R-Car support code. The support code contains platform specific
access (TMU_BASE) which is not needed on other Renesas devices such as
RZ/N1.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The CRU is being probed with a default set of assigned clocks, which
are not implemented in the driver at all.
Hence, when clk_set_defaults is called, it fails with ENOENT.
This would not be a problem, as the CRU still handles all the required
clocks, and the assigned clocks are default configs which are preprogrammed
or not required for Uboot operations.
However, the rockchip reset driver is being bound by the same DT node
as CRU, as the reset driver has no DT node.
But, when probing the reset node, it will call again the clk_set_defaults
for the CRU node, and failing because of missing those specific clocks
in the rk3588 clock driver.
To avoid this, simply implement a basic set/get that will just return
success and the default corresponding rate for the required assigned clocks.
As those clocks were not supported in Uboot, not required for Uboot
operations, there is no need to do any different kind of initialization.
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so fix some
debug strings with fdt_addr_t to be able to handle both sizes.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_ptr instead of the devfdt_get_addr function in
the various files in the drivers directory that cast to a pointer.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_index_ptr instead of the devfdt_get_addr_index function
in the various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Please pull the second part of the sunxi pull request for this cycle.
Another bunch of patches that replace old-school U-Boot hacks with
proper DM based code, this time for the raw NAND flash driver, and the
USB PHY VBUS detection code. Plus two smaller patches that were sitting
in my inbox for a while.
Gitlab CI passed. In lack of some supported board with NAND flash I
couldn't really test this part, but apparently this was tested by the
reviewer. I briefly ran the branch on some boards with USB-OTG, and
this still worked.
This pull request adds support for the last CPU board from
CS GROUP France (previously CSSI).
That CPU board called CMPCPRO has a mpc8321E CPU (Family PQII PRO hence
its name) and can be plugged in place of the CMPC885 board.
In order to support that new board, the following changes are included
in this series:
- Make the mpc8xx watchdog driver more generic for reusing it
with mpc83xx
- Fix various small problems on mpc83xx platform
- Add a GPIO Driver for QE GPIOs
- Add support for mpc832x into mpc83xx SPI driver
- Refactor existing board code that will be shared with new board
- Add the new board
Currently NAND clock setup is done in board code, both in SPL and in
U-Boot proper. Add the NAND clocks/resets here so they can be used by
the "full" NAND driver once it is converted to the driver model.
The bit locations are copied from the Linux CCU drivers.
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
- Add rk3588 evb support;
- Update pinctrl for rk3568 and rk3588;
- Update rk3288 dts;
- Update mmc support for rk3568 and rk3588;
- Add rng support for rk3588;
- Add DSI support for rk3568;
- Some other misc fixes in dts, config, driver;
The device tree sdhci node reference the TMCLK_EMMC clock, add limited
support this clock to rk3588 cru driver. Fixes probe of sdhci driver.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
A RK3568 device tree pmic node can reference the I2S1_MCLKOUT_TX clock
in assigned-clocks, add dummy support to set parent of this clock to the
rk3568 cru driver.
Fixes probe of pmic driver and missing regulators on affected boards,
rk3568-evb and rk3568-rock-3a.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Booting from sdmmc on RK3588 currently works because of a workaround in
the device tree, clocks are reordered so that the driver use ciu-sample
instead of ciu, and the BootRom initializes sdmmc clocks before SPL is
loaded into DRAM.
The sdmmc clocks are normally controlled by TF-A using SCMI. However,
there is a need to control these clocks in SPL, before TF-A has started.
This adds a rk3588_scru driver to control the sdmmc clocks in SPL before
TF-A has started, using scru regs. It also adds a small glue driver to
bind the scmi clock node to the rk3588_scru driver in SPL.
Fixes: 7a474df740 ("clk: rockchip: Add rk3588 clk support")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Building U-Boot SPL with CLK_SCMI and SCMI_FIRMWARE Kconfig options
enabled and SPL_FIRMWARE disabled result in the following error.
drivers/clk/clk_scmi.o: in function `scmi_clk_gate':
drivers/clk/clk_scmi.c:84: undefined reference to `devm_scmi_process_msg'
drivers/clk/clk_scmi.c:88: undefined reference to `scmi_to_linux_errno'
drivers/clk/clk_scmi.o: in function `scmi_clk_get_rate':
drivers/clk/clk_scmi.c:113: undefined reference to `devm_scmi_process_msg'
drivers/clk/clk_scmi.c:117: undefined reference to `scmi_to_linux_errno'
drivers/clk/clk_scmi.o: in function `scmi_clk_set_rate':
drivers/clk/clk_scmi.c:139: undefined reference to `devm_scmi_process_msg'
drivers/clk/clk_scmi.c:143: undefined reference to `scmi_to_linux_errno'
drivers/clk/clk_scmi.o: in function `scmi_clk_probe':
drivers/clk/clk_scmi.c:157: undefined reference to `devm_scmi_of_get_channel'
make[1]: *** [scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
make: *** [Makefile:2043: spl/u-boot-spl] Error 2
Add Kconfig option so that CLK_SCMI can be disabled in SPL to fix this.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The rk3288 pwm nodes synced from Linux make use of PCLK_RKPWM
instead of PCLK_PWM. They have the same pclk_cpu parent,
so add PCLK_RKPWM to rk3288_clk_get_rate().
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add clock tables for R8A779G0 V4H SoC from Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")
There is an adjustment to the clock tables to make them easier suitable
for U-Boot, PLL2 is not treated as GEN4 PLL type PLL2_VAR, but rather a
plain PLL2. This should be sufficient until PLL2_VAR is implemented in
the clock core.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228 . Update from CLK to CPG core driver
Treat PLL2 as non-PLL2_VAR for now]
Add clock tables for R8A779F0 S4 SoC
Based on Linux commit 24aaff6a6ce4 ("clk: renesas: cpg-mssr: Add support
for R-Car S4-8") by Yoshihiro Shimoda and sync the tables up to Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228 . Update from CLK to CPG core driver]
Update R-Car Gen4 support in Gen3 clock driver. This patch renames the
V3U clock parts to Gen4 and extends them by new PLL2, PLL3, PLL4, PLL6
as well as SDSRC clock which use undocumented bits so far, and RPCSRC
clock which uses its own more capable divider table. The Gen4 module
standby and reset tables are also updated.
This patch makes use of union to alias Gen3 and more extensive Gen4
PLL tables, as the driver cannot ever be instantiated on hardware
that would identify itself as both Gen3 and Gen4.
The V3U clock driver is updated to match Gen4 clock driver behavior,
it is augmented with a more extensive PLL table and a valid MODEMR
register offset.
This supersedes "clk: renesas: Introduce R-Car Gen4 CPG driver"
from Hai Pham as the R-Car Gen3 and Gen4 clock core drivers are
extremely similar. That implementation was in turn based on Linux
commit 470e3f0d0b15 ("clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver")
by Yoshihiro Shimoda .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
gd->arch.sdhc_clk only exists when CONFIG_FSL_ESDHC is set,
so enclose it inside ifdefs.
gd->arch.qe_clk and gd->arch.brg_clk must be populated when
CONFIG_QE is set.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Add clock for the DWMAC EQoS block. This is used among other things
to configure the MII clock via DM CLK.
Acked-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
