Commit graph

20503 commits

Author SHA1 Message Date
Sean Anderson
821ca608d8 usb: Use the first available device for ehci_gadget
For whatever reason, usb_setup_ehci_gadget removes and probes USB device
0. However, not all systems have a device 0. Use the first device
instead.

The device probed should probably have something to do with the
controller (as specified by e.g. ums <controller> or fastboot
<controller>). In fact, I find it odd that we probe the USB device in
the first place, because this is just to set up the gadget itself.
Presumably, the controller should be probed by usb_gadget_initialize
somehow.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:47:07 -07:00
Simon Glass
a924641632 acpi: Tidy up the item list
At present this is really just a debugging aid, but it is a bit untidy.
Add proper columns and display the type name instead of a number.

Sample output for coral:

   => acpi items
   Seq  Type       Addr  Size  Device/Writer
   ---  -----  --------  ----  -------------
     0  other  79925000    240  0base
     1  other  79925240     40  1facs
     2  dsdt   799252a4     58  board
     3  dsdt   799252fc     10  lpc
     4  other  79925280   32f0  3dsdt
     5  other  79928570   1000  4gnvs
     6  other  79929570    100  5fact
     7  other  79929670     30  5mcfg
     8  other  799296a0     50  5spcr
     9  other  799296f0     50  5tpm2
     a  other  79929740     70  5x86
     b  ssdt   799297d4     fe  maxim-codec
     c  ssdt   799298d2     28  i2c2@16,0
     d  ssdt   799298fa    270  da-codec
     e  ssdt   79929b6a     28  i2c2@16,1
     f  ssdt   79929b92     28  i2c2@16,2
    10  ssdt   79929bba     83  tpm@50
    11  ssdt   79929c3d     28  i2c2@16,3
    12  ssdt   79929c65    282  elan-touchscreen@10
    13  ssdt   79929ee7    285  raydium-touchscreen@39
    14  ssdt   7992a16c     28  i2c2@17,0
    15  ssdt   7992a194     d8  elan-touchpad@15
    16  ssdt   7992a26c    163  synaptics-touchpad@2c
    17  ssdt   7992a3cf     28  i2c2@17,1
    18  ssdt   7992a3f7    111  wacom-digitizer@9
    19  ssdt   7992a508     8f  sdmmc@1b,0
    1a  ssdt   7992a597     4b  wifi
    1b  ssdt   7992a5e2    1a0  cpu@0
    1c  ssdt   7992a782    1a0  cpu@1
    1d  ssdt   7992a922    1a0  cpu@2
    1e  ssdt   7992aac2    211  cpu@3
    1f  other  799297b0   1530  6ssdt
    20  other  7992ace0   2f10  8dev

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
2d7c738296 acpi: Collect tables in the acpi_item list
At present this list is used to collect items within the DSDT and SSDT
tables. It is useful for it to collect the whole tables as well, so there
is a list of what was created and which write created each one.

Refactor the code accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
31c27eb830 x86: Use the ACPI table writer
Use the new ACPI writer to write the ACPI tables. At present this is all
done in one monolithic function. Future work will split this out.

Unfortunately the QFW write_acpi_tables() function conflicts with the
'writer' version, so disable that for sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
fb746fdec6 acpi: Add a table start
It is useful to record the start of an ACPI table so that offsets from
that point can be easily calculated.

Add this to the context and set it before calling the writer method.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
0679cca507 sandbox: Allow building with GENERATE_ACPI_TABLE
At present this option is missing a header file, a function prototype and
the qfw driver needs a header included.

Fix these problems so we can enable this option on sandbox. This will
increase the build coverage.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Pali Rohár
253373d307 pci: iproc: Set all 24 bits of PCI class code
Register 0x43c in its low 24 bits contains PCI class code.

Update code to set all 24 bits of PCI class code and not only upper 16 bits
of PCI class code.

Use standard U-Boot macro (PCI_CLASS_BRIDGE_PCI << 8) for constructing all
24-bits of PCI class for PCI bridge Normal decode.

Signed-off-by: Pali Rohár <pali@kernel.org>
Acked-by: Roman Bacik <roman.bacik@broadcom.com>
2022-01-24 16:03:27 -05:00
John Keeping
e44d2f5df9 misc: mark write buffer const
The write operation in misc_ops already takes a "const void *" buffer,
but misc_write() takes a mutable "void *".  There's no reason for this,
so make misc_write() consistent with the standard write() prototype.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-24 10:35:10 -05:00
Patrick Delaunay
0f9595b9fa configs: Migrate CONFIG_SYS_MAX_FLASH_BANKS to Kconfig
Use moveconfig.py script to convert define CONFIG_SYS_MAX_FLASH_BANKS
and CONFIG_SYS_MAX_FLASH_BANKS_DETECT to Kconfig and move these entries
to defconfigs.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
[trini: Re-switch to IS_ENABLED check in spi-nor-core.c, re-run migration]
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-01-21 14:01:35 -05:00
Patrick Delaunay
144fef87df mtd: cfi: change CONFIG_SYS_MAX_FLASH_BANKS_DETECT as boolean
Prepare migration to Kconfig.

CONFIG_SYS_MAX_FLASH_BANKS_DETECT becomes boolean and
CONFIG_SYS_MAX_FLASH_BANKS define the MAX size, also used
for detection when CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
(CFI_MAX_FLASH_BANKS = CONFIG_SYS_MAX_FLASH_BANKS).

CONFIG_SYS_MAX_FLASH_BANKS become mandatory when
CONFIG_SYS_MAX_FLASH_BANKS_DETECT is activated.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-21 14:01:35 -05:00
Patrick Delaunay
98150e7e8c mtd: cfi: introduce CFI_FLASH_BANKS
Replace CONFIG_SYS_MAX_FLASH_BANKS by CFI_FLASH_BANKS to prepare
Kconfig migration and avoid to redefine CONFIG_SYS_MAX_FLASH_BANKS
in cfi_flash.h.

After this patch CONFIG_SYS_MAX_FLASH_BANKS should be never used in
the cfi code: use CFI_MAX_FLASH_BANKS for struct size or CFI_FLASH_BANKS
for number of CFI banks which can be dynamic.

This patch modify all the files which include mtd/cfi_flash.h.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-21 14:01:35 -05:00
Tom Rini
2d7a463e82 Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- fdt_support: Add fdt_for_each_node_by_compatible() helper macro
  (Marek)
- turris_omnia: Fixup SATA or PCIe nodes at runtime in DT blob (Pali)
- pci_mvebu: Add support for Kirkwood PCIe controllers (Pali)
- SPL: More verifications for kwbimage in SPL (Pali)
- mvebu: Remove comphy_update_map() (Pali)
- Minor misc stuff
2022-01-20 12:40:20 -05:00
Tom Rini
280db76f15 Pull request doc-2022-04-rc1
Replace @return by Return: in code comments.
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Merge tag 'doc-2022-04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request doc-2022-04-rc1

Replace @return by Return: in code comments.
2022-01-20 09:39:45 -05:00
Pali Rohár
2928d2cd50 phy: marvell: Remove unused function comphy_update_map()
This weak function is not used anymore, so completely remove it.

Private struct comphy_map is not used by any board code anymore, so move it
into private driver header file comphy_core.h.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20 14:46:03 +01:00
Heinrich Schuchardt
2e66ecb765 drivers: octeon: get rid of Unicode in code
Placing Unicode control codes <U+0080><U+0093> in the middle of a comment
does not make much sense. Let's get rid of all Unicode in
drivers/ram/octeon/octeon3_lmc.c.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20 14:45:46 +01:00
Pali Rohár
2e0429bcc1 SPL: Add struct spl_boot_device parameter into spl_parse_board_header()
Add parameter spl_boot_device to spl_parse_board_header(), which allows
the implementations to see from which device we are booting and do
boot-device-specific checks of the image header.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20 11:35:29 +01:00
Pali Rohár
4364071362 pci: pci_mvebu: Add support for Kirkwood PCIe controllers
Kirkwood uses macros KW_DEFADR_PCI_MEM and KW_DEFADR_PCI_IO for base
address of PCIe mappings. Size of PCIe windows is not defined in any macro
yet, so export them in new KW_DEFADR_PCI_MEM_SIZE and KW_DEFADR_PCI_IO_SIZE
macros.

Kirkwood arch code already maps mbus windows for io and mem, so avoid
calling mvebu_mbus_add_window_by_id() function which would try to do
duplicate window mapping.

Kirkwood PCIe controllers already use "marvell,kirkwood-pcie" DT compatible
string, so mark pci_mvebu.c driver as compatible for it.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20 11:35:29 +01:00
Marek Behún
3058e283b8 fdt_support: Add fdt_for_each_node_by_compatible() helper macro
Add macro fdt_for_each_node_by_compatible() to allow iterating over
fdt nodes by compatible string.

Convert various usages of
    off = fdt_node_offset_by_compatible(fdt, start, compat);
    while (off > 0) {
        code();
        off = fdt_node_offset_by_compatible(fdt, off, compat);
    }
and similar, to
    fdt_for_each_node_by_compatible(off, fdt, start, compat)
        code();

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-20 11:35:29 +01:00
Heinrich Schuchardt
185f812c41 doc: replace @return by Return:
Sphinx expects Return: and not @return to indicate a return value.

find . -name '*.c' -exec \
sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \;

find . -name '*.h' -exec \
sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \;

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-19 18:11:34 +01:00
Tom Rini
068415eade Xilinx changes for v2022.04-rc1
gpio:
 - Add modepin driver
 
 net:
 - Save random mac addresses to eth variable
 
 zynqmp gem:
 - Add support for mdio bus DT description
 - Add support for reset and SGMII phy configuration
 - Reduce timeout for MDIO accesses
 
 zynqmp clk:
 - Fix clock handling for gem and usb
 
 phy:
 - Add zynqmp phy/serdes driver
 
 serial:
 - Add one missing compatible string
 
 microblaze:
 - Symbol alignement
 - SPL fixups
 - Code cleanups
 
 zynqmp:
 - Various dt changes, DP pre-reloc, gem resets, gem clocks
 - Switch SOM to shared psu configuration
 - Move dcache handling to firmware driver
 - Workaround gmii2rgmii DT description issue
 - Enable broadcasts again
 - Change firmware enablement logic
 - Small adjustement in firmware driver
 
 versal:
 - Support new mmc@ DT nodes
 - Fix run time variable handling
 - Add missing I2C_PMC ID for power domain
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Merge tag 'xilinx-for-v2022.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.04-rc1

gpio:
- Add modepin driver

net:
- Save random mac addresses to eth variable

zynqmp gem:
- Add support for mdio bus DT description
- Add support for reset and SGMII phy configuration
- Reduce timeout for MDIO accesses

zynqmp clk:
- Fix clock handling for gem and usb

phy:
- Add zynqmp phy/serdes driver

serial:
- Add one missing compatible string

microblaze:
- Symbol alignement
- SPL fixups
- Code cleanups

zynqmp:
- Various dt changes, DP pre-reloc, gem resets, gem clocks
- Switch SOM to shared psu configuration
- Move dcache handling to firmware driver
- Workaround gmii2rgmii DT description issue
- Enable broadcasts again
- Change firmware enablement logic
- Small adjustement in firmware driver

versal:
- Support new mmc@ DT nodes
- Fix run time variable handling
- Add missing I2C_PMC ID for power domain
2022-01-19 11:43:44 -05:00
Michal Simek
11c07719d5 firmware: zynqmp: Do not report error if node is already configured
Power domain driver sends PM fragment to PMUFW. It is sent for every node
which is listed in DT. But some nodes could be already enabled but driver
is not capable to find it out. That's why it blinly sents request for every
listed IP. When PMUFW response by XST_PM_ALREADY_CONFIGURED error code
there is no need to show any error message because node is already enabled.
That's why cover this case with message when DEBUG is enabled.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/8c15ef0b68cf191f693d3d010f70ac24cfd8171f.1642163135.git.michal.simek@xilinx.com
2022-01-19 15:14:29 +01:00
Michal Simek
12662e7034 firmware: zynqmp: Move loading message to debug
Power domain driver is using this function for every IP which is PD listed.
This can end up with a lot of messages which end up in boot log. That's why
show it only in EL3 as was used in past.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/d73fc8bc663110b6e8d5e70fdb6435d1199e9db8.1642163135.git.michal.simek@xilinx.com
2022-01-19 15:14:29 +01:00
Dylan Hung
e559193968 clk: ast2600: Revise MII interface delay
The clock delay of the RMII/RGMII interface is controlled by SCU340~35C.
These values are obtained by measurement and experiments so we simply
use macro to define them.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-01-18 12:48:17 -05:00
Dylan Hung
ac4fda7bc2 net: ftgmac100: Add Aspeed AST2600 support
Add support of the MAC controller of Aspeed AST2600 SOC.  The MAC
controller is the same with AST2500, except it has stand-alone MDIO
hardware block.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-01-18 12:48:17 -05:00
Dylan Hung
9c27ce781d net: ftgmac100: Add DM_MDIO support
Add support for DM_MDIO to connect to PHY.  For the systems that have a
stand-alone MDIO hardware block, enable CONFIG_DM_MDIO to use driver
model for MDIO devices.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-01-18 12:48:17 -05:00
Amit Singh Tomar
57a91c3c9e mmc: actions: add MMC driver for Actions OWL S700/S900
This commit adds support for MMC controllers found on Actions OWL
SoC platform(S700/S900).

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2022-01-18 12:48:17 -05:00
Amit Singh Tomar
05c2ff7dc6 clk: actions: Add SD/MMC clocks
This commit adds SD/MMC clocks, and provides .set/get_rate callbacks
for SD/MMC device present on Actions OWL S700 SoCs.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2022-01-18 12:48:17 -05:00
Amit Singh Tomar
234c1672a1 clk: actions: Introduce dummy get/set_rate callbacks
This commit introduces get/set_rate callbacks, these are dummy at
the moment, and can be used to get/set clock for various devices
based on the clk id.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-01-18 12:48:17 -05:00
AJ Bagwell
1041eae420 pinctrl: single: add support for pinctrl-single, pins when #pinctrl-cells = 2
Changes to the am33xx device (33e9021a) trees have been merged in from
the upstream linux kernel which now means the device tree uses the new
pins format (as of 5.10) where the confinguration can be stores as a
separate configuration value and pin mux mode which are then OR'd
together.

This patch adds support for the new format to u-boot so that
pinctrl-cells is now respected when reading in pinctrl-single,pins
Signed-off-by: Anthony Bagwell <anthony.bagwell@hivehome.com>
2022-01-18 08:31:02 -05:00
qianfan Zhao
ea9733ac4c drivers: musb_gadget: Save endpoint desc to usb_ep->desc
Fix fastboot flash bug.

If the downloading file size is equal to the partition size, "fastboot
flash" can't work, at least in sunxi platform, because used an
uninitalized point: ep->desc.

This patch also fixed 'data abort' bug in am335x platform.

Reproduce: fastboot flash loader1 spl/sunxi-spl.bin.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-01-17 14:45:24 -05:00
Robert Marko
429866e845 mtd: nand: pxa3xx: set mtd->dev
Currently the pxa3xx driver does not set the udevice in the mtd_info
struct and this prevents the mtd from parsing the partitions via DTS
like for SPI-NOR.

So simply set the mtd->dev to the driver udevice.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-17 14:45:24 -05:00
Tom Rini
4e81f3be34 Merge branch '2022-01-15-TI-platform-updates'
- Let am335x_evm use the CPSW or PRUSS ethernet.
- Implement timer_get_boot_us in the omap timer driver
- gpmc bitflip, QSPI clock calculation on am437x, da8xx_gpio bugfixes
- Assorted K3 updates
2022-01-17 11:24:43 -05:00
Tom Rini
6d2ebcd7be Second set of u-boot-at91 features for the 2022.04 cycle
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Merge tag 'u-boot-at91-2022.04-b' of https://source.denx.de/u-boot/custodians/u-boot-at91

Second set of u-boot-at91 features for the 2022.04 cycle:

This small feature set includes few changes for sama7g5 and sama7g5ek:
turn blue led on at boot, changes required for the Rev4 of the board,
better sync with the Linux DT with regards to the new DT nodes.
2022-01-17 08:36:12 -05:00
Tom Rini
34972e7ea6 Merge https://source.denx.de/u-boot/custodians/u-boot-pmic
- Apple M1 PMIC support
2022-01-17 08:35:39 -05:00
Tom Rini
d928b365cc Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-net
- PXE label override support
- Fastboot UDP configurable port
- new phy driver: TI DP83869HM
- and few minor fixes to dsa.
2022-01-17 08:35:11 -05:00
Ashok Reddy Soma
ca994327ce net: gem: Workaround gmii2rgmii bridge DT node issue
For configurations with gmii2rgmii and external phy the DT nodes link
should be gem->gmii2rgmii->phy. But due to limitation in Linux driver
the DT is mentioned as gem->phy and gmii2rgmii->phy as shown in below DT.

ethernet@ff0c0000 {
	compatible = "cdns,zynqmp-gem\0cdns,gem";
	status = "okay";
	interrupt-parent = <0x04>;
	interrupts = <0x00 0x3b 0x04 0x00 0x3b 0x04>;
	reg = <0x00 0xff0c0000 0x00 0x1000>;
	clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk";
	#address-cells = <0x01>;
	#size-cells = <0x00>;
	#stream-id-cells = <0x01>;
	iommus = <0x0d 0x875>;
	power-domains = <0x0c 0x1e>;
	clocks = <0x03 0x1f 0x03 0x69 0x03 0x2e 0x03 0x32 0x03 0x2c>;
	phy-handle = <0x0e>;
	phy-mode = "gmii";
	xlnx,ptp-enet-clock = <0x00>;
	local-mac-address = [ff ff ff ff ff ff];
	phandle = <0x4d>;

	mdio {
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		phandle = <0x4e>;

		ethernet-phy@1 {
			reg = <0x01>;
			rxc-skew-ps = <0x708>;
			txc-skew-ps = <0x708>;
			phandle = <0x0e>;
		};

		gmii_to_rgmii_0@8 {
			compatible = "xlnx,gmii-to-rgmii-1.0";
			phy-handle = <0x0e>;
			reg = <0x08>;
			phandle = <0x4f>;
		};
	};
};

Since same DT is used in Linux and U-Boot we need to workaround this
issue by using the gmii2rgmii node which points to phy and we should
ignore the gem pointing to phy directly.

Do this workaround by updating priv->phydev->node value with
priv->phy_of_node only if it is not valid node.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Link: https://lore.kernel.org/r/641eb13425ffe80e0743f60cf90d0f940577b9e9.1642162085.git.michal.simek@xilinx.com
2022-01-17 10:02:35 +01:00
Michal Simek
a2d5f3d133 Revert "net: gem: Disable broadcast setting"
This reverts commit eafdcda4a8.

The main reason is that QEMU is using BOOTP protocol which is sending DHCP
Offer to a broadcast address that's why it can't be disabled.
DHCP protocol has no issue because it returns directly to client MAC
address.
Both of these options are described in RFC951
(https://datatracker.ietf.org/doc/html/rfc951#section-4)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Link: https://lore.kernel.org/r/fc5f5e2aeca77847ed4ca6a263890375ab9f5163.1642162545.git.michal.simek@xilinx.com
2022-01-17 10:01:51 +01:00
Mark Kettenis
97187d5e37 power: domain: Add Apple pmgr driver
This driver supports power domains for the power management
controller found on Apple SoCs.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-17 06:56:01 +09:00
David Rivshin
f44bcb9f0d nand: gpmc: Handle bitflips in erased pages when using BCH ECC engine
In the case of an erased (sub)page both the data and ECC are all 0xFF
bytes. This fails the normal ECC verification, as the computed ECC of
all-0xFF is not also 0xFF. The GPMC NAND driver attempted to detect
erased pages by checking that the ECC bytes are all-0xFF, but this had
two problems:
1) bitflips in the data were not corrected, so the data looked not-erased
2) bitflips in the ECC bytes were reported as uncorrectable ECC errors

The equivalent Linux driver [1] correctly handles this by counting the
number of 0-bits in the combination of data and ECC bytes. If the number
of 0-bits is less than the amount of bits correctable by the selected
ECC algorithm, then it is treated as an erased page with correctable
bitflips.

Implement similar, though simplified, logic in omap_correct_data_bch().

[1] see omap_elm_correct_data() in omap2.c

Signed-off-by: David Rivshin <drivshin@allworx.com>
2022-01-16 08:31:03 -05:00
Stefan Mätje
a6e562fe36 Fix wrong QSPI clock calculation for AM4372
On AM4372 the SPI_GCLK input gets its clock from the PRCM module which
divides the PER_CLKOUTM2 frequency (192MHz) by a fixed factor of 4.
See AM437x Reference Manual in section 27 QSPI >> 27.2 Integration.

The QSPI_FCLK therefore needs to take this factor into account and
becomes (192000000 / 4).

Signed-off-by: Stefan Mätje <stefan.maetje@esd.eu>
2022-01-16 08:31:03 -05:00
Christian Gmeiner
e660cfad53 omap: timer: implement timer_get_boot_us
To make the OMAP DM timer driver useful for the timing of
bootstages, we need to implement timer_get_boot_us(..).

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-01-16 08:31:03 -05:00
chao zeng
b6e59617c8 gpio: da8xx_gpio: Fix gpio name with address
The GPIO bank numbers do not appear in the device tree,
so make the gpio name based on the address
(ie gpio@42110000_25 vs 25)

Signed-off-by: chao zeng <chao.zeng@siemens.com>
2022-01-16 08:31:03 -05:00
Christian Gmeiner
046bf8d4c5 net: fastboot: make UDP port net: configurable
The fastboot protocol uses per default the UDP port 5554. In some cases
it might be needed to change the used port. The fastboot utility provides
a way to specifiy an other port number to use already.

  fastboot -s udp:192.168.1.76:1234 boot fastboot.img

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-01-15 18:54:21 +02:00
Markus Koch
eab18b3b06 net: fsl: Fix busy flag polling register
NXP's mEMAC reference manual, Chapter 6.5.5 "MDIO Ethernet Management
Interface usage", specifies to poll the BSY (0) bit in the CFG/STAT
register to wait until a transaction has finished, not bit 31 in the
data register.

In the Linux kernel, this has already been fixed in commit 26eee0210ad7
("net/fsl: fix a bug in xgmac_mdio").

This patch changes the register in the fman_mdio and fsl_ls_mdio
drivers.

As the MDIO_DATA_BSY define is no longer in use, this patch also removes
its definition from the fsl_memac header.

Signed-off-by: Markus Koch <markus@notsyncing.net>
Reviewed-by: Camelia Groza <camelia.groza@nxp.com>
2022-01-15 18:53:16 +02:00
Marek Vasut
766ba78375 net: eth-phy: Demote missing phy-handle log message to debug
Reduce the missing phy-handle log message to debug message. It is
possible for ethernet DT node to have no phy-handle e.g. in case
of a fixed-link connection. Furthermore, drop the FEC: prefix,
which is a copy-paste error and rather print the ethernet device
name.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-01-15 18:51:49 +02:00
Dominic Rath
f3e22eea81 net: phy: add TI DP83869HM ethernet driver
This driver is based on an older downstream TI kernel, with
changes and cleanups to work with mainline device-tree bindings.

Signed-off-by: Dominic Rath <rath@ibv-augsburg.net>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-01-15 18:50:16 +02:00
Vladimir Oltean
6372ece6e8 net: dsa: sja1105: fix device id detection
The sja1105_check_device_id() function contains logic to work without
changing the device tree on reworked boards, one of which I have (the
NXP LS1021A-TSN normally has a SJA1105T, but I have a version with a
resoldered SJA1105Q which is pin compatible). This logic is taken from
the Linux driver.

However this logic gets shortcircuited in U-Boot by an earlier check for
the exact device ID specified in the device tree. So the reworked board
does not probe the SJA1105Q switch. Remove this duplicated logic and let
the automatic device ID detection do its job.

Fixes: f24b666b22 ("net: dsa: add driver for NXP SJA1105 L2 switch")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-01-15 18:49:13 +02:00
Vignesh Raghavendra
38922b1f4a net: ti: am65-cpsw: Add support for multi port independent MAC mode
On certain TI SoC, like AM64x there is a CPSW3G which supports 2
external independent MAC ports for single CPSW instance.
It is not possible for Ethernet driver to register more than one port
for given instance.

This patch modifies top level CPSW NUSS as UCLASS_MISC and binds
UCLASS_ETH to individual ports so as to support bring up more than one
Ethernet interface in U-Boot.

Note that there is no isolation in the since, CPSW NUSS is in promisc
mode and forwards all packets to host.

Since top level driver is now UCLASS_MISC, board files would need to
instantiate this driver explicitly.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-01-15 10:38:26 -05:00
Vignesh Raghavendra
4af5e5f6fd dma: ti: k3-udma: Fix rflow reservation for PKTDMA
Driver has a bug in that it uses rflow_in_use bitmap when setting up free rflow range
from TISCI but use rflow_map for reservation in __udma_reserve_rflow()

Fix this by dropping rflow_in_use bitmap array and use rflow_map for
PKTDMA. BCDMA does not need rflow_in_use either.

This fixes CPSW3g not able to get DMA channels at R5 SPL on AM64x

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-01-15 10:38:26 -05:00
Alper Nebi Yasak
226fce6108 phy: Track power-on and init counts in uclass
On boards using the RK3399 SoC, the USB OHCI and EHCI controllers share
the same PHY device instance. While these controllers are being stopped
they both attempt to power-off and deinitialize it, but trying to
power-off the deinitialized PHY device results in a hang. This usually
happens just before booting an OS, and can be explicitly triggered by
running "usb start; usb stop" in the U-Boot shell.

Implement a uclass-wide counting mechanism for PHY initialization and
power state change requests, so that we don't power-off/deinitialize a
PHY instance until all of its users want it done. The Allwinner A10 USB
PHY driver does this counting in-driver, remove those parts in favour of
this in-uclass implementation.

The sandbox PHY operations test needs some changes since the uclass will
no longer call into the drivers for actions matching its tracked state
(e.g. powering-off a powered-off PHY). Update that test, and add a new
one which simulates multiple users of a single PHY.

The major complication here is that PHY handles aren't deduplicated per
instance, so the obvious idea of putting the counts in the PHY handles
don't immediately work. It seems possible to bind a child udevice per
PHY instance to the PHY provider and deduplicate the handles in each
child's uclass-private areas, like in the CLK framework. An alternative
approach could be to use those bound child udevices themselves as the
PHY handles. Instead, to avoid the architectural changes those would
require, this patch solves things by dynamically allocating a list of
structs (one per instance) in the provider's uclass-private area.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Peter Robinson <pbrobinson@gmail.com> - Rock960
2022-01-14 14:36:57 -05:00