mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-24 13:43:28 +00:00
mmc: actions: add MMC driver for Actions OWL S700/S900
This commit adds support for MMC controllers found on Actions OWL SoC platform(S700/S900). Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
This commit is contained in:
Amit Singh Tomar
Tom Rini
parent
3739cd58a4
commit
57a91c3c9e
3 changed files with 416 additions and 0 deletions
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@ -295,6 +295,13 @@ config MMC_MXC
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If unsure, say N.
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config MMC_OWL
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bool "Actions OWL Multimedia Card Interface support"
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depends on ARCH_OWL && DM_MMC && BLK
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help
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This selects the OWL SD/MMC host controller found on board
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based on Actions S700/S900 SoC.
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config MMC_MXS
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bool "Freescale MXS Multimedia Card Interface support"
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depends on MX23 || MX28 || MX6 || MX7
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@ -39,6 +39,7 @@ obj-$(CONFIG_MMC_OMAP_HS) += omap_hsmmc.o
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obj-$(CONFIG_MMC_MXC) += mxcmmc.o
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obj-$(CONFIG_MMC_MXS) += mxsmmc.o
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obj-$(CONFIG_MMC_OCTEONTX) += octeontx_hsmmc.o
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obj-$(CONFIG_MMC_OWL) += owl_mmc.o
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obj-$(CONFIG_MMC_PCI) += pci_mmc.o
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obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
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obj-$(CONFIG_$(SPL_TPL_)SUPPORT_EMMC_RPMB) += rpmb.o
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408
drivers/mmc/owl_mmc.c
Normal file
408
drivers/mmc/owl_mmc.c
Normal file
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@ -0,0 +1,408 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 Amit Singh Tomar <amittomer25@gmail.com>
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*
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* Driver for SD/MMC controller present on Actions Semi S700/S900 SoC, based
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* on Linux Driver "drivers/mmc/host/owl-mmc.c".
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*
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* Though, there is a bit (BSEL, BUS or DMA Special Channel Selection) that
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* controls the data transfer from SDx_DAT register either using CPU AHB Bus
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* or DMA channel, but seems like, it only works correctly using external DMA
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* channel, and those special bits used in this driver is picked from vendor
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* source exclusively for MMC/SD.
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*/
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#include <common.h>
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#include <clk.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <errno.h>
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#include <log.h>
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#include <mmc.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/iopoll.h>
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/*
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* SDC registers
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*/
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#define OWL_REG_SD_EN 0x0000
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#define OWL_REG_SD_CTL 0x0004
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#define OWL_REG_SD_STATE 0x0008
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#define OWL_REG_SD_CMD 0x000c
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#define OWL_REG_SD_ARG 0x0010
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#define OWL_REG_SD_RSPBUF0 0x0014
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#define OWL_REG_SD_RSPBUF1 0x0018
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#define OWL_REG_SD_RSPBUF2 0x001c
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#define OWL_REG_SD_RSPBUF3 0x0020
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#define OWL_REG_SD_RSPBUF4 0x0024
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#define OWL_REG_SD_DAT 0x0028
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#define OWL_REG_SD_BLK_SIZE 0x002c
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#define OWL_REG_SD_BLK_NUM 0x0030
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#define OWL_REG_SD_BUF_SIZE 0x0034
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/* SD_EN Bits */
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#define OWL_SD_EN_RANE BIT(31)
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#define OWL_SD_EN_RESE BIT(10)
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#define OWL_SD_ENABLE BIT(7)
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#define OWL_SD_EN_BSEL BIT(6)
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#define OWL_SD_EN_DATAWID(x) (((x) & 0x3) << 0)
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#define OWL_SD_EN_DATAWID_MASK 0x03
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/* SD_CTL Bits */
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#define OWL_SD_CTL_TOUTEN BIT(31)
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#define OWL_SD_CTL_DELAY_MSK GENMASK(23, 16)
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#define OWL_SD_CTL_RDELAY(x) (((x) & 0xf) << 20)
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#define OWL_SD_CTL_WDELAY(x) (((x) & 0xf) << 16)
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#define OWL_SD_CTL_TS BIT(7)
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#define OWL_SD_CTL_LBE BIT(6)
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#define OWL_SD_CTL_TM(x) (((x) & 0xf) << 0)
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#define OWL_SD_DELAY_LOW_CLK 0x0f
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#define OWL_SD_DELAY_MID_CLK 0x0a
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#define OWL_SD_RDELAY_HIGH 0x08
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#define OWL_SD_WDELAY_HIGH 0x09
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/* SD_STATE Bits */
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#define OWL_SD_STATE_DAT0S BIT(7)
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#define OWL_SD_STATE_CLNR BIT(4)
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#define OWL_SD_STATE_CRC7ER BIT(0)
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#define OWL_MMC_OCR (MMC_VDD_32_33 | MMC_VDD_33_34 | \
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MMC_VDD_165_195)
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#define DATA_TRANSFER_TIMEOUT 3000000
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#define DMA_TRANSFER_TIMEOUT 5000000
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/*
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* Simple DMA transfer operations defines for MMC/SD card
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*/
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#define SD_DMA_CHANNEL(base, channel) ((base) + 0x100 + 0x100 * (channel))
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#define DMA_MODE 0x0000
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#define DMA_SOURCE 0x0004
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#define DMA_DESTINATION 0x0008
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#define DMA_FRAME_LEN 0x000C
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#define DMA_FRAME_CNT 0x0010
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#define DMA_START 0x0024
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/* DMAx_MODE */
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#define DMA_MODE_ST(x) (((x) & 0x3) << 8)
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#define DMA_MODE_ST_DEV DMA_MODE_ST(0)
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#define DMA_MODE_DT(x) (((x) & 0x3) << 10)
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#define DMA_MODE_DT_DCU DMA_MODE_DT(2)
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#define DMA_MODE_SAM(x) (((x) & 0x3) << 16)
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#define DMA_MODE_SAM_CONST DMA_MODE_SAM(0)
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#define DMA_MODE_DAM(x) (((x) & 0x3) << 18)
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#define DMA_MODE_DAM_INC DMA_MODE_DAM(1)
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#define DMA_ENABLE 0x1
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struct owl_mmc_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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struct owl_mmc_priv {
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void *reg_base;
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void *dma_channel;
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struct clk clk;
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unsigned int clock; /* Current clock */
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unsigned int dma_drq; /* Trigger Source */
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};
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static void owl_dma_config(struct owl_mmc_priv *priv, unsigned int src,
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unsigned int dst, unsigned int len)
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{
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unsigned int mode = priv->dma_drq;
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/* Set Source and Destination adderess mode */
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mode |= (DMA_MODE_ST_DEV | DMA_MODE_SAM_CONST | DMA_MODE_DT_DCU |
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DMA_MODE_DAM_INC);
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writel(mode, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_MODE);
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writel(src, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_SOURCE);
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writel(dst, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_DESTINATION);
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writel(len, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_FRAME_LEN);
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writel(0x1, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_FRAME_CNT);
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}
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static void owl_mmc_prepare_data(struct owl_mmc_priv *priv,
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struct mmc_data *data)
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{
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unsigned int total;
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u32 buf = 0;
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setbits_le32(priv->reg_base + OWL_REG_SD_EN, OWL_SD_EN_BSEL);
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writel(data->blocks, priv->reg_base + OWL_REG_SD_BLK_NUM);
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writel(data->blocksize, priv->reg_base + OWL_REG_SD_BLK_SIZE);
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total = data->blocksize * data->blocks;
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if (total < 512)
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writel(total, priv->reg_base + OWL_REG_SD_BUF_SIZE);
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else
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writel(512, priv->reg_base + OWL_REG_SD_BUF_SIZE);
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/* DMA STOP */
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writel(0x0, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_START);
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if (data) {
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if (data->flags == MMC_DATA_READ) {
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buf = (ulong) (data->dest);
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owl_dma_config(priv, (ulong) priv->reg_base +
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OWL_REG_SD_DAT, buf, total);
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invalidate_dcache_range(buf, buf + total);
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} else {
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buf = (ulong) (data->src);
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owl_dma_config(priv, buf, (ulong) priv->reg_base +
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OWL_REG_SD_DAT, total);
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flush_dcache_range(buf, buf + total);
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}
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/* DMA START */
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writel(0x1, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_START);
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}
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}
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static int owl_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct owl_mmc_priv *priv = dev_get_priv(dev);
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unsigned int cmd_rsp_mask, mode, reg;
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int ret;
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setbits_le32(priv->reg_base + OWL_REG_SD_EN, OWL_SD_ENABLE);
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/* setup response */
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mode = 0;
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if (cmd->resp_type != MMC_RSP_NONE)
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cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
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if (cmd->resp_type == MMC_RSP_R1) {
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if (data) {
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if (data->flags == MMC_DATA_READ)
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mode |= OWL_SD_CTL_TM(4);
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else
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mode |= OWL_SD_CTL_TM(5);
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} else
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mode |= OWL_SD_CTL_TM(1);
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} else if (cmd->resp_type == MMC_RSP_R2) {
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mode = OWL_SD_CTL_TM(2);
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} else if (cmd->resp_type == MMC_RSP_R1b) {
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mode = OWL_SD_CTL_TM(3);
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} else if (cmd->resp_type == MMC_RSP_R3) {
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cmd_rsp_mask = OWL_SD_STATE_CLNR;
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mode = OWL_SD_CTL_TM(1);
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}
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mode |= (readl(priv->reg_base + OWL_REG_SD_CTL) & (0xff << 16));
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/* setup command */
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writel(cmd->cmdidx, priv->reg_base + OWL_REG_SD_CMD);
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writel(cmd->cmdarg, priv->reg_base + OWL_REG_SD_ARG);
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/* Set LBE to send clk at the end of last read block */
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if (data)
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mode |= (OWL_SD_CTL_TS | OWL_SD_CTL_LBE | 0xE4000000);
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else
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mode |= OWL_SD_CTL_TS;
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if (data)
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owl_mmc_prepare_data(priv, data);
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/* Start transfer */
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writel(mode, priv->reg_base + OWL_REG_SD_CTL);
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ret = readl_poll_timeout(priv->reg_base + OWL_REG_SD_CTL, reg,
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!(reg & OWL_SD_CTL_TS), DATA_TRANSFER_TIMEOUT);
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if (ret == -ETIMEDOUT) {
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debug("error: transferred data timeout\n");
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return ret;
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}
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reg = readl(priv->reg_base + OWL_REG_SD_STATE) & cmd_rsp_mask;
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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if (reg & OWL_SD_STATE_CLNR) {
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printf("Error CMD_NO_RSP\n");
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return -1;
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}
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if (reg & OWL_SD_STATE_CRC7ER) {
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printf("Error CMD_RSP_CRC\n");
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return -1;
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}
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if (cmd->resp_type & MMC_RSP_136) {
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cmd->response[3] = readl(priv->reg_base + OWL_REG_SD_RSPBUF0);
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cmd->response[2] = readl(priv->reg_base + OWL_REG_SD_RSPBUF1);
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cmd->response[1] = readl(priv->reg_base + OWL_REG_SD_RSPBUF2);
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cmd->response[0] = readl(priv->reg_base + OWL_REG_SD_RSPBUF3);
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} else {
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u32 rsp[2];
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rsp[0] = readl(priv->reg_base + OWL_REG_SD_RSPBUF0);
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rsp[1] = readl(priv->reg_base + OWL_REG_SD_RSPBUF1);
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cmd->response[0] = rsp[1] << 24 | rsp[0] >> 8;
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cmd->response[1] = rsp[1] >> 8;
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}
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}
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if (data) {
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ret = readl_poll_timeout(SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_START,
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reg, !(reg & DMA_ENABLE), DMA_TRANSFER_TIMEOUT);
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if (ret == -ETIMEDOUT) {
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debug("error: DMA transfer timeout\n");
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return ret;
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}
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/* DMA STOP */
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writel(0x0, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_START);
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/* Transmission STOP */
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while (readl(priv->reg_base + OWL_REG_SD_CTL) & OWL_SD_CTL_TS)
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clrbits_le32(priv->reg_base + OWL_REG_SD_CTL,
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OWL_SD_CTL_TS);
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}
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return 0;
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}
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static int owl_mmc_clk_set(struct owl_mmc_priv *priv, int rate)
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{
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u32 reg, wdelay, rdelay;
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reg = readl(priv->reg_base + OWL_REG_SD_CTL);
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reg &= ~OWL_SD_CTL_DELAY_MSK;
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/* Set RDELAY and WDELAY based on the clock */
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if (rate <= 1000000)
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rdelay = wdelay = OWL_SD_DELAY_LOW_CLK;
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else if ((rate > 1000000) && (rate <= 26000000))
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rdelay = wdelay = OWL_SD_DELAY_MID_CLK;
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else if ((rate > 26000000) && (rate <= 52000000)) {
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rdelay = OWL_SD_RDELAY_HIGH;
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wdelay = OWL_SD_WDELAY_HIGH;
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} else {
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debug("SD clock rate not supported\n");
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return -EINVAL;
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}
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writel(reg | OWL_SD_CTL_RDELAY(rdelay) | OWL_SD_CTL_WDELAY(wdelay),
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priv->reg_base + OWL_REG_SD_CTL);
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return 0;
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}
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static int owl_mmc_set_ios(struct udevice *dev)
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{
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struct owl_mmc_priv *priv = dev_get_priv(dev);
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struct owl_mmc_plat *plat = dev_get_plat(dev);
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struct mmc *mmc = &plat->mmc;
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u32 reg, ret;
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if (mmc->clock != priv->clock) {
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priv->clock = mmc->clock;
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ret = owl_mmc_clk_set(priv, mmc->clock);
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if (IS_ERR_VALUE(ret))
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return ret;
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ret = clk_set_rate(&priv->clk, mmc->clock);
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if (IS_ERR_VALUE(ret))
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return ret;
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}
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if (mmc->clk_disable)
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ret = clk_disable(&priv->clk);
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else
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ret = clk_enable(&priv->clk);
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if (ret)
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return ret;
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/* Set the Bus width */
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reg = readl(priv->reg_base + OWL_REG_SD_EN);
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reg &= ~OWL_SD_EN_DATAWID_MASK;
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if (mmc->bus_width == 8)
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reg |= OWL_SD_EN_DATAWID(2);
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else if (mmc->bus_width == 4)
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reg |= OWL_SD_EN_DATAWID(1);
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writel(reg, priv->reg_base + OWL_REG_SD_EN);
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return 0;
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}
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static const struct dm_mmc_ops owl_mmc_ops = {
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.send_cmd = owl_mmc_send_cmd,
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.set_ios = owl_mmc_set_ios,
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};
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static int owl_mmc_probe(struct udevice *dev)
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{
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct owl_mmc_plat *plat = dev_get_plat(dev);
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struct owl_mmc_priv *priv = dev_get_priv(dev);
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struct mmc_config *cfg = &plat->cfg;
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struct ofnode_phandle_args args;
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int ret;
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fdt_addr_t addr;
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cfg->name = dev->name;
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cfg->voltages = OWL_MMC_OCR;
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cfg->f_min = 400000;
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cfg->f_max = 52000000;
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cfg->b_max = 512;
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cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz;
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ret = mmc_of_parse(dev, cfg);
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if (ret)
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return ret;
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addr = dev_read_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->reg_base = (void *)addr;
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ret = dev_read_phandle_with_args(dev, "dmas", "#dma-cells", 0, 0,
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&args);
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if (ret)
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return ret;
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priv->dma_channel = (void *)ofnode_get_addr(args.node);
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priv->dma_drq = args.args[0];
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret) {
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debug("clk_get_by_index() failed: %d\n", ret);
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return ret;
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}
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upriv->mmc = &plat->mmc;
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return 0;
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}
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static int owl_mmc_bind(struct udevice *dev)
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{
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struct owl_mmc_plat *plat = dev_get_plat(dev);
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return mmc_bind(dev, &plat->mmc, &plat->cfg);
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}
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static const struct udevice_id owl_mmc_ids[] = {
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{ .compatible = "actions,s700-mmc" },
|
||||
{ .compatible = "actions,owl-mmc" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(owl_mmc_drv) = {
|
||||
.name = "owl_mmc",
|
||||
.id = UCLASS_MMC,
|
||||
.of_match = owl_mmc_ids,
|
||||
.bind = owl_mmc_bind,
|
||||
.probe = owl_mmc_probe,
|
||||
.ops = &owl_mmc_ops,
|
||||
.plat_auto = sizeof(struct owl_mmc_plat),
|
||||
.priv_auto = sizeof(struct owl_mmc_priv),
|
||||
};
|
||||
Loading…
Reference in a new issue