Move from andr_boot_img_hdr_v0 to andr_image_data
structure to prepare for boot image header
version 3 and 4.
Signed-off-by: Safae Ouajih <souajih@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
andr_image_data structure is used as a global representation of
boot image header structure. Introduce this new structure to
support all boot header versions : v0,v1.v2.v3.v4 and to support
v3 and v4 while maitaining support for v0,v1,v2.
The need of using andr_image_data comes from the change of header
structure in both version 3 and 4.
Rework android_image_get_kcomp() to support this new struct.
Signed-off-by: Safae Ouajih <souajih@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
With the new vendor boot image introduced in versions 3 and 4
of boot image header, the header check must be done for both boot
image and vendor boot image. Thus, replace android_image_check_header()
by is_android_boot_image_header() to only refer to boot image header check.
Signed-off-by: Safae Ouajih <souajih@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Vendor boot image is introduced in boot image header
version 3 and 4. Please check [1] for more details.
To prepare for boot image v3/v4 support, allow the abootimg command
to store the vendor_boot image address.
Full support for this new format will be done in a future patch.
Link:[1] https://source.android.com/docs/core/architecture/bootloader/partitions/vendor-boot-partitions
Signed-off-by: Safae Ouajih <souajih@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Android introduced boot header version 3 or 4.
The header structure change with version 3 and 4 to support
the new updates such as:
- Introducing Vendor boot image: with a vendor ramdisk
- Bootconfig feature (v4)
Change andr_img_hdr struct name to maintain support for version v0,
v1 and v2 while introducing version 3 and 4.
Signed-off-by: Safae Ouajih <souajih@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
- Update our CI to use clang-16 for tests. This also changes slightly
how we do linker lists so that we don't rely on undefined behavior
that lead to clang-15 and later failing to work (and in some cases
seemingly, earlier versions of clang would sometimes fail).
As this is now the stable release, move to using that now for our tests.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Per the GCC bug listed below, the way we do linker lists is relying on
undefined behavior that seems to work in gcc, but doesn't always work in
clang. Andrew suggests rewriting our start/end macros in a different way
(as implemented here, from what he said in comment 1) to avoid these
problems.
Reported-by: AdityaK <appujee@google.com>
Suggested-by: Andrew Pinski <apinski@marvell.com>
Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108915
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andrew Pinski <apinski@marvell.com>
In order to prepare for slight size growth due to reworking linker list
support, enable LTO here to save more space again.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Given the number of jobs in CI we have which use python and pip install
packages, we should do this once in the Dockerfile, in order to populate
the cache. We let each job continue to create and use the virtual
environments they need to facilitate making updates to these
environments easier.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In order to better make use of pip caches, and also for better overall
consistency, we should use the same versions of packages in each of our
python requirements files. Update pytest to use the newer versions of
packages we use in sphinx builds.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
There is no need for the board file to instantiate a PL01X platform
device anymore. This is all taken care of by the DM code which now will
probe the device based on the DT node.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tag the serial nodes with bootph-all in order to have these nodes and
the drivers available before relocation.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sync the serial nodes of the LX2160A based boards with their
representation in Linux. We also imported the clockgen and sysclk nodes
which are dependencies.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Move the serial nodes under the soc node. No changes are made to the
nodes, just their location is changed.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The u-boot dts for these boards do not have an soc node, unlike its
Linux counterpart. This patch just adds the soc node as seen in Linux,
the next patches will move some nodes under it.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Now that the DT nodes for the serial devices are in place for these
boards, enable DM_SERIAL in the associated configs.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tag the serial nodes with bootph-all in order to have these nodes and
the drivers available before relocation.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sync the serial nodes of the LS1088A based boards with their
representation in Linux. We also imported the clockgen and sysclk nodes
which are dependencies.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Move the serial nodes under the soc node. No changes are made to the
nodes, just their location is changed.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The u-boot dts for these boards do not have an soc node, unlike its
Linux counterpart. This patch just adds the soc node as seen in Linux,
the next patches will move some nodes under it.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Since the device trees are more or less synchronized with Linux, the
only necessary changes are to enable CONFIG_DM_SERIAL and the DM_SERIAL
driver for ns16550 (ns16550.c rather than serial_ns16550.c).
ls1028aqds_tfa_lpuart_defconfig already uses DM_SERIAL for the LPUART
driver, so I didn't touch that.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Beacon Embedded has an i.MX8M Plus development kit which consists
of a SOM + baseboard. The SOM includes Bluetooth, WiFi, QSPI, eMMC,
and one Ethernet PHY. The baseboard includes audio, HDMI, USB-C Dual
Role port, USB Hub with five ports, a PCIe slot, and a second Ethernet
PHY. The device trees are already queued for inclusion in Linux 6.3.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add support for Data Modul i.MX8M Plus eDM SBC board. This is an
evaluation board for various custom display units. Currently
supported are serial console, ethernet, eMMC, SD, SPI NOR, USB.
Signed-off-by: Marek Vasut <marex@denx.de>
Add WDT reboot bindings on DH i.MX6 DHSOM to permit the platform
to reboot via WDT in U-Boot. These are custom U-Boot bindings,
hence they are placed in -u-boot.dtsi .
Reviewed-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
change prints to show which DDR configuration (single/dual rank) is used
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Deduplicate similar DDRC configurations and LPDDR4 training patterns
by patching a single configuration.
The aim is to reduce the SPL memory footprint and simplify maintenance
of lpddr4_timing.c
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Update LPDDR4 configuration and training using updated spreadsheet and
tools from NXP using data from previous spreadsheet and verified
toward datasheet:
- MX8M_Plus_LPDDR4_RPA_v9.xlsx
- mscale_ddr_tool_v3.30.exe
From:
https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/1104467
Some register values differ due to these fixes/modifications:
- corrected calculation of T_CKPDX parameter (equal to tCKCKEH for LPDDR4)
- corrected ECC related items, none of which affect normal operation
when ECC is not enabled
- corrected formula for calculation of tRTP in cell D122
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Change tRFCmin (tRFCab) from 280 ns to 380 ns to be compliant with
current and futures memories.
Fixes: 2bc2f817ce ("board: toradex: add verdin imx8m plus support")
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Add support to Verdin IMX8MP V1.1B SKU which uses
MT53E1G32D2FW-046 WT:B memory.
Compared to the 8 GB memory (MT53E2G32D4NQ-046 WT:A) used on
Verdin IMX8MP V1.0A it has 16 row addresses instead of 17.
In fact, the new memory, is a 2 GB/rank memory. The 8 GB memory is a
4 GB/rank memory.
Manually tweaking Host Interface addresses vs LPDDR4 signals mapping it
is possible to have a single configuration working with both memories:
- Old configuration: HIF bit 30 -> rank, HIF bit 29 -> Row 16
- New configuration: HIF bit 29 -> rank, HIF bit 30 -> Row 16
With this change the memory space from the host processor is contiguous
for both the configurations and the correct memory size is computed
using get_ram_size() at runtime.
Support for single rank memories still works thanks to the fact
dual ranks training fails (ddr_init->ddr_cfg_phy) toward single rank
memories.
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
U-Boot can be booted from NAND without SPL by prepending the DCD header to
the actual U-Boot binary. However this requires prepending 1024 bytes to
u-boot.imx (DCD + u-boot.bin).
There is already a similar target to build spl/u-boot-nand-spl.imx, add the
same option for no-SPL boot.
Tested on i.MX6ULL.
The resulting layout of u-boot-nand.imx is:
- Offset 0x0000 (0 KiB): padding
- Offset 0x0400 (1 KiB): DCD header
- Offset 0x1000 (4 KiB): u-boot.bin
Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Enable SDP protocol support in SPL for DH i.MX6 DHSOM, now that those
components fit into the SPL due to LTO.
To start U-Boot via SDP upload on i.MX6 DHSOM based board, proceed as follows:
- Compile imx_usb [1] .
- Power off the i.MX6 DHSOM based board.
- Connect both USB-serial console and USB-OTG miniB ports to host PC.
- Switch board to USB boot mode.
- Power on the board.
- Verify using '$ dmesg' that a new device has been detected as follows:
New USB device found, idVendor=15a2, idProduct=0054, bcdDevice= 0.01
New USB device strings: Mfr=1, Product=2, SerialNumber=0
Product: SE Blank ARIK
Manufacturer: Freescale SemiConductor Inc
- Upload U-Boot SPL:
$ imx_usb u-boot-with-spl.imx
- Wait for SPL to come up, the following print ought to be the last on
UART console:
SDP: handle requests...
- Upload U-Boot proper:
$ imx_usb u-boot.img
[1] https://github.com/boundarydevices/imx_usb_loader.git
Signed-off-by: Marek Vasut <marex@denx.de>
The spl_board_prepare_for_boot() should be called before jump_to_image_no_args()
to perform board-specific deinitialization before jumping to the next stage.
This board-specific deinitialization can be very much anything, e.g. disable
dcache in case it was enabled, or such.
Add the missing spl_board_prepare_for_boot() call into f_sdp .
Signed-off-by: Marek Vasut <marex@denx.de>
J721e SK has been broken since at least March 2022.
The main-navss and mcu-navss nodes were renamed and this caused the
A72 SPL to fail early in the boot even before the serial port was
enabled. Fix this.
A later patch series between v2022.07 and v2022.10 additionally broke
boot on this board by introducing hbmc nodes which are not present on
this board. The right fix is to disable these by default in the SOC
dtsi file, but for now we can also disable them in the u-boot dtsi.
With both these fixed, we can now boot the j721e SK board fully from
mainline u-boot.
Fixes: 58d61fb5a7 ("arm: dts: k3-j721e-sk: Add initial A72 specific dts support")
Fixes: 297daac43a ("arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller node")
Reported-by: Anand Gadiyar <gadiyar@ti.com>
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
[gadiyar@ti.com: update commit description]
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
Cc: Bryan Brattlof <bb@ti.com>
Minor changes with fdt command, vboot test, pinctrl
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Merge tag 'dm-next-3apr23' of https://source.denx.de/u-boot/custodians/u-boot-dm into next
Enable VPL tests
Minor changes with fdt command, vboot test, pinctrl
Originally, the mmc aliases node was present in imx6qdl-pico.dtsi.
After the sync with Linux in commit d0399a46e7 ("imx6dl/imx6qdl:
synchronise device trees with linux"), the aliases node is gone as
the upstream version does not have it.
This causes a boot regression in which the eMMC card cannot be found anymore.
Fix it by passing the alias node in the u-boot.dtsi file to
restore the original behaviour where the eMMC (esdhc3) was
mapped to mmc0.
Fixes: d0399a46e7 ("imx6dl/imx6qdl: synchronise device trees with linux")
Signed-off-by: Fabio Estevam <festevam@denx.de>
