Hand over maintainership of Toradex SoMs (that I was responsible of) to
Oleksandr because of my resignation from Toradex, as such I will
have no immediate involvement with these modules and as a result not
able to continue maintaining these boards.
CC: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Acked-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Add implementation of board_mem_get_layout for overriding the memory
layout.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Acked-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
This commit adds initial support for the Toradex Apalis iMX8X 2GB WB
IT V1.1A System on Module support [1].
Boot log:
U-Boot 2020.10-02940-g894aebb7e8-dirty (Oct 22 2020 - 09:43:57 +0300)
CPU: NXP i.MX8QXP RevB A35 at 1200 MHz at 30C
DRAM: 2 GiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... OK
In: serial@5a070000
Out: serial@5a070000
Err: serial@5a070000
Model: Toradex Apalis iMX8 QuadXPlus 2GB Wi-Fi / BT IT V1.1A,
Serial# 06617018
Net: eth0: ethernet@5b040000 [PRIME]
Hit any key to stop autoboot: 0
Functionality wise the following is known to be working:
- eMMC and MMC/SD card
- Ethernet (*)
- GPIOs
- I2C
Unfortunately, there is no USB functionality for the i.MX 8QXP as of
yet.
* With the SCU FW from the latest Toradex BSP 5.0.0 (SCU FW 1.5.1)
ETH PHY encounters bring up problems after reset, this will be fixed
soon on SCU FW side.
[1] https://www.toradex.com/computer-on-modules/apalis-arm-family/nxp-imx-8x
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Acked-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Implement board_phys_sdram_size() to automatically detect Verdin iMX8M
Mini DualLite 1GB vs. Verdin iMX8M Mini Quad 2GB.
Note: This only works if we keep using similar RAM chips!
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Now with them first Verdin iMX8M Mini DualLite modules in for bring-up
we got clarity how is_cpu_type() actually behaves.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Enable PCA9450 i2c level translator, as this is used for the
on module ADC.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
And select the correct devicetree accordingly by setting the variant
environment variable.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
V1.1A HW switched the PMIC from BD71837 to PCA9450.
- Disable combined DVS in PCA9450_BUCK123_DVS.
- Increase DDR Voltage to 0.95V as we use a 1.5GHz RAM.
- Configure WDOG_B behaviour.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Use gpio_early_init_uart() function to disable RS232 serial transceiver
ForceOFF# pins on Iris.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Avoid UART input from floating RX pins on UARTB and UARTC (Colibri T30)
and UARTB, UARTC and UARTD (Apalis T30).
Note: Floating pins may cause spurious break conditions potentially
interrupting U-Boot's autoboot.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Fix SPI1 and UART2/3 resp. UARTB/C pinmuxing.
Note: The former was illegally muxing multiple SoC balls onto the same
internal SoC signal which caused rather strange behaviour regarding
the RS232 serial transceiver ForceOFF# pins as available on Iris.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add pinmuxing comment stating that TRISTATE means the output driver is
tri-stated and INPUT means the input driver is enabled vs. OUTPUT where
it is disabled.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The Toradex product is called apalis-imx8 consisting of SoM with
i.MX8QM and i.MX8QP SoCs.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
The Toradex product is called colibri-imx8x consisting of SoM with
i.MX8QXP and i.MX8DX SoCs.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Wrap video specific functionality with ifdefs.
Fixes: 195011b24d("colibri-imx7: fix splash logo drawing")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Drop show_boot_logo legacy function, as splashscreen functionality can
be used instead.
Fixes: d324189772("toradex: common: show boot logo")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Set proper splashscreen env value instead of calling legacy function
to show embed boot logo.
Fixes: 195011b24d("colibri-imx7: fix splash logo drawing")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Set proper splashscreen env value instead of calling legacy function
to show embed boot logo.
Fixes: 391c712dde("colibri-imx6ull: show boot logo")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
1. Configure white on black for video console.
2. Enable printing bmp logo during late board init stage.
3. Use iomux configuration from device tree.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
1. Show boot logo embed in U-Boot blob.
2. Drop iomux configration for LCD, and use the one provided in device
tree.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
This introduces support for EEPROM as a storage for the main Toradex
config block and additional config blocks on extra EEPROM chips (on
carrier board or video adapters).
To enable EEPROM as a storage for the main config block:
TDX_HAVE_EEPROM=y.
For additional EEPROMs please enable this Kconfig symbol:
TDX_CFG_BLOCK_EXTRA=y.
Information about existing EEPROM chips is provided via Device Tree
using aliases.
You can also write configuration for the carrier board using
create_carrier subcommand for cfgblock. Example:
Verdin iMX8MM # cfgblock create_carrier
Supported carrier boards:
UNKNOWN CARRIER = [0]
Verdin Carrier Board = [1]
Choose your carrier board (provide ID): 1
Enter carrier board version (e.g. V1.1B): V1.0A
Enter carrier board serial number: 10622780
Also with barcode:
Verdin iMX8MM # cfgblock create carrier -y 0156100010622780
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
The Linux coding style guide (Documentation/process/coding-style.rst)
clearly says:
It's a **mistake** to use typedef for structures and pointers.
Besides, using typedef for structures is annoying when you try to make
headers self-contained.
Let's say you have the following function declaration in a header:
void foo(bd_t *bd);
This is not self-contained since bd_t is not defined.
To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h>
#include <asm/u-boot.h>
void foo(bd_t *bd);
Then, the include direcective pulls in more bloat needlessly.
If you use 'struct bd_info' instead, it is enough to put a forward
declaration as follows:
struct bd_info;
void foo(struct bd_info *bd);
Right, typedef'ing bd_t is a mistake.
I used coccinelle to generate this commit.
The semantic patch that makes this change is as follows:
<smpl>
@@
typedef bd_t;
@@
-bd_t
+struct bd_info
</smpl>
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Current codes assume the OPTEE address is at the end of first DRAM bank.
Adjust the process to allow OPTEE in the middle of first bank.
When OPTEE memory is removed from first bank, it may split the first bank
to two banks, adjust the MMU table for the split case,
Since the default CONFIG_NR_DRAM_BANKS is 4, it is enough, just enlarge
i.MX8MP evk to default to avoid issue.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Tested-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
We should not use typedefs in U-Boot. They cannot be used as forward
declarations which means that header files must include the full header to
access them.
Drop the typedef and rename the struct to remove the _s suffix which is
now not useful.
This requires quite a few header-file additions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Move this header out of the common header. Network support is used in
quite a few places but it still does not warrant blanket inclusion.
Note that this net.h header itself has quite a lot in it. It could be
split into the driver-mode support, functions, structures, checksumming,
etc.
Signed-off-by: Simon Glass <sjg@chromium.org>
This patch adds skew register settings for KSZ9131. It checks first
which phy is on the board and then applies the correct skew settings.
Skew settings calculation for the KSZ9131:
The i.MX6 SoC has an output skew tolerance of -100ps to 900ps. All
PCB traces where routed exactly the same length so we can calculate
the skew settings without taking the length into consideration. The
traces are all length matched.
RXC skew (PHY to MAC):
- We use the 2ns DLL controlled delay on the PHY
- We do not use the skew registers
This results in the following values:
RXC
PHY fixed Delay 2000ps
PHY Added Delay 0ps
T_setup_R min 2.00ns
T_setup_R typ 2.00ns
T_setup_R max 2.00ns
T_hold_R min 1.60ns
T_hold_R typ 2.00ns
T_hold_R max 2.40ns
That means we are well within RGMII specs.
TXC skew (MAC to PHY):
- We use the 2ns DLL controlled delay on the PHY
- We then subtract ~0.6ns with TXD[0:3] and TXC clock pad skew
register in a resulting ~1.4ns delay.
This results in the following values under consideration of the
tolerances:
TXC min TXC typ TXC max
MAC min -100ps -100ps -100ps
MAC max 900ps 900ps 900ps
PHY fixed Delay 2000ps 2000ps 2000ps
PHY added Delay -340ps -600ps -859ps
T_setup_T min 1.56ns 1.30ns 1.04ns
T_setup_T typ 2.06ns 1.80ns 1.54ns
T_setup_T max 2.56ns 2.30ns 2.04ns
T_hold_T min 1.04ns 1.30ns 1.56ns
T_hold_T typ 1.94ns 2.20ns 2.46ns
T_hold_T max 2.84ns 3.10ns 3.36ns
This shows that T_hold_T min and T_setup_T min times are out of spec
for RGMII timing. However the KSZ9131 has a minimal value for this time
of 0.8ns which is met under all circumstances.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
This patch determines which phy is placed on the board with the PHY ID
then it sets the same settings for KSZ9031 as before but for KSZ9131
it enables both RXC and TXC delay lines in the PHY.
This will compensate the missing delay from the MAC. Other skew
settings are not needed as the traces on board are routed exactly the
same length
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Tested-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Acked-by: Igor Opaniuk <igor.opaniuk@toradex.com>
This patches uses the existing functions for interacting with the
KSZ9031 and uses the values appropriate for our board.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Tested-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Acked-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Use the `do_reset` implementation of `arch/arm/lib/reset.c` in SPL
instead. It is very close to what is done here, anyway, and plays
more nicely with the rest of U-Boot than adding a custom `do_reset`
implementation into board files.
`do_reset` from `arch/arm/lib/reset.c` calls `reset_cpu` with 0 as the
addr parameter while the boards are passing WDOG1_BASE_ADDR. This is
ok because the `reset_cpu` implementation uses WDOG1_BASE_ADDR by
default if 0 is passed in.
Co-Authored-by: Harald Seiler <hws@denx.de>
Signed-off-by: Claudius Heine <ch@denx.de>
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Adjust DRAM size in case BL32 secure payload is loaded (OP-TEE/Trusty),
so during MMU initialization U-Boot won't touch this mem area.
BL32 is loaded to the end of DRAM, bl32 payload size is read from
rom_pointer[1]. This relates to the issue described in
59efa6b52b("imx8m: Fix MMU table issue for OPTEE memory").
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Update reference in many files detected by
scripts/documentation-file-ref-check
README.imx8image => imx/mkimage/imx8image.txt
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
