Commit graph

13 commits

Author SHA1 Message Date
Mugunthan V N
3a3939bf3d ARM: AM43xx: Add Ethernet boot support to SPL
Add Ethernet Boot support to SPL

Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2014-03-04 09:42:07 -05:00
Lokesh Vutla
e27f2dd721 ARM: AM4372: Update EMIF registers for DDR3
Updating EMIF_PHY_CTRL and adding EMIF_READ_WRITE_EXECUTION_THRESHOLD
registers.
In EMIF_PHY_CTRL:
Updating [4:0]READ_LATENCY to 8, because at higher frequencies like
400MHz the read latency expected will be CL+3 as per tests from HW
folks.
Clearing [19]PHY_DIS_CALIB_RST bit as this is used onl for debug
purpose. With out this resume is not working(Still waiting for PHY team
to come back for better explanation).

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-03-04 09:42:07 -05:00
Mugunthan V N
4cdd7fda91 ARM: AM43xx: Add CPSW support to AM43xx EPOS and GP EVM
Adding support for CPSW to AM43xx EPOS nad GP EVM which is connected
to RMII and RGMII phy respectively and enable cpsw in config.

Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2014-03-04 09:42:06 -05:00
Dave Gerlach
cd8341b7eb ARM: AM43xx: GP-EVM: Correct GPIO used for VTT regulator control
Schematic indicates GPIO5_7 is to be used for VTT regulator control
rather than GPIO0_21 so modify enable_vtt_regulator to reflect this.
Without this some boards will experience DDR3 corruption and fail to
boot.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[trini: Rework patch against mainline]
Signed-off-by: Tom Rini <trini@ti.com>
2014-02-21 13:55:40 -05:00
Lokesh Vutla
0df8afdf10 ARM: AM43xx: Enable DDR dynamic IO power down for DDR3
This patch enables dynamically powering down the
IO receiver when not performing a read on DDR3 board.
This optimizes both active and standby power consumption.
This is derived from a patch that is done on AM335x[1]

[1] http://arago-project.org/git/projects/?p=u-boot-am33x.git;a=commit;h=6a9ee4bc72ece53fabf01825605fba3d71d5feb2

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-01-24 11:38:39 -05:00
Lokesh Vutla
b5e01eecc8 ARM: AM43xx: GP_EVM: Add support for DDR3
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:45 -05:00
Lokesh Vutla
d3daba10f1 ARM: AM43xx: EPOS_EVM: Add support for LPDDR2
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
Adding LPDDR2 init sequence and register details for the same.
Below is the brief description of LPDDR2 init sequence:
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
-> Wait till initialization is complete and the configure MR registers.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:44 -05:00
Lokesh Vutla
cf04d0326b ARM: AM43xx: clocks: Update DPLL details
Updating the Multiplier and Dividers value for all DPLLs.
Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value
returned the MPU DPLL is locked.
At different OPPs follwoing are the MPU locked frequencies.
OPP50	300MHz
OPP100	600MHz
OPP120	720MHz
OPPTB	800MHz
OPPNT	1000MHz
According to the latest DM following is the OPP table dependencies:
	VDD_CORE 	VDD_MPU
	OPP50		OPP50
	OPP50 		OPP100
	OPP100		OPP50
	OPP100		OPP100
	OPP100		OPP120
So at different OPPs of MPU it is safest to lock CORE at OPP_NOM.
Following are the DPLL locking frequencies at OPP NOM:
Core locks at 1000MHz
Per locks at 960MHz
LPDDR2 locks at 266MHz
DDR3 locks at 400MHz

Touching AM33xx files also to get DPLL values specific to board but no
functionality difference.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:01 -05:00
Sekhar Nori
f4af163e6c ARM: AM43XX: Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support
CONFIG_ENV_VARS_UBOOT_CONFIG, CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and
CONFIG_BOARD_LATE_INIT is already set. Adding support to detect the
board. These variables are used by findfdt.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:00 -05:00
Sekhar Nori
9f1a8cd33f ARM: AM43XX: board: add support for reading onboard EEPROM
Add support for reading onboard EEPROM to enable
board detection.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:00 -05:00
Lokesh Vutla
369cbe1e1e ARM: AM43xx: Adapt to ti_armv7_common.h config file
Use ti_armv7_common.h config file to inclde the common
configs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:00 -05:00
Lokesh Vutla
3b34ac13fe ARM: AM43xx: clocks: Add dpll and clock data
Add dpll and clock data for AM43xx

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-08-15 08:51:10 -04:00
Lokesh Vutla
fbf2728da3 ARM: AM43xx: Add Board files
Add board specific information for AM43xx.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-08-15 08:51:10 -04:00