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ARM: AM4372: Update EMIF registers for DDR3

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Updating EMIF_PHY_CTRL and adding EMIF_READ_WRITE_EXECUTION_THRESHOLD
registers.
In EMIF_PHY_CTRL:
Updating [4:0]READ_LATENCY to 8, because at higher frequencies like
400MHz the read latency expected will be CL+3 as per tests from HW
folks.
Clearing [19]PHY_DIS_CALIB_RST bit as this is used onl for debug
purpose. With out this resume is not working(Still waiting for PHY team
to come back for better explanation).

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla 2014-02-18 07:31:57 -05:00 committed by Tom Rini
parent 8feb37b9be
commit e27f2dd721
1 changed files with 1 additions and 1 deletions
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2
board/ti/am43xx/board.c
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@ -206,7 +206,7 @@ const struct emif_regs ddr3_emif_regs_400Mhz = {
.read_idle_ctrl = 0x00050000,
.zq_config = 0x50074BE4,
.temp_alert_config = 0x0,
.emif_ddr_phy_ctlr_1 = 0x0E084008,
.emif_ddr_phy_ctlr_1 = 0x0E004008,
.emif_ddr_ext_phy_ctrl_1 = 0x08020080,
.emif_ddr_ext_phy_ctrl_2 = 0x00400040,
.emif_ddr_ext_phy_ctrl_3 = 0x00400040,