Commit graph

76519 commits

Author SHA1 Message Date
Simon Glass
886d36efdb pinctrl: meson: Correct the driver GPIO declaration
This should use the provided U_BOOT_DRIVER() macro so that the driver gets
added to the appropriate linker list. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 7c9dcfed50 ("pinctrl: meson: rework gx pmx function")
Reported-by: Tom Rini <trini@konsulko.com>
Tested-by: Tom Rini <trini@konsulko.com> on libretech-cc
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-11-19 18:15:26 +01:00
Tom Rini
f9bab982ae Revert "nvme: Enable FUA"
Unaddressed review comments.

This reverts commit b6bfb8971d.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-18 20:18:34 -05:00
Tom Rini
8e2a782af3 Revert "nvme: Fix error in nvme_setup_prps"
Dependent commit has unaddressed review comments.

This reverts commit c4eef59faa.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-18 20:18:22 -05:00
Tom Rini
8391a0f3d9 Merge branch '2021-11-18-regression-fixes'
- An assortment of fixes related to GD, GD_FLG_SKIP_RELOC, and the lmb
- Environment fix on synquacer developmentbox
- Fix for get_info is not valid in partition code
2021-11-18 18:25:19 -05:00
Marek Vasut
b1f3f982fa arm64: Add missing GD_FLG_SKIP_RELOC handling
In case U-Boot enters relocation with GD_FLG_SKIP_RELOC, skip the
relocation. The code still has to set up new_gd pointer and new
stack pointer.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2021-11-18 18:20:19 -05:00
Marek Vasut
bd994c007a lmb: Reserve U-Boot separately if relocation is disabled
In case U-Boot starts with GD_FLG_SKIP_RELOC, the U-Boot code is
not relocated, however the stack and heap is at the end of DRAM
after relocation. Reserve a LMB area for the non-relocated U-Boot
code so it won't be overwritten.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2021-11-18 18:20:19 -05:00
Marek Vasut
47d7d03622 board_f: Copy GD to new GD even if relocation disabled
Even if U-Boot has relocation disabled via GD_FLG_SKIP_RELOC , the
relocated stage of U-Boot still picks GD from new_gd location. The
U-Boot itself is not relocated, but GD might be, so copy the GD to
new GD location even if relocation is disabled.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Peng Fan <peng.fan@oss.nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2021-11-18 18:20:19 -05:00
schspa
50f7b2effd part: return -ENOSYS when get_info not valid.
In some case, get_info() interface can be NULL, add this check to stop
from crash.

Signed-off-by: schspa <schspa@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-11-18 18:20:06 -05:00
Masami Hiramatsu
0171d056ec Revert "board: synquacer: developerbox: Don't set gd->env_addr to default_environment"
Without default setting of gd->env_addr, U-Boot will cause
a synchronous abort if the env-variables on the SPI flash is
broken or not saved corectly. Set gd->env_addr correctly.

This reverts commit 535870f3b0.

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2021-11-18 14:22:11 -05:00
Tom Rini
7a9b768147 Merge branch '2021-11-17-assorted-driver-platform-updates' into next
- NVMe updates
- TI AM64x related USB updates
- Update PCIe CAM support macros, add PCI CAM support as well
- AST2600, Apple (ARM64) pinctrl drivers
- ARM-specific DEBUG uart inconsistencies fixed
- MediaTek MMC improvement
- aspeed: Support secure boot chain with FIT image verification
2021-11-18 13:46:00 -05:00
Aswath Govindraju
b5b97ae073 configs: am64x_evm_*_defconfig: Add configs to enable serdes for USB 3.0 support
Add configs to enable serdes for USB 3.0 support.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-11-17 17:10:16 -05:00
Kishon Vijay Abraham I
326ee2b0bc arm: dts: am642-sk: Add and Enable USB SuperSpeed Host Port in SPL
Add and Enable USB SuperSpeed Host Port in SPL.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-11-17 17:09:47 -05:00
Aswath Govindraju
1ac3b72077 usb: cdns3: cdns3-ti: Add compatible for AM64 SoC
Add new compatible for AM64 SoC.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-11-17 17:09:47 -05:00
Aswath Govindraju
82c65587f6 phy: cadence: phy-cadence-torrent: Change the name of subnode searched
Search for "phy" in the subnode names, to syncup with kernel.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-11-17 17:09:47 -05:00
Jon Lin
c4eef59faa nvme: Fix error in nvme_setup_prps
Consulting to "NVM Express® Base Specification, revision 2.0".

If more PRP List pages are required, then the last entry of
the PRP List contains the Page Base Address of the next PRP
List page. The next PRP List page shall be memory page aligned.

Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
2021-11-17 17:09:47 -05:00
Jon Lin
b6bfb8971d nvme: Enable FUA
Most NVME devcies maintain data in internal cache for an uncertain
times, and u-boot has no method to force NVME to flush cache.
So this patch adds FUA to avoid data loss caused by power off after data
programming.

Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
2021-11-17 17:09:47 -05:00
Alistair Delva
4f2e228086 RFC: arm: pci: Add PCI cam support to PCI-E ecam driver
When booting U-Boot in crosvm, the virtual machine emulates a PCI cam
device, not the PCI-E 'ecam' device normally seen on e.g. QEMU. This
PCI device can be supported with only trivial changes to the ecam
driver.

Instead of adding a completely new driver which is identical besides the
initialization step, add support for the PCI version to the existing
driver.

Signed-off-by: Alistair Delva <adelva@google.com>
Cc: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Cc: Ram Muthiah <rammuthiah@google.com>
2021-11-17 17:09:47 -05:00
Chia-Wei Wang
e3cdc2cbb1 configs: ast2600: Boot kernel FIT in DRAM
AST2600 leverages the FIT hash/signature verification to fulfill
secure boot trust chain. To improve the performance and save SW
code size for those crypto operations, the two HW crypto engine,
HACE and ACRY, are enabled.

However, both of the engines can only access to data stored in
DRAM space. Therefore, we need to move the FIT image into DRAM
before the booting.

This patch update the CONFIG_BOOTCOMMAND to execute the pre-defined
ENV variable which consists of FIT image copy to memory and booting.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17 17:05:57 -05:00
Chia-Wei Wang
3aeb239f51 configs: aspeed: Make EXTRA_ENV_SETTINGS board specific
Move CONFIG_EXTRA_ENV_SETTINGS to board-specific
configuration headers.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17 17:05:57 -05:00
Chia-Wei Wang
ddd778aebe configs: ast2600-evb: Enable SPL FIT support
Enable SPL FIT image load and verification support.
The HW accelerated SHA is also available with the
newly added support of the HACE HW hash engine.

The SPL thumb build is also enabled to keep the binary
less than 64KB to fit into the Aspeed secure boot design.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
2021-11-17 17:05:57 -05:00
Chia-Wei Wang
e3aab73989 ast2600: spl: Locate load buffer in DRAM space
Return CONFIG_SYS_LOAD_ADDR pointing to DRAM space for
spl_get_load_buffer() to allow generic SPL image loading
code (e.g. FIT and Ymodem) to store data in DRAM.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
2021-11-17 17:05:00 -05:00
Chia-Wei Wang
f05522749c ARM: dts: ast2600: Add ACRY to device tree
Add ACRY DTS node and enable it for AST2600 EVB.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
2021-11-17 17:05:00 -05:00
Chia-Wei Wang
89c36cca0b crypto: aspeed: Add AST2600 ACRY support
ACRY is designed to accelerate ECC/RSA digital signature
generation and verification.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17 17:05:00 -05:00
Chia-Wei Wang
af6451187c clk: ast2600: Add RSACLK control for ACRY
Add RSACLK enable for ACRY, the HW RSA/ECC crypto engine
of ASPEED AST2600 SoCs.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17 17:05:00 -05:00
Joel Stanley
a2f16d0073 ARM: dts: ast2600: Add HACE to device tree
Add HACE DTS node and enable it for AST2600 EVB.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17 17:05:00 -05:00
Johnny Huang
9fcdd98e54 crypto: aspeed: Add AST2600 HACE support
Hash and Crypto Engine (HACE) is designed to accelerate the
throughput of hash data digest, and symmetric-key encryption.

Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-11-17 17:05:00 -05:00
Joel Stanley
4080714f5e clk: ast2600: Add YCLK control for HACE
Add YCLK enable for HACE, the HW hash engine of
ASPEED AST2600 SoCs.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17 17:05:00 -05:00
Chia-Wei Wang
3d99be97f1 aspeed: ast2600: Enlarge SRAM size
The AST2600 SRAM has been extended to 88KB since A1
chip revision. This patch updates the SRAM size to
offer more space for early stack/heap use.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
2021-11-17 17:04:59 -05:00
Chia-Wei Wang
deea089077 image: fit: Fix parameter name for hash algorithm
Fix inconsistent function parameter name of the hash algorithm.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Fixes: 92055e138f ("image: Drop if/elseif hash selection in calculate_hash()")
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-11-17 17:04:59 -05:00
Julien Masson
faf5d4d53d mmc: mtk-sd: implement waiting for DAT0 line state
With the recent changes on mmc driver, we saw that the boot is ~5 secs
longer compared to v2021.07 on mediatek platforms.

This regression is seen during mmc_init and caused by the following
patch [1].

Indeed since we did not support poll dat0, we fulfilled the condition
of [1] and a delay of 500 ms was added for every __mmc_switch call.

By adding the support of wait_dat0(), we now don't need to mdelay
during mmc_init anymore.

[1]: https://patchwork.ozlabs.org/project/uboot/patch/1629192034-64056-1-git-send-email-ye.li@nxp.com/

Signed-off-by: Julien Masson <jmasson@baylibre.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-11-17 17:04:59 -05:00
Simon Glass
55de0c1931 rk3399: Don't enable the debug UART if there is no driver
Some boards do not enable SPL_SERIAL so cannot use the debug UART. Add
this condition to the code and drop use of the preprocessor while we are
here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
2021-11-17 17:04:59 -05:00
Simon Glass
370cc945df arm: qemu: Enable the debug UART
Enable this to permit early debugging. Due to the way qmeu works, the
input clock can be zero and things still work.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-11-17 17:04:59 -05:00
Simon Glass
0dba45864b arm: Init the debug UART
At present we don't init the debug UART in the generic ARM code, but
instead leave it to individual machines to handle. This is not the
way it is supposed to work.

Add the required init to the crt files. This ensures that the UART
is available as early as possible and that the announcement appears
when it should, if enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-11-17 17:04:59 -05:00
Simon Glass
31ec464d65 arm: Fix some inconsistent debug-UART CONFIG options
A few boards enable CONFIG_DEBUG_UART_BOARD_INIT but do not define the
required init function. Fix this by disabling the debug UART.

With snow the debug UART is enabled but the driver CONFIG is not. Fix this
too.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-11-17 17:04:58 -05:00
Pali Rohár
a4bc38da27 pci: Add standard PCIe ECAM macros
Lot of PCIe controllers are using ECAM addressing. So add common ECAM
macros into U-Boot's pci.h header file which can be suitable for most
PCI controller drivers.

Replace custom ECAM address macros in every PCI controller driver by new
ECAM macros from U-Boot's pci.h header file.

Similar macros are defined also in Linux kernel. There is a small
difference between Linux and these new U-Boot macros.

U-Boot's PCIE_ECAM_OFFSET() takes device and function numbers in separate
arguments. Linux's PCIE_ECAM_OFFSET() takes device and function numbers
encoded in one argument. The reason is that U-Boot's PCI_DEVFN() macro is
different than Linux's PCI_SLOT() macro. So having device and function
numbers in separate arguments makes code more straightforward.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-17 17:04:58 -05:00
Mark Kettenis
b814e0007e pinctrl: Add Apple pinctrl driver
This driver supports both pin muxing and GPIO support for the
pin control logic found on Apple SoCs.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2021-11-17 17:04:58 -05:00
Ryan Chen
46220bf017 aspeed: AST2600 Pinctrl Driver
This driver uses Pinctrl framework and is compatible with the Linux
driver for AST2600.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2021-11-17 17:04:58 -05:00
Mathew McBride
4a08dba019 drivers: tpm: atmel_twi: fix printf specifier compile warning
%d was being used as the specifier for size_t, leading to a
compiler warning

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-11-17 13:47:36 +02:00
Mathew McBride
fb30d99df8 drivers: tpm: atmel_twi: implement get_desc operation
Without get_desc, the tpm command will not provide a
description of the device in 'tpm device' or 'tpm info'.

Due to the characteristics of the Atmel TPM it isn't
possible to determine certain attributes (e.g open/close
status) without using the TPM stack (compare Infineon
and ST TPM drivers), so just print out the chip model
and udevice name as the identifier.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-11-17 13:47:33 +02:00
Mathew McBride
fdb4a5fcd7 drivers: tpm: atmel_twi: do not use an offset byte
This driver was broken due to an empty offset byte being prepended
at the start of every transmission.

The hardware does not mimic an EEPROM device with registers so
an offset byte is not required.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-11-17 13:47:31 +02:00
Mathew McBride
02f50d8ebb drivers: tpm: atmel_twi: drop non-DM_I2C compatibility
There are no users of this driver without DM_I2C

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-11-17 13:47:29 +02:00
Mathew McBride
e845dd7c8b cmd: tpm-v1: fix load_key_by_sha1 compile errors
This command is not compiled by default and has not been updated alongside
changes to the tpmv1 API, such as passing the TPM udevice to the relevant
functions.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-11-17 13:47:27 +02:00
Mathew McBride
ebb6d74df3 cmd: tpm-v1: fix compile error in TPMv1 list resources command
This command is not compiled by default and was not
updated to pass the udevice to tpm_get_capability.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-11-17 13:47:21 +02:00
Tom Rini
f299171c1d Merge branch '2021-11-16-env-rework' into next
To quote Simon:

One barrier to completing the 7-year-long Kconfig migration is that
the default environment is implemented using ad-hoc CONFIG options.
At present U-Boot environment variables, and thus scripts, are defined
by CONFIG_EXTRA_ENV_SETTINGS.

It is not really feasible to move the environment to Kconfig as it is
hundreds of lines of text in some cases.

Even considering the current situation, it is painful to add large
amounts of text to the config-header file and dealing with quoting and
newlines is harder than it should be. It would be better if we could just
type the script into a text file and have it included by U-Boot.

This is already supported by the CONFIG_USE_DEFAULT_ENV_FILE feature. But
that does not support use of CONFIG options or comments, so is best suited
for use by other build systems wanting to define the U-Boot environment.

Add a feature that brings in a .env file associated with the board
config, if present. To use it, create a file board/<vendor>/<board>.env or
use CONFIG_ENV_SOURCE_FILE to set a filename.

The environment variables should be of the form "var=value". Values can
extend to multiple lines. This series converts the existing environment
documentation to rST and updates it to explain how to use this.
2021-11-16 20:55:12 -05:00
Simon Glass
7839865272 bootm: Tidy up use of autostart env var
This has different semantics in different places. Go with the bootm method
and put it in a common function so that the behaviour is consistent in
U-Boot. Update the docs.

To be clear, this changes the way that 'bootelf' and standalone boot
work. Before, if autostart was set to "fred" or "YES", for example, they
would consider that a "yes". This may change behaviour for some boards,
but the only in-tree boards which mention autostart use "no" to disable
it, which will still work.

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Wolfgang Denk <wd@denx.de>
2021-11-16 14:35:09 -05:00
Simon Glass
1d192d5bcc sandbox: Update the test MAC/IP addresses
These conflict with real-word addresses. Use locally administered
MAC addresses and a suitable IPv4 address from 192.0.2.0/24
(TEST-NET-1).

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Alexander Dahl <ada@thorsis.com>
2021-11-16 14:35:08 -05:00
Simon Glass
40b9e0dd05 doc: Improve environment documentation further
Make various other updates suggested during review of the rST conversion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-11-16 14:35:08 -05:00
Simon Glass
5ba9e01a3e doc: Improve environment documentation
Make various updates suggested during review of the rST conversion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Suggested-by: Wolfgang Denk <wd@denx.de>
2021-11-16 14:35:08 -05:00
Simon Glass
1df02d1d01 doc: Mention CONFIG_DEFAULT_ENV_FILE
Add mention of this option since it does a similar thing to the text
environment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2021-11-16 14:35:08 -05:00
Simon Glass
f501bb4c2a sandbox: Use a text-based environment
Use a text file for the environment instead of the #define settings.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2021-11-16 14:35:08 -05:00