Just preparing for upcoming cleaning.
The board-specific linker script board/vpac270/u-boot-spl.lds
has been touched to avoid build error. It does not change the
size of spl/u-boot-spl.bin for this board, so it should be OK.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch enabled the MVEBU PCIe support on the db-88f6820-gp A38x
eval board. It also enabled the Intel E1000 driver support and
adds the initialization of PCIe network controllers to the
board code.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anton Schubert <anton.schubert@gmx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
This patch enabled the MVEBU PCIe support on the db-mv784mp-gp AXP
eval board. It also enabled the Intel E1000 driver support and
adds the initialization of PCIe network controllers to the
board code.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anton Schubert <anton.schubert@gmx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This patch enables the NAND controller on the Armada XP/38x and provides
a new function that returns the NAND controller input clock. This
function will be used by the MVEBU NAND driver.
As part of this patch, the multiple BIT macro definitions are moved
to a common place in soc.h.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Peter Morrow <peter@senient.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Remove FAT function prototypes from the cm5200 firmware update code, and
include the relevant headers instead.
This exposes the fact that the custom prototyoe for do_fat_read() in
this file was incorrect. Rather than simply fixing the call-site, replace
do_fat_read() with fat_exists(). This removes the only use of
do_fat_read() outside of the FAT code.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Add support for 4 1.62G lane eDP panels connected via an anx9804 bridge,
such as found on the Colombus devkit.
While at it also fix the wrong indentation of the SSD2828 Kconfig help text
in board/sunxi/Kconfig.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Auxtek-T003 HDMI stick is an A10s based HDMI stick with USB wifi,
and composite video out support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Make sure SODIMM pin 87 nRESET_OUT is released properly by explicitly
setting its pin mux function to GMI. This solves some issues with e.g.
USB not being fully operational on carrier boards with USB hubs
connected to reset if U-Boot got loaded via recovery mode aka rcm.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Various clean-ups either in comments, order or spacing without any
functional impact:
- Add some comments in the device trees resp. reorder some parameters
for consistency across all our modules.
- Sort some include files alphabetically (while leaving common.h on
top of course).
- Streamline some comments in the configuration files and fix the
spacing from using spaces to tabs.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The Colibri T20's PMIC enters a sleep mode on low supply voltage < 3.0V
±2.5% (2.92...3.08V). Rising the main supply voltage again does not
bring it back to regular operation. Not even a full reset does bring
the module back. A full power cycle was required to reboot the system.
A long positive pulse on the PMICs resume pin also reboots the system
but this pin is only accessible as a test point on the module.
This patch configures the PMIC through I2C to not enter this sleep mode
plus force it to normal state upon sleep request exit should this ever
happen.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add LCD display support defaulting to VESA VGA resolution. Different
resolutions configurable via device tree.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Allow detecting whether or not U-Boot was launched through the
recovery mode of the resp. NVIDIA SoC.
Make use of a board specific arch_misc_init() and enable the same via
CONFIG_ARCH_MISC_INIT configuration option.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
- Move the CONS_INDEX selection out of CONFIG_SYS_EXTRA_OPTIONS and
into Kconfig proper.
- While in here, enable CONFIG_SPL_STACK_ADDR
Signed-off-by: Tom Rini <trini@konsulko.com>
Add initial support for CM-T43, an AM437x based SoM.
This support includes: serial, MMC/eMMC, NAND, USB, ETH, I2C, GPIO, DRAM
detection.
Cc: Tom Rini <trini@konsulko.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
HiKey is the first 96boards consumer edition compliant board. It features a hi6220
SoC which has eight ARM A53 cpu's.
This initial port adds support for: -
1) Serial
2) eMMC / SD card
3) USB
4) GPIO
It has been tested with Arm Trusted Firmware running u-boot as the BL33 executable.
Notes:
eMMC has been tested with basic reading of eMMC partition into DDR. I have not
tested writing / erasing. Due to lack of clock control it won't be
running in the most performant high speed mode.
SD card slot has been tested for reading and booting kernels into DDR.
It is also currently configured to save the u-boot environment to the
SD card.
USB has been tested with ASIX networking adapter to tftpboot kernels
into DDR. On v2015.07-rc2 dhcp now works, and also USB mass storage
are correctly enumerated.
GPIO has been tested using gpio toggle GPIO4_1-3 to flash the LEDs.
Basic SoC datasheet can be found here: -
https://github.com/96boards/documentation/blob/master/hikey/
Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
Board schematic can be found here: -
https://github.com/96boards/documentation/blob/master/hikey/
96Boards-Hikey-Rev-A1.pdf
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Remove unused external clocks and make a common definition
for all keystone platforms.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This is just a cosmetic change that makes
the calling of pll init code looks much cleaner.
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Use common devspeed and armspeed definitions.
Also fix reading efuse bootrom register.
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
There are two types of PLL for all keystone platforms:
Main PLL, Secondary PLL. Instead of duplicating the same definition
for each secondary PLL, have a common function which does
initialization for both PLLs. And also add proper register
definitions.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This switches the Integrator boards over to using the device model
for its serial ports.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The mailbox buffer is required to be at least 16 bytes aligned, but for
cache invalidation and/or flush it needs to be cacheline aligned.
Use ALLOC_CACHE_ALIGN_BUFFER for all mailbox buffer allocations.
Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Using the twl4030 keypad allows booting directly into some special boot modes,
such as recovery or fastboot. the VOL+ key will trigger a boot to recovery while
the VOL- key will trigger a boot to fastboot.
The G (gesture) key remains unused at this point.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
In most cases, userspace will attempt to power off the device with HALT instead
of POWER_OFF, which triggers a reset instead of a proper power off from the
TWL4030. Hence, it is up to the bootloader to actually turn the device off when
there is no reason to turn it on.
A reboot identified with the OMAP reboot mode bits set is acceptable, as well as
a power on reason from either the power button, USB or charger plug.
Other cases should trigger a power off. Note that for the U-Boot reset command
to take effect, we have to fill-in the OMAP reboot bits.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This adds support for resetting the device on a long press on the power button.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This adds support for the fastboot USB gadget, including flashing to the
internal MMC and reboot to bootloader or not.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Update to use Kconfig for MUSB]
Signed-off-by: Tom Rini <trini@konsulko.com>
Now that the serial number is correctly defined, we can pass it to the kernel
using the (legacy) ATAG method. It will be automatically passed via device-tree
when enabled.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
The OMAP3 has some die-specific ID bits that we can use to give the device a
(more or less) unique serial number. This is particularly useful for e.g. USB.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This adds support for the omap3 reboot mode mechanism and exports the reboot
mode via an environment variable, that is used in the boot command to make it
possible to boot from the recovery partition.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
The LG Optimus Black (P970) codename sniper is a smartphone that was designed
and manufactured by LG Electronics (LGE) and released back in 2011.
It is using an OMAP3630 SoC GP version, which allows running U-Boot and the
U-Boot SPL from the ground up. This port is aimed at running an Android version
such as Replicant, the fully free Android distribution. However, support for
upstream Linux with device-tree and common GNU/Linux distros boot commands
could be added in the future.
For more information about the journey to freeing this device, please read the
series of blog posts at:
http://code.paulk.fr/article20/a-hacker-s-journey-freeing-a-phone-from-the-ground-up-first-part
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Add CONFIG_OF_SUPPORT]
Signed-off-by: Tom Rini <trini@konsulko.com>
The change adds SPL build support to Timll DevKit3250 board, the
generated SPL image can be uploaded over UART5, JTAG or stored on
NAND. SPL is designed to load U-boot image from NAND.
All new NAND chip defines in board configuration are needed by
SPL NAND "simple" framework, the framework is used to reduce
potentially duplicated code from LPC32xx SLC NAND driver.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
This change adds more peripherals to Timll DevKit3250 board, namely
MAC and SMSC phy, SLC NAND, GPIO, SPI and I2C.
Also the default serial console is changed to UART5, added an option
to pass device tree blob by means of bootm, predefined environment
variables are slightly extended and reserved space on NAND to store
user defined U-boot environment.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Enable BCM SF2 ethernet and PHY for BCM Cygnus SoC
Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
add support for the at91sam9260 based board smartweb from
siemens. SPL is used without serial support, as this
SoC has only 4k sram for running SPL. Here a U-Boot
bootlog:
RomBOOT
>
U-Boot 2015.07-rc2-00109-g4ae828c (Jun 15 2015 - 09:31:16 +0200)
CPU: AT91SAM9260
Crystal frequency: 18.432 MHz
CPU clock : 198.656 MHz
Master clock : 99.328 MHz
Watchdog enabled
DRAM: 64 MiB
WARNING: Caches not enabled
NAND: 256 MiB
In: serial
Out: serial
Err: serial
Net: macb0
Hit any key to stop autoboot: 0
U-Boot>
Signed-off-by: Heiko Schocher <hs@denx.de>
On the highbank platform the SoC's management controller firmware
will probe the DRAM modules and populates the initial device tree with
the correct values. Therefore the memory sizes in the DT are already
correct, so remove U-Boot's DRAM bank setup so the memory node is not
"fixed up" by u-boot.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andre Przywara <osp@andrep.de>
If enable DM PMIC and REGULATOR, we should not use original power
framework. So need to comment out the pfuze code for original power
framework, when CONFIG_DM_PMIC_PFUZE100 defined.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add composite video out support.
This only gets enabled on the Mele M3 for now, since that is were it
was tested. It will be enabled on more boards after testing.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
To enable NAND flash in sunxi SPL,
pins 0-6, 8-22 and 24 on port C are configured.
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Introduce structure socfpga_sdram_misc_config to wrap the remaining
misc configuration values in board file. Again, introduce a function,
socfpga_get_sdram_misc_config(), which returns this the structure. This
is almost the final step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce structure socfpga_sdram_io_config to wrap the IO configuration
values in board file. Introduce socfpga_get_sdram_io_config() function,
which returns this the structure. This is another step toward wrapping
the nasty QTS generated macros in board files and reducing the pollution
of the namespace.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce structure socfpga_sdram_rw_mgr_config to wrap the RW manager
configuration values in board file. Introduce a complementary function,
socfpga_get_sdram_rwmgr_config(), which returns this the structure.
This is another step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce two wrapper functions, socfpga_get_seq_ac_init() and
socfpga_get_seq_inst_init() to avoid direct inclusion of the
sequencer_auto_ac_init.h and sequencer_auto_inst_init.h QTS
generated files. This reduces namespace pollution again.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Move the files generated by QTS into the board directory, they should not
be part of the driver files at all.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce socfpga_sdram_get_config() function implement in a board file,
which returns the socfpga_sdram_config structure. This is the last step
in cleaning up the socfpga_mmr_init_full(), but not the last step which
allows removing the inclusion of sdram.h from drivers/ddr/altera/sdram.c
thus far.
Signed-off-by: Marek Vasut <marex@denx.de>
Implement new accessor, sysmgr_get_pinmux_table(), used to obtain pinmux
table and it's size from the QTS-generated pinmux_config.c. The target
here is again to get rid of poluting global namespace by including the
pinmux_config.h into it.
Furthermore, the pinmux_config.h declares some CONFIG_HPS_* macros,
which are explicitly useless to us in U-Boot. Instead, U-Boot does
use DT to detect exactly these configuration options. This patch
makes sure that while this QTS-generated file can stay in the tree,
these obscure macros do not ooze into the namespace anymore.
Signed-off-by: Marek Vasut <marex@denx.de>
Introduce accessor iocsr_get_config_table() for retrieving IOCSR config
tables. This patch is again trimming down the namespace polution.
The IOCSR config tables are used only by scan manager, they are generated
by qts and are board specific. Before this patch, the approach to use
these tables in scan manager was to define an extern variable to silence
the compiler and compile board-specific iocsr_config.c into U-Boot which
defined those extern variables. Furthermore, since these are tables and
the scan manager needs to know the size of those tables, iocsr_config.h
is included build-wide.
This patch wraps all this into a single accessor which takes the scan
chain ID and returns pointer to the table and it's size. All this is
wrapped in wrap_iocsr_config.c board-specific file. The file includes
the iocsr_config.c (!) to access the original tables and transitively
iocsr_config.h . It is thus no longer necessary to include iocsr_config.h
build-wide and the namespace polution is trimmed some more.
Signed-off-by: Marek Vasut <marex@denx.de>
Extract the clock configuration horribleness caused by pll_config.h in
the following manner.
First of all, introduce a few new accessors which return values of
various clocks used in clock_manager.c and use them in clock_manager.c .
These accessors replace those few macros which came from pll_config.h
originally. Also introduce an accessor which returns the struct cm_config
default configuration for the clock manager used in SPL.
The accessors are implemented in a board-specific wrap_pll_config.c
file, whose sole purpose is to include the qts-generated pll_config.h
and provide only the necessary values to the clock manager.
The purpose of this design is to limit the scope of inclusion for the
pll_config.h , which thus far was included build-wide and poluted the
namespace. With this change, the inclusion is limited to just the new
wrap_pll_config.c file, which in turn provides three simple functions
for the clock_manager.c to use.
Signed-off-by: Marek Vasut <marex@denx.de>
Move all the files generated by Quartus into the qts/ subdir of the
board/altera/socfpga dir to make them explicitly separate from the
generic U-Boot code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
P2371-0000 is a P2581 or P2530 CPU board married to a P2595 I/O
board. The combination contains SoC, DRAM, eMMC, SD card slot,
HDMI, USB micro-B port, Ethernet via USB3, USB3 host port, SATA,
a GPIO expansion header, and an analog audio jack.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
E2220-1170 is a Tegra210 bringup board with onboard SoC, DRAM,
eMMC, SD card slot, HDMI, USB micro-B port, and sockets for various
expansion modules.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
T124/210 requires some specific configuration (VPR setup) to
be performed by the bootloader before the GPU can be used.
For this reason, the GPU node in the device tree is disabled
by default. This patch enables the node if U-boot has performed
VPR configuration.
Boards enabled by this patch are T124's Jetson TK1 and Venice2
and T210's P2571.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add a comment block to the top of each generated Tegra pinmux header file
indicating that the file was auto-generated, should not be manually
edited, and with a pointer to the tool and command used to generate it.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Spring is the first ARM-based HP Chromebook 11. It is similar to snow
and it uses the same Samsung Exynos5250 chip. But has some unusual
features. Mainline support for it has lagged snow (both in kernel and
U-Boot). Now that the exynos5 code is common we can support spring just
by adding a device tree and a few lines of configuration.
Signed-off-by: Simon Glass <sjg@chromium.org>
Now that most exynos5250 boards can use the generic exynos5 code, switch
over to it and remove the old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Now that exynos5420 boards can use the generic exynos5 code, switch over to
it and remove the old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Some boards use device tree for almost all board-specific configuration.
They therefore do not need their own separate board code, but can all use
the same version. Add a common version of the board code. It uses the
PMIC, regulator and video bridge uclasses. This will support smdk5250,
smdk5420, snow, spring, pit and pi.
Signed-off-by: Simon Glass <sjg@chromium.org>
CPU board (E2530) has a fan - turn it on via GPIO to keep
the SoC cool.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This was done in the 32-bit AVP loader (SPL) but is
board-specific so should be moved to the CPU portion.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Now that the musb-new driver has a Kconfig, we can move Kconfig options to
enable controllers to it, so that it's easier in e.g. menuconfig.
In addition, this allows declaring support for USB_MUSB_HOST/GADGET in
defconfigs instead of the USB_MUSB_SUNXI controller, that will get selected
automatically when needed.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
USB-related options are usually prefixed with CONFIG_USB and platform-specific
adaptation for the MUSB controller already have a CONFIG_USB_MUSB prefix, so
this switches all MUSB-related options to a CONFIG_USB_MUSB prefix, for
consistency.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Disable a few things which interfere with the EFI init. This allows QEMU to
to boot into EFI, load a U-Boot payload then boot to the U-Boot prompt.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Disable a few things which interfere with the EFI init. This allows the
Minnowboard MAX to boot into EFI, load a U-Boot payload then boot to the
U-Boot prompt.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add support for the efi-x86 board, which supports running U-Boot as an
EFI 32-bit application.
Signed-off-by: Ben Stoltz <stoltz@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Intel Bayley Bay board is a BayTrail based board. Add this board
with existing baytrail fsp support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
On Intel BayTrail SoC, there is a legacy UART (I/O 0x3f8) integrated
into the SoC which is enabled by the FSP. Remove the smsc47x superio
initialization codes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
On LS1021A Rev2.0, OCRAM's security level needs to be changed to
non-secure access for SD boot. This patch will allow OCRAM
access permission as R/W in SPL.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Program the external regulator to switch off voltage in deep sleep.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Refactor display code to only setup hdmi if do_enable_hdmi() is invoked.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Add support for selecting display preset using the environment variable
"displaytype". This is a preparation for future merging of compulab
omap3_display.c display selection code with the cm-fx6 display selection code.
The "panel" environment variable is retained for backwards compatibility.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Implement a cm-fx6 specific board_video_skip() to provide the option to not
initialize the display.
The new function does not init display if the environment variable "panel" is
not defined, or if it is set to an unsupported value.
Collateral changes:
- Don't use the global displays array (it's CONFIG_IMX_VIDEO_SKIP specific).
- Don't use detect_hdmi(), since env controlled init makes it unnecessary.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
U-Boot does not explicitly assign the display to an IPU interface. Instead, it
relies on the power-on default of DI0.
Since the kernel reassigns HDMI display to DI1, after a warm reset the HDMI
display no longer works in U-Boot.
Fix this by explicitly assigning HDMI to IPU1 DI0 in U-Boot.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
1. Add DDR script for mx6qpsabreauto board.
2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
and init the enet pll output to 125Mhz.
3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
Build target: mx6qpsabreauto_config
Boot Log:
U-Boot 2015.07-rc2-00071-gfd985ff (Jun 29 2015 - 22:10:55 +0800)
CPU: Freescale i.MX6QP rev1.0 996 MHz (running at 792 MHz)
CPU: Automotive temperature grade (-40C to 125C) at 34C
Reset cause: POR
Board: MX6Q-Sabreauto revA
I2C: ready
DRAM: 2 GiB
PMIC: PFUZE100 ID=0x10
Flash: 32 MiB
NAND: 0 MiB
MMC: FSL_SDHC: 0
*** Warning - bad CRC, using default environment
No panel detected: default to HDMI
Display: HDMI (1024x768)
In: serial
Out: serial
Err: serial
Net: FEC [PRIME]
Hit any key to stop autoboot: 0
Note:
In this patch, we still add a new config mx6qpsabreauto_config,
since SPL is not supported now, and IMX_CONFIG is needed at
build time, so add this config. Future, when SPL is converted,
this config can be removed.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Detect the SOC and board variant at runtime and change the dtb name,
but not hardcoding the fdt_file env variable.
Take the following patch as a reference.
Íd58699b157df75f1aa0b363ea9c21add21a0c
"mx6cuboxi: Load the correct 'fdtfile' variable"
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
sw variable in checkboard function is storing vbank value
which can only take 3-bit value.
So check of sw value for if greater than 7 is redundant.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
eMMC has no CD and WP pins, it needs to add board-specific
board_mmc_getcd() and board_mmc_getwp() in SPL to support
eMMC boot without external SD card inserted.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Add support for NOR flash and GPIO/I2C switch control on RevC.
- NOR support
- bank0/bank4 switch
- SD/eMMC switch
- board version
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Secure Boot Target is added for NAND for P5020 and P5040.
The Secure boot target has already been added for P3041 by
enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM.
The targets for P5020 and P5040 are added in the same manner.
Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Secure Boot Target is added for NAND for P3041.
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF.
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on SRAM configured
at address 0xBFF00000.
In the U-Boot code, TLB entries are created to map the virtual address
0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM.
Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Update PBI command in pbi_cfg files to keep register bit
to default reset value while configuring CPC
as SRAM
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
cpld reset altbank should always reset to bank4 no matter what
current bank is.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Because the function ft_board_setup() delete the USB2 device node, it
leads to can't find the device node and hung up.
In fact only P1020RDB needs to delete the USB2 node, this patch fixes
this issue.
Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
defconfig files are added and SFP version for these platforms
is updated.
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
T1040D4RDB is re-designed T1040RDB board with following changes :
- Support of DDR4 memory
- Support of 0x66 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
- Support of QE-TDM
Similarily T1042D4RDB is a Freescale reference board that hosts the T1040
SoC. T1042D4RDB is re-designed T1042RDB board with following changes :
- Support of DDR4 memory
- Support for 0x86 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
- Support of DIU
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
