Commit graph

13262 commits

Author SHA1 Message Date
Tom Rini
67ece26d8b Xilinx changes for v2021.01
arm64:
 - Support for bigger U-Boot images compiled with PIE
 
 microblaze:
 - Extend support for LE/BE systems
 
 zynqmp:
 - Refactor silicon ID detection code with using firmware interface
 - Add support for saving variables based on bootmode
 
 zynqmp-r5:
 - Fix MPU mapping and defconfig setting.
 
 xilinx:
 - Minor driver changes: names alignment
 - Enable UBIFS
 - Minor DT and macros fixes
 - Fix boot with appended DT
 - Fix distro boot
 
 cmd:
 - pxe: Add fixing for platforms with manual relocation support
 
 clk:
 - fixed_rate: Add DM flag to support early boot on r5
 
 fpga:
 - zynqmppl: Use only firmware interface and enable SPL build
 
 serial:
 - uartlite: Enable for ARM systems and support endians
 
 mmc:
 - zynq: Fix indentation
 
 net:
 - gem: Support for multiple phys
 - emac: Fix 64bit support and enable it for arm64
 
 kconfig:
 - Setup default values for Xilinx platforms
 - Fix dependecies for Xilinx drivers
 - Source board Kconfig only when platform is enabled
 - Fix FPGA Kconfig entry with SPL
 - Change some defconfig values
 
 bindings:
 - Add binding doc for vsc8531
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Merge tag 'xilinx-for-v2021.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2021.01

arm64:
- Support for bigger U-Boot images compiled with PIE

microblaze:
- Extend support for LE/BE systems

zynqmp:
- Refactor silicon ID detection code with using firmware interface
- Add support for saving variables based on bootmode

zynqmp-r5:
- Fix MPU mapping and defconfig setting.

xilinx:
- Minor driver changes: names alignment
- Enable UBIFS
- Minor DT and macros fixes
- Fix boot with appended DT
- Fix distro boot

cmd:
- pxe: Add fixing for platforms with manual relocation support

clk:
- fixed_rate: Add DM flag to support early boot on r5

fpga:
- zynqmppl: Use only firmware interface and enable SPL build

serial:
- uartlite: Enable for ARM systems and support endians

mmc:
- zynq: Fix indentation

net:
- gem: Support for multiple phys
- emac: Fix 64bit support and enable it for arm64

kconfig:
- Setup default values for Xilinx platforms
- Fix dependecies for Xilinx drivers
- Source board Kconfig only when platform is enabled
- Fix FPGA Kconfig entry with SPL
- Change some defconfig values

bindings:
- Add binding doc for vsc8531
2020-09-24 08:33:47 -04:00
Michal Simek
e3259a700a xilinx: r5: Fix MPU setting for R5
Map all resource for R5 to operate properly.
The patch is done based on the commit 23f7b1a776 ("armv7R: K3: am654:
Enable MPU regions") which also map the whole 4GB at first and then change
mapping for DDR.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:41 +02:00
Michal Simek
29bd8ada52 fpga: kconfig: Rename SPL_FPGA_SUPPORT to SPL_FPGA
The patch does sed 's/SPL_FPGA_SUPPORT/SPL_FPGA/g' but also fixing Makefile
and zynqmp.c to simplify if/endif logic in zynqmp.c.

This change is mostly done to be able to use CONFIG_IS_ENABLED macro and
obj-$(CONFIG_$(SPL_)FPGA) in Makefile. For them symbols need to be in sync.

And removing one line from Topic Miami boards which is not needed because
symbol is not enabled via Kconfig.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-23 10:31:41 +02:00
Michal Simek
6cb402f38e ARM: zynqmp: Fix SPL_DM_SPI dependencies
Add missing dependencies for DM_SPI_FLASH.
Kconfig reports it as:
WARNING: unmet direct dependencies detected for SPL_DM_SPI_FLASH
  Depends on [n]: SPL [=n] && SPL_DM [=n]
  Selected by [y]:
  - ARCH_ZYNQMP [=y] && <choice> && SPL_DM_SPI [=y]

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:41 +02:00
Michal Simek
96a60c03b9 arm64: zynqmp: Change bl2_plat_get_bl31_params() guarding
It was protected just for SPL_OS_BOOT but this function is only called when
SPL_ATF is enabled that's why change macro name.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
Saeed Nowshadi
ed6d31c8a6 arm64: zynqmp: Correct value of shunt resistor for VCCINT and VCC_SOC
Value of shunt resistor for INA226s that monitor VCCINT and VCC_SOC power
rails are incorrect.  This patch corrects those values.

Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
2020-09-23 10:31:40 +02:00
Saeed Nowshadi
02abe1fbf3 arm64: zynqmp: Add device tree node for 2nd mux on I2C1 bus
There is 2nd pca9548 mux on I2C1 bus that controls SFP0, SFP1, and QSFP1
ports. Channel 0 and 1 are connected to J287 connector for SFP0 & SFP1, and
channel 2 is connected to J288 connector for QSFP1.

Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
Michal Simek
6ba36c0e59 xilinx: kconfig: Move sourcing of board Kconfig to mach folders
Do not source xilinx board Kconfig by other boards. These configs should be
available only when Xilinx platforms are selected.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
Simon Glass
68de0679c9 binman: sunxi: Add help message for missing sunxi ATF BL31
Add a special help message pointing to the relevant README.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:54:13 -06:00
Simon Glass
cfa3db602c sunxi: Convert 64-bit boards to use binman
At present 64-bit sunxi boards use the Makefile to create a FIT, using
USE_SPL_FIT_GENERATOR. This is deprecated.

Update sunxi to use binman instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-22 12:50:43 -06:00
Edgar E. Iglesias
28c851f128 arm64: Add support for larger PIE U-Boot
Linking a U-Boot larger than 1MB fails with PIE enabled:
u-boot/arch/arm/cpu/armv8/start.S:71:(.text+0x3c): relocation
truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `__rel_dyn_end'
defined in .bss_start section in u-boot.

This extends the supported range by using adrp & add to load symbols
early while starting up.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-22 12:47:28 +02:00
Edgar E. Iglesias
04d13b5d09 arm64: Trap PIE builds early if load address is not 4K aligned
PIE requires a 4K aligned load address. If this is not met, trap
the startup sequence in a WFI loop rather than running into obscure
failures.

Tested-by: Michal Simek <michal.simek@xilinx.com>
Suggested-by: André Przywara <andre.przywara@arm.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-22 12:47:28 +02:00
Edgar E. Iglesias
11f4fbf0d4 arm64: Mention 4K aligned load addresses in the PIE Kconfig help
Mention the requirement of 4K aligned load addresses in the
help section for the POSITION_INDEPENDENT option.

Suggested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-22 12:47:28 +02:00
Tom Rini
2512b3b88b Merge branch '2020-09-14-generic-phy-error-trace' into next
- Add error tracing messages to the generic PHY infrastructure
2020-09-21 16:44:16 -04:00
Tom Rini
751b18b8a1 Merge branch 'master' into next
Merge in v2020.10-rc5
2020-09-21 14:25:37 -04:00
Robert Marko
430e1dcfa4 IPQ40xx: Add USB nodes
There are drivers to support built in USB controller and PHY-s now, so lets add the USB nodes to DTSI.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-18 16:20:47 -04:00
Robert Marko
496a3aa5ff IPQ40xx: Add reset controller support
Since we have a driver for the reset controller, lets add the necessary node.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-18 16:20:47 -04:00
Robert Marko
6ef099b29e IPQ40xx: Add SMEM support
There is already existing driver for SMEM so lets enable it for IPQ40xx as well.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-18 16:20:47 -04:00
Robert Marko
5ae15415c1 IPQ40xx: clk: Use dt-bindings instead of hardcoding
Its common to use dt-bindings instead of hard-coding clocks or resets.
So lets use the imported Linux GCC bindings on IPQ40xx target.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-18 16:20:47 -04:00
Philippe Schenker
bf46474e21 apalis-imx8qm: rename all occurences to apalis-imx8
The Toradex product is called apalis-imx8 consisting of SoM with
i.MX8QM and i.MX8QP SoCs.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-09-17 14:41:33 +02:00
Philippe Schenker
08b6a60ee8 colibri-imx8qxp: rename all occurences to colibri-imx8x
The Toradex product is called colibri-imx8x consisting of SoM with
i.MX8QXP and i.MX8DX SoCs.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-09-17 14:41:26 +02:00
Marek Vasut
d1a7205532 ARM: mx6: ddr: Add support for iMX6UL/ULL/SL/SDL
This patch adds support for iMX6UL/ULL/SL/SDL MMDC into the DDR calibration
code. The difference between MX6DQ and MX6UL/ULL/SL is that the later SoCs
have 2 SDQS registers, just like MX6SX, while the MX6DQ/MX6SDL has 8.

Fixes: 4f4c128c65 ("ARM: mx6: ddr: Add support for iMX6SX")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eric Nelson <eric@nelint.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-09-17 14:40:55 +02:00
Peng Fan
0098222dac imx8mp: Remove parts MIMX8ML7 and MIMX8ML5 support
Latest datasheet revE has removed MIMX8ML7D/5D/7C/5C parts, so
update u-boot to remove decoding and support for those parts.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-09-17 14:40:22 +02:00
Peng Fan
a3e7d51fd5 imx8m: clock_imx8mm: add missed return
Add missed return

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-09-17 14:40:17 +02:00
Peng Fan
ece7844d8f imx8mq: fix SSCG_PLL_REFCLK_SEL_x
Fix SSCG_PLL_REFCLK_SEL_x, the offset starts from 0, not 16

Reported-by: Coverity 3448860
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
2020-09-17 14:40:10 +02:00
Peng Fan
d81e8cf6ea imx8mq: fix FRAC_PLL_REFCLK_SEL_MASK
Coverity reported dead code, however it is FRAC_PLL_REFCLK_SEL_MASK
was wrongly set.

Reported-by: Coverity 10045172
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
2020-09-17 14:40:04 +02:00
Peng Fan
95bae9ff92 imx7: ccm: correct target interface num
According to i.MX 7Dual Applications Processor Reference Manual, Rev. 1
The target interface CCM root index ranges [0,124], so the number
should be 125.

Reported-by: Coverity 18045
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
2020-09-17 14:39:55 +02:00
Heinrich Schuchardt
5b861eea79 rockchip: make_fit_atf: ignore empty PT_LOAD segment
The linker sometimes creates PT_LOAD segments with length (p_filesz) zero
as described in https://man7.org/linux/man-pages/man5/elf.5.html. This
leads to build failures. We should ignore empty segments.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-09-16 16:41:30 +08:00
Kever Yang
fe4931c09a rockchip: rv1108: Enable grf as pre-reloc node
The grf node will be used before relocate, enable it in dts.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-09-16 16:31:18 +08:00
Tom Rini
bd4e8944cf Merge tag 'ti-v2021.01-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti into next
- Hyperflash boot for J7200
- Update Main R5FSS lockstep mode
- R5F remoteproc support for J7200
- Minor env fixes
- Add SPI boot support for am335x-icev2
2020-09-15 15:22:00 -04:00
Faiz Abbas
41cf3cb39d arm: mach-omap2: am33xx: Add device structure for spi
Add platform data and a device structure for the spi device
present on am335x-icev2. This requires moving all omap3_spi
platform data structures and symbols to an omap3_spi.h so that
the board file can access them.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-09-15 18:51:53 +05:30
Faiz Abbas
38e6ddc4d7 arm: dts: am335x-icev2: Add spi node
Add spi and spi nor flash nodes for am335x-icev2.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-09-15 18:51:53 +05:30
Suman Anna
70377b7279 arm: dts: k3-j7200-r5: Add fs_loader node
Add a generic fs_loader node to the K3 J7200 R5 common board dts
file and use it as the chosen firmware-loader so that it can be
used for loading various firmwares from a boot media/filesystem
in R5 SPL on K3 J7200 EVM.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Suman Anna
3f7e032f70 arm: dts: k3-j7200-main: Add MAIN domain R5F cluster nodes
The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster is present within the MCU
domain (MCU_R5FSS0), and the other one is present within the MAIN
domain (MAIN_R5FSS0). Each of these can be configured at boot time
to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode
to provide a larger 128 KB of memory.

Add the DT node for the MAIN domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in Split-mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Suman Anna
10c4de02f0 arm: dts: k3-j7200-mcu: Add MCU domain R5F cluster node
The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster is present within the MCU
domain (MCU_R5FSS0), and the other one is present within the MAIN
domain (MAIN_R5FSS0). Each of these can be configured at boot time
to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode
to provide a larger 128 KB of memory.

Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in LockStep mode by default, with
the ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Suman Anna
7873e9df8f armv8: K3: j7200: Add custom MMU support
The A72 U-Boot code can load and boot a number of the available
R5FSS Cores on the J7200 SoC. Change the memory attributes for the
DDR regions used by the remote processors so that the cores can see
and execute the proper code.

The J7200 SoC has less number of remote processors compared to J721E,
so use less memory for the remote processors. So, a separate table
based on the current J721E table is added for J7200 SoCs, and selected
using the appropriate Kconfig CONFIG_TARGET_J7200_A72_EVM symbol.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Suman Anna
31defbd347 arm: dts: k3-j721e-main: Configure MAIN R5FSS1 for Split-mode
Switch the MAIN R5FSS1 cluster to be configured for Split-mode as the
default so that two different applications can be run on each of the
R5F cores in performance mode. LockStep-mode would be available only
on SoCs efused with the appropriate bit, and Split-mode is the mode
that is available on all J721E SoCs.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Vignesh Raghavendra
c07d06855e ARM: dts: k3-j7200-r5-common-proc-board: Enable HyperFlash
Enable HyperBus and HyperFlash to support HyperFlash boot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-09-15 18:51:53 +05:30
Vignesh Raghavendra
7ce6c8ae58 arm: mach-k3: Add HyperFlash boot mode support
HBMC controller on TI K3 SoC provides MMIO access to HyperFlash similar
to legacy Parallel CFI NOR flashes. Therefore alias HyperFlash bootmode
to NOR boot to enable SPL to load next stage using NOR boot flow.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-09-15 18:51:52 +05:30
Mingming Lee
75fb7b9163 ARM: MediaTek: amend IC description for MediaTek MT8512
The description for MT8512  has some mistake, so correct it.

Signed-off-by: Mingming Lee <Mingming.Lee@mediatek.com>
2020-09-12 10:53:01 -04:00
Thirupathaiah Annapureddy
0b65e494e9 arm: dts: fix ast2500-evb inclusion for the correct soc family
Include ast2500-evb.dtb for CONFIG_ASPEED_AST2500 instead of
for all aspeed targets.

ast2400 is based on ARM926EJ-S processor (ARMv5-architecture).
ast2500 is based on ARM1176JZS processor (ARMv6-architecture).
ast2600 is based on Cortex A7 processor (ARMv7-A architecture).
Each of the above SOC is using a different ARM CPU(s) with different ARM
architecture revision. It is not possible to support all 3 of these
families in a single binary. So there is no need to build ast2500-evb.dtb
for other SOC families.

Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com>
2020-09-10 11:17:46 -04:00
Ryan Chen
654ae299ec cosmetic: aspeed: Modify for SPDX-License
Modify SPDX-License for furture patch warning

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-09-09 16:57:36 -04:00
Ryan Chen
c39c9a94cb clock:aspeed: Sync with Linux kernel clock header define
v2: modify title description aspeed:clock -> clock:aspeed

Use kernel include/dt-bindings/clock/aspeed-clock.h define
for clock driver.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-09-09 16:57:35 -04:00
Ryan Chen
15b87feb2b cosmetic: aspeed: ast2500: Rename clock header
Rename the ast2500-scu.h to aspeed-clock.h.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
2020-09-09 16:57:35 -04:00
Marek Vasut
b6055945d6 ARM: dts: stm32: Adjust PLL4 settings on AV96 again
PLL4Q is supplying both FDCAN and LTDC. In case HDMI is in use, the
50 MHz generated from PLL4Q cannot be divided well enough to produce
accurate clock for HDMI pixel clock. Adjust it to generate 74.25 MHz
instead. The PLL4P/PLL4R are generating 99 MHz instead of 100 MHz,
which is in tolerance for the SDMMC.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Gerald Baeza <gerald.baeza@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-09 15:02:23 +02:00
Marek Vasut
43e2d1dd47 ARM: dts: stm32: Pull UART4 RX high on AV96
There is no dedicated pull resistor on the AV96 UART4 (console UART)
pin. In case there is no UART adapter installed on the AV96, the line
is floating and can trigger reception of garbage characters, which in
turn can abort U-Boot autoboot. Add default pull up to mitigate this
problem.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-09 15:01:53 +02:00
Patrick Delaunay
cf8df34015 arm: stm32mp: cleanup test on eth_env_set_enetaddr result
Remove the unnecessary inversion on the eth_env_set_enetaddr() result which
only make complex the code of setup_mac_address() and display an invalid
value in the associated pr_err.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2020-09-09 14:19:12 +02:00
Patrick Delaunay
93d3bc5f8d arm: meson: change trace level for phy errors managed by uclass
As the error message is now displayed by generic phy functions,
the pr_err can be change to pr_debug.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
2020-09-08 08:46:32 -04:00
Tom Rini
9bfb567e5f Merge branch 'master' of git://git.denx.de/u-boot-usb
- Mostly DFU fixes and r8152 fixes
2020-09-03 09:48:28 -04:00
Chee Hong Ang
6b6307ed22 arm: socfpga: soc64: Check FPGA Config status register before bridge reset
Instead of querying SDM for FPGA configuration status through mailbox
messages, U-Boot now checks System Manager's FPGA Config status register
for FPGA configuration status before resetting bridge.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-09-03 11:26:07 +08:00