Commit graph

20 commits

Author SHA1 Message Date
Alexey Brodkin
227ad7b2b6 net: designware: Respect "bus mode" register contents on SW reset
"bus mode" register contains lots of fields and some of them don't
expect to be written with 0 (zero). So since we're only interested in
resetting MAC (which is done with setting the least significant bit of
this register with "0") I believe it's better to modify only 1 bit of
the register.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Vipin Kumar <vipin.kumar@st.com>
Patch: 277864
2013-11-22 16:50:54 -06:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Vipin Kumar
7091915ad7 net/designware: Do not select MIIPORT for RGMII interface
Do not select MIIPORT for RGMII interface

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Acked-by: Stefan Roese <sr@denx.de>
2013-06-24 19:10:16 -05:00
Dinh Nguyen
66f119e50c net/designware: Consecutive writes to the same register to be avoided
This commit is an add-on to f6c4191f. There are a few registers where
consecutive writes to the same location should be avoided or have a delay.

According to Synopsys, here is a list of the registers and bit(s) where
consecutive writes should be avoided or a delay is required:

DMA Registers:
Register 0        Bit 7
Register 6        All bits except for 24, 16-13, 2-1.

GMAC Registers:
Registers 0-3     All bits
Registers 6-7     All bits
Register 10       All bits
Register 11       All bits except for 5-6.
Registers 16-47   All bits
Register 48       All bits except for 18-16, 14.
Register 448      Bit 4.
Register 459      Bits 0-3.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Matthew Gerlach <mgerlach@altera.com>
Acked-by: Amit Virdi <amit.virdi@st.com>
2012-07-11 13:15:31 -05:00
Stefan Roese
ef76025a99 net: Multiple updates/enhancements to designware.c
This patch adds the following changes to designware ethernet driver
found on the ST SPEAr SoC:

- Don't init MAC & PHY upon startup. This causes a delay, waiting for
  the auto negotiation to complete. And we don't want this delay to
  always happen. Especially not on platforms where ethernet is not
  used at all (e.g. booting via flash).
  Instead postpone the MAC / PHY configuration to the stage, where
  ethernet is first used.
- Add possibility for board specific PHY init code. This is needed
  for example on the X600 board, where the Vitesse PHY needs to be
  configured for GMII mode.
  This board specific PHY init is done via the function
  designware_board_phy_init(). And this driver now adds a weak default
  which can be overridden by board code.
- Use common functions miiphy_speed() & miiphy_duplex() to read
  link status from PHY.
- Print status and progress of auto negotiation.
- Print link status (speed, dupex) upon first usage.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@gmail.com>
2012-07-07 14:07:42 +02:00
Vipin Kumar
9afc1af01f SPEAr: Add interface information in initialization
Few Designware peripheral registers need to be modified based on the
ethernet interface selected by the board. This patch supports interface
information in ethernet driver

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-07-07 14:07:40 +02:00
Joe Hershberger
10cbe3b6a4 net: Fix remaining API interface breakage
These are all the files which use the API incorrectly but did not get
built using MAKEALL -a powerpc|arm.  I have no compiler for them, but
the remaining issues should be far less than without this patch.

Any outstanding issues are left to the maintainers of boards that use
these drivers.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-23 14:19:21 -05:00
Amit Virdi
cafabe1995 net/designware: Change timeout loop implementation
The new implementation changes the timeout loop implementation to avoid 1 ms
delay in each failing test. It also configures the delay to 10usec.

Signed-off-by: Amit Virdi <amit.virdi@st.com>
2012-04-04 10:47:53 -05:00
Armando Visconti
20a5dde149 net/designware: Set ANAR to 0x1e1
This patch forces the advertised capabilities during auto
negotiation to always be 10/100 Mbps and half/full as duplexing.

Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
2012-04-04 10:47:40 -05:00
Vikas Manocha
e25c90b45c net/designware: Program phy registers when auto-negotiation is ON
If AN(auto-negotiation) is ON, speed bit of control register are not
applicable.  Also phy registers were not getting programmed as per the
result of AN. This patch sets only AN bit & restart AN bit for AN ON
selection & programs PHY registers as per AN result.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
2012-04-04 10:47:34 -05:00
Vipin Kumar
13edd1706c net/designware: Try configuring phy on each dw_eth_init
Phy autonegotiation works only when the ethernet cable is plugged in.
Since the phy was configured only at the init time, a plugged in cable
was necessary to initialize the phy properly.

This patch keeps a flag to check if the phy initialization has
succeeded, and calls configure_phy routine at every init if this flag
reports otherwise.

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
2012-04-04 10:47:21 -05:00
Armando Visconti
aa51005c3f net/designware: Consecutive writes must have delay
This patch solves a TX/RX problem which happens at 10Mbps, due to the
fact that we are not respecting 4 cyles of the phy_clk (2.5MHz) between
two consecutive writes on the same register.

Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
2012-04-04 10:47:09 -05:00
Vipin KUMAR
024333c96f net/designware: Phy address fix
The code assumes the phy address to be > 0, which is not true, the phy address
can be in the range 0-31.

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
2012-04-04 10:46:59 -05:00
Vipin KUMAR
c7f6dbe736 net/designware: Fix to restore hw mac address
The network controller mac resets hardware address stored in MAC_HI and MAC_LO
registers if mac is resetted. So, hw mac address needs to be restored in case
mac is explicitly resetted from driver.

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
2012-04-04 10:46:39 -05:00
Simon Glass
7616e78508 Add Ethernet hardware MAC address framework to usbnet
Built-in Ethernet adapters support setting the mac address by means of a
ethaddr environment variable for each interface (ethaddr, eth1addr, eth2addr).

This adds similar support to the USB network side, using the names
usbethaddr, usbeth1addr, etc. They are kept separate since we don't want
a USB device taking the MAC address of a built-in device or vice versa.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Eric Bénard <eric@eukrea.com>
2011-08-08 21:05:23 +02:00
Mike Frysinger
f0ece9e934 net: designware: fix uninitialized phy_addr usage
When CONFIG_DW_SEARCH_PHY is disabled, the local phy_addr variable
never gets initialized which causes random behavior at runtime and a
gcc warning.  So set it by default to the stored phy address.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Reviewed-by: Vipin Kumar <vipin.kumar@st.com>

Fix commit message.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-07-25 22:20:10 +02:00
Mike Frysinger
ee7f5bfd12 net: designware: fix unused warning when CONFIG_DW_AUTONEG is enabled
The ctrl variable is only used when autoneg support is disabled, so only
declare it under those conditions to avoid an unused variable warning.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Reviewed-by: Vipin Kumar <vipin.kumar@st.com>
2011-07-25 22:19:40 +02:00
Mike Frysinger
8ef583a035 miiphy: convert to linux/mii.h
The include/miiphy.h header duplicates a lot of things from linux/mii.h.
So punt all the things that overlap to keep the API simple and to make
merging between U-Boot and Linux simpler.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-01-09 18:06:50 +01:00
Mike Frysinger
5700bb6352 miiphy: constify device name
The driver name does not need to be writable, so constify it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-08-09 11:52:29 -07:00
Vipin KUMAR
5b1b1883ff SPEAr : Network driver support added
Designware network driver support added.
This is a Synopsys ethernet controller

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-07-12 00:08:05 -07:00