This fixes below build error when CC_OPTIMIZE_FOR_DEBUG is enabled and
CONFIG_FPGA or CONFIG_SPL_FPGA are not enabled.
When CC_OPTIMIZE_FOR_DEBUG is enabled, unused code will not be optimized
out. Hence, fpga_load function must have a dummy implementation to avoid
the build error.
../common/spl/spl_fit.c:591: undefined reference to `fpga_load'
collect2: error: ld returned 1 exit status
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Link: https://lore.kernel.org/r/20230831075247.137501-1-chanho61.park@samsung.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
This is always defined to 5, so use that as the default.
Cc: Michal Simek <michal.simek@amd.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Add supporting new compatible string "u-boot,zynqmp-fpga-enc" to
handle loading encrypted bitfiles.
This feature requires encrypted FSBL, as according to UG1085:
"The CSU automatically locks out the AES key, stored in either BBRAM
or eFUSEs, as a key source to the AES engine if the FSBL is not
encrypted. This prevents using the BBRAM or eFUSE as the key source
to the AES engine during run-time applications."
Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Link: https://lore.kernel.org/r/20220722141614.297383-14-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek <michal.simek@amd.com>
Add a "compatible" string to binary flag converter, which uses
a callback str2flag() of given FPGA driver if available.
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Tested-by: Ricardo Salveti <ricardo@foundries.io>
Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Link: https://lore.kernel.org/r/20220722141614.297383-8-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek <michal.simek@amd.com>
These flags may be used to check whether an FPGA driver is able to
load a particular FPGA bitstream image.
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Tested-by: Ricardo Salveti <ricardo@foundries.io>
Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Link: https://lore.kernel.org/r/20220722141614.297383-7-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek <michal.simek@amd.com>
In cmd/fpga.c the commands should return enum command_ret_t, e.g.
CMD_RET_USAGE, CMD_RET_SUCCESS, or CMD_RET_FAILURE. What they actually
do is passing a return value from different 'fpga_' functions.
Passing on a return value of -1 from a called function leads to printing
out usage text. In case of actually correct usage with correctly
specified parameters but some fail at runtime printing out that usage
text is distracting.
The reason is most 'fpga_' functions return either FPGA_SUCCESS or
FPGA_FAIL, the latter was equal to -1 which is the same value as
CMD_RET_USAGE. So just passing on FPGA_FAIL lead to printing out usage.
We should only return CMD_RET_USAGE in cases, where the user sent wrong
input. Every other case should return CMD_RET_SUCCESS or
CMD_RET_FAILURE, and not simply pass an error code.
Simply changing FPGA_FAIL from -1 to 1 gets the job done.
Suggested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Ensure the string for filename is always constant, otherwise it can be
corrupted by the writing.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds support to load secure bitstreams(authenticated or
encrypted or both). As of now, this feature is added and tested only
for xilinx bitstreams and the secure bitstream was generated using
xilinx bootgen tool, but the command is defined in more generic way.
Command example to load authenticated and device key
encrypted bitstream is as follows
"fpga loads 0 100000 2000000 0 1"
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.
Signed-off-by: Tom Rini <trini@konsulko.com>
This drops the limit that fpga is only loaded from FIT images for Xilinx.
This is done by moving the 'partial' check from 'common/image.c' to
'drivers/fpga/xilinx.c' (the only driver supporting partial images yet)
and supplies a weak default implementation in 'drivers/fpga/fpga.c'.
Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Tested-by: Michal Simek <michal.simek@xilinx.com> (On zcu102)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add bitstream type BIT_NONE to the bitstream type
enum. This might be useful while loading bitstreams
in respective drivers.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This problem is reported by checkpatch.pl
Warnings:
CHECK: extern prototypes should be avoided in .h files
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Added support to load partial bitstreams.
The partial bitstreams can be loaded using the below commands
Commands:
fpga loadp <dev> <addr> <size>
fpga loadbp <dev> <addr> <size>
The full bit streams can be loaded using the
old commands(fpga load and fpga loadb).
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Clean up partial, full and compressed bitstream handling.
U-Boot supports full bitstream loading and partial
based on detection which is not 100% correct.
Extending fpga_load/fpga_loadbitstream() with one more
argument which stores bitstream type.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
All these macros are completely unused by any code.
CONFIG_FPGA is not a bitfield anymore.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
Ensure that wrong bitstream won't be loaded
to current device.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
All fpga functions use devnum as int. Only fpga_loadbitstream
is using it as unsinged long dev.
This patch synchronize it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
In bitstream decoding you can directly check device
which you want to load and in fpga.c are fpga_validate
and fpga_dev_info functions which should be used for it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.
All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.
Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.
Signed-off-by: York Sun <yorksun@freescale.com>
Fix compiler warning:
cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data'
from incompatible pointer type
Adding the needed 'const' here entails a whole bunch of additonal
changes all over the FPGA code.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andre Schwarz <andre.schwarz@matrix-vision.de>
Cc: Murray Jensen <Murray.Jensen@csiro.au>
Acked-by: Andre Schwarz<andre.schwarz@matrix-vision.de>
The patch adds support to load a Lattice's bitstream
image (called VME file) into a Lattice FPGA. The code
containing the state machine delivered as part of
Lattice's ispVMtools is integrated.
The FPGA is programmed using the JTAG interface. The
board maintainer must provide accessors to drive the
JTAG signals TCK, TMS, TDI and to get the value of the
input signal TDO.
Signed-off-by: Stefano Babic <sbabic@denx.de>
PPC boards are the only users of the current FPGA code which is littered
with manual relocation fixups. Now that proper relocation is supported
for PPC boards, remove FPGA manual relocation.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).
Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.
Signed-off-by: Wolfgang Denk <wd@denx.de>
