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fpga: Remove all CONFIG_SYS_* fpga related options

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All these macros are completely unused by any code.
CONFIG_FPGA is not a bitfield anymore.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
This commit is contained in:
Michal Simek 2013-05-01 18:05:56 +02:00
parent 6631db4773
commit b03b25caea
10 changed files with 6 additions and 60 deletions
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17
include/altera.h
View file

@ -27,23 +27,6 @@
#ifndef _ALTERA_H_
#define _ALTERA_H_
/* Altera Model definitions
*********************************************************************/
#define CONFIG_SYS_ACEX1K CONFIG_SYS_FPGA_DEV( 0x1 )
#define CONFIG_SYS_CYCLON2 CONFIG_SYS_FPGA_DEV( 0x2 )
#define CONFIG_SYS_STRATIX_II CONFIG_SYS_FPGA_DEV( 0x4 )
#define CONFIG_SYS_ALTERA_ACEX1K (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_ACEX1K)
#define CONFIG_SYS_ALTERA_CYCLON2 (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_CYCLON2)
#define CONFIG_SYS_ALTERA_STRATIX_II (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_STRATIX_II)
/* Add new models here */
/* Altera Interface definitions
*********************************************************************/
#define CONFIG_SYS_ALTERA_IF_PS CONFIG_SYS_FPGA_IF( 0x1 ) /* passive serial */
#define CONFIG_SYS_ALTERA_IF_FPP CONFIG_SYS_FPGA_IF( 0x2 ) /* fast passive parallel */
/* Add new interfaces here */
typedef enum { /* typedef Altera_iface */
min_altera_iface_type, /* insert all new types after this */
passive_serial, /* serial data and external clock */

2
include/configs/M54455EVB.h
View file

@ -238,7 +238,7 @@
/* FPGA - Spartan 2 */
/* experiment
#define CONFIG_FPGA CONFIG_SYS_SPARTAN3
#define CONFIG_FPGA
#define CONFIG_FPGA_COUNT 1
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_CHECK_CTRLC

2
include/configs/MERGERBOX.h
View file

@ -606,7 +606,7 @@
* FPGA
*/
#define CONFIG_FPGA_COUNT 1
#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
#define CONFIG_FPGA
#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_CYCLON2

2
include/configs/MVBC_P.h
View file

@ -310,7 +310,7 @@
#undef FPGA_DEBUG
#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
#define CONFIG_FPGA
#define CONFIG_FPGA_ALTERA 1
#define CONFIG_FPGA_CYCLON2 1
#define CONFIG_FPGA_COUNT 1

2
include/configs/MVBLM7.h
View file

@ -499,7 +499,7 @@
""
#define CONFIG_FPGA_COUNT 1
#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
#define CONFIG_FPGA
#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_CYCLON2

2
include/configs/MVSMR.h
View file

@ -280,7 +280,7 @@
#undef FPGA_DEBUG
#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_FPGA CONFIG_SYS_XILINX_SPARTAN2
#define CONFIG_FPGA
#define CONFIG_FPGA_XILINX 1
#define CONFIG_FPGA_SPARTAN2 1
#define CONFIG_FPGA_COUNT 1

2
include/configs/omap3_mvblx.h
View file

@ -273,7 +273,7 @@
#endif /* (CONFIG_CMD_NET) */
#define CONFIG_FPGA_COUNT 1
#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
#define CONFIG_FPGA
#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_CYCLON2
#define CONFIG_SYS_FPGA_PROG_FEEDBACK

10
include/fpga.h
View file

@ -31,16 +31,6 @@
#define CONFIG_MAX_FPGA_DEVICES 5
#endif
/* CONFIG_FPGA bit assignments */
#define CONFIG_SYS_FPGA_MAN(x) (x)
#define CONFIG_SYS_FPGA_DEV(x) ((x) << 8 )
#define CONFIG_SYS_FPGA_IF(x) ((x) << 16 )
/* FPGA Manufacturer bits in CONFIG_FPGA */
#define CONFIG_SYS_FPGA_XILINX CONFIG_SYS_FPGA_MAN( 0x1 )
#define CONFIG_SYS_FPGA_ALTERA CONFIG_SYS_FPGA_MAN( 0x2 )
/* fpga_xxxx function return value definitions */
#define FPGA_SUCCESS 0
#define FPGA_FAIL -1

3
include/lattice.h
View file

@ -278,9 +278,6 @@ typedef struct {
char *desc; /* description string */
} Lattice_desc; /* end, typedef Altera_desc */
/* Lattice Model Type */
#define CONFIG_SYS_XP2 CONFIG_SYS_FPGA_DEV(0x1)
/* Board specific implementation specific function types */
typedef void (*Lattice_jtag_init)(void);
typedef void (*Lattice_jtag_set_tdi)(int v);

24
include/xilinx.h
View file

@ -27,30 +27,6 @@
#ifndef _XILINX_H_
#define _XILINX_H_
/* Xilinx Model definitions
*********************************************************************/
#define CONFIG_SYS_SPARTAN2 CONFIG_SYS_FPGA_DEV( 0x1 )
#define CONFIG_SYS_VIRTEX_E CONFIG_SYS_FPGA_DEV( 0x2 )
#define CONFIG_SYS_VIRTEX2 CONFIG_SYS_FPGA_DEV( 0x4 )
#define CONFIG_SYS_SPARTAN3 CONFIG_SYS_FPGA_DEV( 0x8 )
#define CONFIG_SYS_ZYNQ CONFIG_SYS_FPGA_DEV(0x10)
#define CONFIG_SYS_XILINX_SPARTAN2 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN2)
#define CONFIG_SYS_XILINX_VIRTEX_E (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX_E)
#define CONFIG_SYS_XILINX_VIRTEX2 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX2)
#define CONFIG_SYS_XILINX_SPARTAN3 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN3)
#define CONFIG_SYS_XILINX_ZYNQ (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_ZYNQ)
/* XXX - Add new models here */
/* Xilinx Interface definitions
*********************************************************************/
#define CONFIG_SYS_XILINX_IF_SS CONFIG_SYS_FPGA_IF( 0x1 ) /* slave serial */
#define CONFIG_SYS_XILINX_IF_MS CONFIG_SYS_FPGA_IF( 0x2 ) /* master serial */
#define CONFIG_SYS_XILINX_IF_SP CONFIG_SYS_FPGA_IF( 0x4 ) /* slave parallel */
#define CONFIG_SYS_XILINX_IF_JTAG CONFIG_SYS_FPGA_IF( 0x8 ) /* jtag */
#define CONFIG_SYS_XILINX_IF_MSM CONFIG_SYS_FPGA_IF( 0x10 ) /* master selectmap */
#define CONFIG_SYS_XILINX_IF_SSM CONFIG_SYS_FPGA_IF( 0x20 ) /* slave selectmap */
/* Xilinx types
*********************************************************************/
typedef enum { /* typedef Xilinx_iface */