Commit graph

3310 commits

Author SHA1 Message Date
Icenowy Zheng
39858b12cc sunxi: add PRCM secure switch register definition
Some new Allwinner SoCs' PRCM has a secure switch register, which
controls the access to some clock and power registers in PRCM block.

Add the definition of this register and its bits in the PRCM header
file.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-11 15:49:39 +05:30
Suji Velupillai
c89782dcac net: move Broadcom SF2 driver to Kconfig
move to Kconfig:
	CONFIG_BCM_SF2_ETH
	CONFIG_BCM_SF2_ETH_DEFAULT_PORT
	CONFIG_BCM_SF2_ETH_GMAC

Also modified defconfigs of all platforms that use these configs.

Signed-off-by: Suji Velupillai <suji.velupillai@broadcom.com>
Tested-by: Suji Velupillai <suji.velupillai@broadcom.com>
Reviewed-by: JD Zheng <jiandong.zheng@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Steve Rae <steve.rae@raedomain.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-08-07 15:18:30 -05:00
Tom Rini
fe84c48eeb Xilinx changes for v2017.09
Zynq:
 - Add Z-Turn board support
 
 fpga:
 - Remove intermediate buffer from code
 
 Zynqmp:
 - dts cleanup
 - change psu_init handling
 - Add options to get silicon version
 - Fix time handling
 - Map OCM/TCM via MMU
 - Add new clock driver
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iEYEABECAAYFAlmBs2kACgkQykllyylKDCFUGgCgmfop8Ki5+6QI7XQRP7u8nhjw
 KakAn1sYIRDFQ34AoxmiYa6RTmjepLMv
 =1Gh3
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2017.09' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2017.09

Zynq:
- Add Z-Turn board support

fpga:
- Remove intermediate buffer from code

Zynqmp:
- dts cleanup
- change psu_init handling
- Add options to get silicon version
- Fix time handling
- Map OCM/TCM via MMU
- Add new clock driver
2017-08-04 07:23:32 -04:00
Tom Rini
ec7483e34e Merge git://git.denx.de/u-boot-fsl-qoriq
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	include/configs/ls1046aqds.h
	include/configs/ls1046ardb.h
2017-08-02 10:52:26 -04:00
Siva Durga Prasad Paladugu
74ba69db35 arm64: zynqmp: Make chip_id routine to handle based on el.
Modify chip_id() routine such that to handle based on
the current el. Also make it available even if FPGA is
not enabled in system such it can be used always.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Siva Durga Prasad Paladugu
f52bf5a3dd arm64: zynqmp: Make chip_id a global routine()
This patch makes chip_id() as a global routine so that
it can be used in other places as required.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Siva Durga Prasad Paladugu
db3123b40d arm64: zynqmp: Modify chip_id routine to get either idcode or version
This patch modifies the chip_id routine to get either idcode or
silicon version based on the argument received.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Siva Durga Prasad Paladugu
4b5b0fcd21 arm64: zynqmp: Dont write to system timestamp generator
Remove incorrect code of writing to system timestamp
counter registers. This register writes does nothing
and can be removed.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Siva Durga Prasad Paladugu
a076789efe arm64: zynqmp: Define a way to intialize TCM
TCM on ZynqMP needs to be intialized in a sequence
and this patch provides a global routine to perform
this as per requirement.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Santan Kumar
ec8a7d7743 soc/fsl-layerscape: Update SVR number for LS2081A and LS2041A
Update SVR as per the SOC document.
 -LS2081A: 0x870919 -> 0x870918
 -LS2041A: 0x870915 -> 0x870914

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-01 08:28:56 -07:00
Alison Wang
020b3ce8ae armv8: Remove duplicate definition for IH_ARCH_ARM and IH_ARCH_ARM64
The duplicate definitions for IH_ARCH_ARM and IH_ARCH_ARM64 are removed.
The definitions in <image.h> are used.

According to this modification, the comparison between os arch and cpu
arch is done in C programming instead of ASM programming.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-01 08:28:56 -07:00
Tom Rini
211aaf309c Merge git://git.denx.de/u-boot-usb 2017-07-29 11:43:51 -04:00
Bin Meng
cbb89ed026 configs: Remove CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS in all boards
Now that EHCD does not use CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS,
remove it in all boards' config files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2017-07-28 23:34:24 +02:00
Simon Glass
000f15fa15 dm: tegra: Convert clock_decode_periph_id() to support livetree
Adjust this to take a device as a parameter instead of a node.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
be7890927a dm: tegra: Convert USB setup to livetree
Adjust this code to support a live device tree. This should be implemented
as a PHY driver but that is left as an exercise for the maintainer.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
66de3eee79 tegra: tegra124: Add a PMC syscon driver
The PMC can be modelled as a syscon peripheral. Add a driver for this
so that it can be accessed by drivers when needed. Enable it for tegra124
boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Philipp Tomsich
01106571ad rockchip: clk: rk3399: remove unused fields from priv-structures
This removes the unused 'rate' field from both rk3399_pmuclk_priv and
rk3399_clk_priv. I didn't bother to check where this came from (i.e.
what the historical context of these was), but only verified that
these are indeed unused across all code-paths.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-27 14:59:02 +02:00
Philipp Tomsich
80c83e8190 rockchip: clk: rk3368: remove unused fields from rk3368_clk_priv
The rk3368_clk_priv has two unused fields: rate, has_bwadj. This
removes them as there's no need for either (i.e. has_bwadj is always
true for the RK3368, according to its TRM).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-27 14:59:02 +02:00
Philipp Tomsich
700f3108d3 rockchip: spl: make boot0 hook TPL safe
When building for a TPL/SPL setup (e.g. on the RK3368), we need the
TPL stage to have the extra space for for the 'Rockchip SPL name'
(i.e. 'RK33' word).  Yet, the SPL will start execution at its first
word (i.e. the first word in the SPL binary needs to be a valid
instruction).  To make things a bit more involved, CONFIG_SPL_BUILD
is defined both for the SPL and the TPL stage.

To avoid having to explicitly test for the first stage (TPL, if and
only if TPL and SPL are built, SPL otherwise), this commit modifies
the sequence to repeat the 'b reset' (instead of reserving 4 bytes
of undefined space) at the start of the boot0 hook: if overwritten
(and execution starts at the second word), the first instruction is
still a 'b reset'... if not overwritten, we start on a 'b reset' as
well.

This solution wouldn't even require the check whether we are in the
SPL/TPL build (i.e. CONFIG_SPL_BUILD), but we leave this check in for
documentation purposes.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-27 14:59:02 +02:00
Kever Yang
06f4e36baf rockchip: pwm: add mask for config setting
Use mask to clear old setting before direct set the new config,
or else there it will mess up the config when it's not the same
with default value.

Fixes: 3851059 rockchip: Setup default PWM flags
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Philipp Tomsich
cb91173a7f rockchip: timer: make register sizes explicit
We are about to reuse the rockchip timer (header file) for 64bit ARMv8
chips, so it seems a good time to make the register sizes explicit by
changing from 'unsigned int' to 'u32'.

Reorders the header-includes in rk_timer.c to ensure that 'u32' is
definded before it is used by 'asm/arch/timer.h'.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:00 +02:00
Patrice Chotard
9242ece12b ram: stm32: migrate fmc defines in driver file
Migrate all FMC defines from arch/arm/include/asm/arch-stm32f7/fmc.h
to drivers/ram/stm32_sdram.c

This will avoid to add an additionnal arch-stm32xx/fmc.h file when
a new stm32 family soc will be introduced.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-26 11:29:07 -04:00
Patrice Chotard
81d0128d2b clk: stm32f7: remove clock_get()
All drivers which was using clock_get() are now using
clk_get_rate() from clock framework, now it's safe to
remove clock_get().

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:28:08 -04:00
Patrice Chotard
b9e86511d1 clk: stm32f7: cleanup clocks unused definitions
clean the code by removing unused enums, structs and
defines related to clocks

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:26:54 -04:00
Patrice Chotard
288f17e648 clk: stm32f7: add clock .get_rate() callback
Add clock framework .get_rate callback.
This step will allow to convert all drivers which was using
proprietary clock_get() to use clock framework .get_rate().

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:26:53 -04:00
Patrice Chotard
704e954cee clk: stm32f7: add static for configure_clocks()
Also remove its declaration from stm32.h which
is no more needed.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:26:53 -04:00
Beniamino Galvani
2009a8d03f pinctrl: meson: add GPIO support
This commit adds GPIO support to the Amlogic Meson pin controller
driver, based on code from Linux kernel.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
2017-07-26 11:26:48 -04:00
Andrew F. Davis
03750231a8 arm: mach-omap2: Factor out common FDT fixup suport
Some of the fixups currently done for OMAP5 class boards are common to
other OMAP family devices, move these to fdt-common.c.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-07-22 22:22:43 -04:00
Stefano Babic
552a848e4f imx: reorganize IMX code as other SOCs
Change is consistent with other SOCs and it is in preparation
for adding SOMs. SOC's related files are moved from cpu/ to
mach-imx/<SOC>.

This change is also coherent with the structure in kernel.

Signed-off-by: Stefano Babic <sbabic@denx.de>

CC: Fabio Estevam <fabio.estevam@nxp.com>
CC: Akshay Bhat <akshaybhat@timesys.com>
CC: Ken Lin <Ken.Lin@advantech.com.tw>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Heiko Schocher <hs@denx.de>
CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com>
CC: Christian Gmeiner <christian.gmeiner@gmail.com>
CC: Stefan Roese <sr@denx.de>
CC: Patrick Bruenn <p.bruenn@beckhoff.com>
CC: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Nikita Kiryanov <nikita@compulab.co.il>
CC: Otavio Salvador <otavio@ossystems.com.br>
CC: "Eric Bénard" <eric@eukrea.com>
CC: Jagan Teki <jagan@amarulasolutions.com>
CC: Ye Li <ye.li@nxp.com>
CC: Peng Fan <peng.fan@nxp.com>
CC: Adrian Alonso <adrian.alonso@nxp.com>
CC: Alison Wang <b18965@freescale.com>
CC: Tim Harvey <tharvey@gateworks.com>
CC: Martin Donnelly <martin.donnelly@ge.com>
CC: Marcin Niestroj <m.niestroj@grinn-global.com>
CC: Lukasz Majewski <lukma@denx.de>
CC: Adam Ford <aford173@gmail.com>
CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr>
CC: Boris Brezillon <boris.brezillon@free-electrons.com>
CC: Soeren Moch <smoch@web.de>
CC: Richard Hu <richard.hu@technexion.com>
CC: Wig Cheng <wig.cheng@technexion.com>
CC: Vanessa Maegima <vanessa.maegima@nxp.com>
CC: Max Krummenacher <max.krummenacher@toradex.com>
CC: Stefan Agner <stefan.agner@toradex.com>
CC: Markus Niebel <Markus.Niebel@tq-group.com>
CC: Breno Lima <breno.lima@nxp.com>
CC: Francesco Montefoschi <francesco.montefoschi@udoo.org>
CC: Jaehoon Chung <jh80.chung@samsung.com>
CC: Scott Wood <oss@buserror.net>
CC: Joe Hershberger <joe.hershberger@ni.com>
CC: Anatolij Gustschin <agust@denx.de>
CC: Simon Glass <sjg@chromium.org>
CC: "Andrew F. Davis" <afd@ti.com>
CC: "Łukasz Majewski" <l.majewski@samsung.com>
CC: Patrice Chotard <patrice.chotard@st.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Hans de Goede <hdegoede@redhat.com>
CC: Masahiro Yamada <yamada.masahiro@socionext.com>
CC: Stephen Warren <swarren@nvidia.com>
CC: Andre Przywara <andre.przywara@arm.com>
CC: "Álvaro Fernández Rojas" <noltari@gmail.com>
CC: York Sun <york.sun@nxp.com>
CC: Xiaoliang Yang <xiaoliang.yang@nxp.com>
CC: Chen-Yu Tsai <wens@csie.org>
CC: George McCollister <george.mccollister@gmail.com>
CC: Sven Ebenfeld <sven.ebenfeld@gmail.com>
CC: Filip Brozovic <fbrozovic@gmail.com>
CC: Petr Kulhavy <brain@jikos.cz>
CC: Eric Nelson <eric@nelint.com>
CC: Bai Ping <ping.bai@nxp.com>
CC: Anson Huang <Anson.Huang@nxp.com>
CC: Sanchayan Maity <maitysanchayan@gmail.com>
CC: Lokesh Vutla <lokeshvutla@ti.com>
CC: Patrick Delaunay <patrick.delaunay@st.com>
CC: Gary Bisson <gary.bisson@boundarydevices.com>
CC: Alexander Graf <agraf@suse.de>
CC: u-boot@lists.denx.de
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-07-12 10:17:44 +02:00
Tom Rini
8d3a25685e Merge git://git.denx.de/u-boot-dm 2017-07-11 20:28:46 -04:00
Tom Rini
d43ef73bf2 Merge branch 'master' of git://git.denx.de/u-boot-rockchip 2017-07-11 14:21:50 -04:00
Simon Glass
fedb428c5b Convert CONFIG_SCSI to Kconfig
This converts the following to Kconfig:
   CONFIG_SCSI

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Sjoerd Simons
2454b719fb rockchip: rk3288: Add pinctrl support for the gmac ethernet interface
Add support for the gmac ethernet interface to pinctrl. This hardcodes
the setup to match that of the firefly and Radxa Rock2 boards, using the
RGMII phy mode for gmac interface and GPIO4B0 as the phy reset GPIO.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 15:23:38 +02:00
eric.gao@rock-chips.com
e3ef41df48 rockchip: pwm: fix the register layout for the PWM controller
According to rk3288 spec, the pwm register order is:
    PWM_PWM0_CNT,
    PWM_PWM0_PERIOD_HPR,
    PWM_PWM0_DUTY_LPR,
    PWM_PWM0_CTRL
but the source code's order is:
  struct rk3288_pwm {
    u32 cnt;
    u32 duty_lpr;
    u32 period_hpr;
    u32 ctrl;
  };

So, correct it here. It is the same as RK3399.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Edited the commit message:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:47 +02:00
Kever Yang
168eef7ada rockchip: rk322x: add basic soc support
Enable soc support for SPL and U-boot skeleton.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:46 +02:00
Kever Yang
5cc9d31a79 rockchip: rk322x: add pinctrl driver
Add init pinctrl driver support for:
- i2c;
- spi;
- uart;
- pwm;
- emmc/sdmmc;

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:46 +02:00
Kever Yang
045029cbd1 rockchip: rk322x: add clock driver
Add clock driver init support for:
- cpu, bus clock init;
- emmc, sdmmc clock;
- ddr clock;

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Fixed format specified (%x -> %p) in clk_rk322x.c:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:45 +02:00
Kever Yang
cc89369fb0 rockchip: rk3368: add sdram driver for U-Boot
Add sdram driver in U-Boot for get the correct sdram size from
sys_reg, so that U-Boot can co-work with Rockchip loader or SPL
to get different dram capability and then tell the kernel.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:45 +02:00
Kever Yang
7805cdf494 rockchip: use common sdram function
Replace the sdram_init() in board init and rockchip_sdram_size() in
sdram driver for all the Rockchip SoCs which enable CONFIG_RAM.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Make dram_init() in rk3036-board.c conditional on CONFIG_RAM:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:44 +02:00
Kever Yang
6d1970fa8a rockchip: add sdram_common for common functions
There are some functions like sdram_size_mb can be re-used for
different rockchip SoCs, just put them into common file.
Add board_get_usable_ram_top() for ram_top init base on
SDRAM_MAX_SIZE.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Added SDRAM_MAX_SIZE definition for RK3036:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

fixup: 3036 fix for sdram_common
2017-07-11 12:13:44 +02:00
Jorge Ramirez-Ortiz
d754254f20 ARM64: poplar: hi3798cv200: u-boot support for Poplar 96Boards
This port adds support for:
        1) Serial
        2) eMMC
        3) USB

It has been tested with ARM TRUSTED FIRMWARE running u-boot as the
BL33 executable [see board's README]

eMMC has been tested for reading and booting the loader and linux
kernels as well as saving the u-boot environment.

USB has been tested with ASIX networking adapter and SanDisk 7.4GB
drive.

PSCI has been tested via the reset call (PSCI executes from DDR)

The firwmare upgrade process has been tested via TFTP and USB FAT
filesystem containing the fastboot.bin image in one of the partitions.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2017-07-10 14:26:03 -04:00
Tom Rini
de8203653f ti816x: Enable ethernet support
The ti816x SoC revision of the ethernet IP block is handled by the
"davinci_emac" driver, rather than the "cpsw" driver as done by later
members of the family.  Enable the relevant plumbing.

Signed-off-by: Sriramakrishnan <srk@ti.com>
Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-28 11:43:39 -04:00
Tom Rini
821560fd8e Merge git://www.denx.de/git/u-boot-imx
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	include/configs/imx6qdl_icore_rqs.h
	include/configs/imx6ul_geam.h
	include/configs/imx6ul_isiot.h
2017-06-27 09:32:37 -04:00
Tom Rini
784667d7f9 Xilinx changes for v2017.07
ZynqMP:
 - config cleanup
 - SD LS mode support
 - psu_init* cleanup
 - unmap OCM
 - Support for SMC
 
 Zynq:
 - add ddrc to Kconfig
 - add topic-miamilite board support
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iEYEABECAAYFAllJNGcACgkQykllyylKDCEBrACdE1X8RroAQZQ3cN3yEXp/OQ3V
 D+gAn1PAUvy3zT8UDiJcF1rCxptvlKlv
 =4ans
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2017.07' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2017.07

ZynqMP:
- config cleanup
- SD LS mode support
- psu_init* cleanup
- unmap OCM
- Support for SMC

Zynq:
- add ddrc to Kconfig
- add topic-miamilite board support
2017-06-21 07:57:37 -04:00
Michal Simek
fb4000e871 arm64: zynqmp: Check pmufw version
If PMUFW version is not v0.3 then panic.
ZynqMP switch to CCF based clock driver which requires
PMUFW to be present at certain version.
This patch ensure that you use correct and tested PMUFW
binary.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-06-20 16:42:13 +02:00
Siva Durga Prasad Paladugu
e0752bc184 arm64: zynqmp: Define routines for mmio write and read
Define routines of mmio write and read functionalities
for zynqmp platform.

Also do not call SMC from SPL because SPL is running before ATF in EL3
that's why SMCs can't be called because there is nothing to call.
zynqmp_mmio*() are doing direct read/write accesses and this patch does
the same. PMUFW is up and running at this time and there is a way to talk
to pmufw via IPI but there is no reason to implement IPI stuff in SPL if
we need just simple read for getting clock driver to work.

Also make invoke_smc as global so that it can be reused in
multile places where ever possible.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-06-20 16:42:06 +02:00
Tom Rini
ebba9d1daf Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2017-06-19 08:08:40 -04:00
Semen Protsenko
fa24eca1f2 omap: Add routine for setting fastboot variables
This patch reuses new option, which allows us to expose variables
from environment to "fastboot getvar" command. Those variables must be
of "fastboot.%s" format.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2017-06-12 08:36:21 -04:00
Tom Rini
8cb3ce64f9 Merge git://git.denx.de/u-boot-dm 2017-06-10 18:01:22 -04:00
Tom Rini
d2e1ee686a Merge branch 'master' of git://git.denx.de/u-boot-video 2017-06-10 09:48:09 -04:00