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clk: stm32f7: remove clock_get()

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All drivers which was using clock_get() are now using
clk_get_rate() from clock framework, now it's safe to
remove clock_get().

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
This commit is contained in:
Patrice Chotard 2017-07-18 09:29:10 +02:00 committed by Tom Rini
parent 541cd6e54e
commit 81d0128d2b
2 changed files with 0 additions and 54 deletions
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6
arch/arm/include/asm/arch-stm32f7/stm32.h
View file

@ -57,11 +57,6 @@ static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
[5 ... 7] = 256 * 1024
};
enum clock {
CLOCK_AHB,
CLOCK_APB1,
CLOCK_APB2
};
#define STM32_BUS_MASK GENMASK(31, 16)
struct stm32_rcc_regs {
@ -108,7 +103,6 @@ struct stm32_pwr_regs {
};
#define STM32_PWR ((struct stm32_pwr_regs *)PWR_BASE)
unsigned long clock_get(enum clock clck);
void stm32_flash_latency_cfg(int latency);
#endif /* _ASM_ARCH_HARDWARE_H */

48
drivers/clk/clk_stm32f7.c
View file

@ -171,54 +171,6 @@ static int configure_clocks(struct udevice *dev)
return 0;
}
unsigned long clock_get(enum clock clck)
{
u32 sysclk = 0;
u32 shift = 0;
/* Prescaler table lookups for clock computation */
u8 ahb_psc_table[16] = {
0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
};
u8 apb_psc_table[8] = {
0, 0, 0, 0, 1, 2, 3, 4
};
if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
RCC_CFGR_SWS_PLL) {
u16 pllm, plln, pllp;
pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
>> RCC_PLLCFGR_PLLN_SHIFT);
pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
}
switch (clck) {
case CLOCK_AHB:
shift = ahb_psc_table[(
(readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
>> RCC_CFGR_HPRE_SHIFT)];
return sysclk >>= shift;
break;
case CLOCK_APB1:
shift = apb_psc_table[(
(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
>> RCC_CFGR_PPRE1_SHIFT)];
return sysclk >>= shift;
break;
case CLOCK_APB2:
shift = apb_psc_table[(
(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
>> RCC_CFGR_PPRE2_SHIFT)];
return sysclk >>= shift;
break;
default:
return 0;
break;
}
}
static unsigned long stm32_clk_get_rate(struct clk *clk)
{
struct stm32_clk *priv = dev_get_priv(clk->dev);