Commit graph

18051 commits

Author SHA1 Message Date
Alper Nebi Yasak
127c8d85cf video: rockchip: Add missing dpcd_write() call to link_train_ce()
Found this by comparing it to the coreboot driver, a form of this call
was introduced there in their commit b9a7877568cf ("rockchip/*: refactor
edp driver"). This is copy-pasted from U-Boot's link_train_cr() slightly
above it.

Without this on a gru-kevin chromebook, I have:

    clock recovery at voltage 0 pre-emphasis 0
    requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB
    using signal parameters: voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB
    using signal parameters: voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB
    using signal parameters: voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB
    using signal parameters: voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB
    using signal parameters: voltage 0.4V pre_emph 3.5dB
    channel eq failed, ret=-5
    link train failed!
    rk_vop_probe() Device failed: ret=-5

With this, it looks like training succeeds:

    clock recovery at voltage 0 pre-emphasis 0
    requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB
    using signal parameters: voltage 0.4V pre_emph 3.5dB
    requested signal parameters: lane 0 voltage 0.4V pre_emph 6dB
    requested signal parameters: lane 1 voltage 0.4V pre_emph 6dB
    requested signal parameters: lane 2 voltage 0.4V pre_emph 6dB
    requested signal parameters: lane 3 voltage 0.4V pre_emph 6dB
    using signal parameters: voltage 0.4V pre_emph 6dB
    requested signal parameters: lane 0 voltage 0.4V pre_emph 0dB
    requested signal parameters: lane 1 voltage 0.4V pre_emph 0dB
    requested signal parameters: lane 2 voltage 0.4V pre_emph 0dB
    requested signal parameters: lane 3 voltage 0.4V pre_emph 0dB
    using signal parameters: voltage 0.4V pre_emph 0dB
    channel eq at voltage 0 pre-emphasis 0
    config video failed
    rk_vop_probe() Device failed: ret=-110

The "config video failed" error also goes away when I disable higher
log levels, and it claims to have successfully probed the device.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 18:20:03 +08:00
Heiko Stuebner
2db36c64bd ram: rockchip: px30: add a config-based ddr selection
The SRAM on the PX30 is not big enough to hold multiple DDR configs
so it needs to be selected during build.

So far simply the DDR3 config was always selected and getting DDR4
or LPDDR2/3 initialized would require a code modification.

So add Kconfig options similar to RK3399 to allow selecting the DDR4
and LPDDR2/3 options instead, while DDR3 stays the default as before.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 18:11:29 +08:00
Jack Mitchell
da0be4e176 clk: rockchip: rk3399: implement getting wdt/alive clocks
In order to correctly calculate the designware watchdog
timeouts, the watchdog clock is required. Implement required
clocks to facilitate this.

Signed-off-by: Jack Mitchell <ml@embed.me.uk>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-10-30 18:05:45 +08:00
Tom Rini
a58d86db46 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-cfi-flash
- Fix devicetree address determination seen on QEMU ARM64
- Use DMA for reads is available
2020-10-08 10:20:53 -04:00
Andre Przywara
492b9917c6 cfi_flash: Fix devicetree address determination
The cfi-flash driver uses an open-coded version of the generic
algorithm to decode and translate multiple frames of a "reg" property.

This starts off the wrong foot by using the address-cells and size-cells
properties of *this* very node, and not of the parent. This somewhat
happened to work back when we were using a wrong default size of 2,
but broke about a year ago with commit 0ba41ce1b7 ("libfdt: return
correct value if #size-cells property is not present").

Instead of fixing the reinvented wheel, just use the generic function
that does all of this properly.

This fixes U-Boot on QEMU (-arm64), which was crashing due to decoding
a wrong flash base address:
DRAM:  1 GiB
Flash: "Synchronous Abort" handler, esr 0x96000044
elr: 00000000000211dc lr : 00000000000211b0 (reloc)
elr: 000000007ff5e1dc lr : 000000007ff5e1b0
x0 : 00000000000000f0 x1 : 000000007ff5e1d8
x2 : 000000007edfbc48 x3 : 0000000000000000
x4 : 0000000000000000 x5 : 00000000000000f0
x6 : 000000007edfbc2c x7 : 0000000000000000
x8 : 000000007ffd8d70 x9 : 000000000000000c
x10: 0400000000000003 x11: 0000000000000055
     ^^^^^^^^^^^^^^^^

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-08 09:04:41 +02:00
Vignesh Raghavendra
3f891a103c mtd: cfi_mtd: Use DMA for reads
When possible use DMA for reading from CFI flash, this provides upto 5x
improvement in read performance with high speed CFI compliant flashes
like HyperFlash.

Code will gracefully fallback to CPU copy when DMA is unavailable.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-08 09:04:41 +02:00
Vignesh Raghavendra
8995a86cd6 dma: Reduce error level when DMA channel type does not exist
Caller would need gracefully handle failures of dma_get_device(),
therefore reduce pr_err() to pr_debug() when DMA device is not found.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-08 09:04:41 +02:00
Tom Rini
1c431f118c - mips: octeon: add support for DDR4 memory controller
- mips: octeon: add support for DWC3 USB
 - mips: octeon: add support for booting Linux
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiQkHUH+J02LLC9InKPlOlyTyXBgFAl9+Ie4ACgkQKPlOlyTy
 XBg5lw//TEk6avR1/G4/SKe2Mj2hDQGm2OKjx5BLG6LC/m+It8lk5hFGCKeRTS3m
 zlQ1z4Rki05Q/HW8fZfUSNZTGwbp1n5WJWMx5PRB2T4zYYeoktxQo6dRLbmR9mxL
 2tiZ3QV3qzJafcwy1xdddr2GRGpRyu/sPHnEf5iHtijfT+6MPqSY5E1An+mAGhGb
 IOjzh/OtmO+4Hu9zlp4G5AhNoQBBRRZg+2Sm+kVrzLyM345byucNpnnFiCT1T54M
 iB3KsijBBvcnZ/bR7WMB+x942uFQi9hWdK0ngQhhOO4W1/Mf2ILst44gcxiJQNaf
 dNIEdQxOeL1JDurQL/GSo4cQIr2mXlt3FtTB8RH8sAf9+aMJjlVqYaX3PGUFQJ5B
 z5hnzKWk+jnxwD2F8fAtjqawQY6cBAaF/BDkxFdZcvhIIp9veUNDnk98YYwL7ZjU
 8zRZQSmwI9zmC0kC9C6mmIN+eAbUhT+XDIlVk/USreujDkq9ESWIvo4SdY0+uXjJ
 EJ1Xhqx/H7Qzem+SdbonJjMIWa/5rBnqT/nvCwSGDx64OdvD+F93RHFeyJvp8p1J
 DWNNRZ4rAlrz3z8hDSuIt0M5ENoGWlHjD3nb11CBK/XnobBLhT+8W/b/ffjGcRnn
 dowofymjvGMnhUUkHIb5heyMZaRCZVquGlEOIjrOdc4GNm6EW5Y=
 =v+p3
 -----END PGP SIGNATURE-----

Merge tag 'mips-pull-2020-10-07' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips

- mips: octeon: add support for DDR4 memory controller
- mips: octeon: add support for DWC3 USB
- mips: octeon: add support for booting Linux
2020-10-07 17:25:25 -04:00
Stefan Roese
92ca2fee08 usb: xhci: octeon: Add DWC3 glue layer for Octeon
This patch adds the glue layer for the MIPS Octeon SoCs. It's ported
mainly from the Linux code.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
2020-10-07 20:25:57 +02:00
Stefan Roese
e68efa1ecf usb: xhci: xhci_bulk_tx: Don't "BUG" when comparing addresses
Octeon uses mapped addresses for virtual and physical memory. It's not
that easy to calculate the resulting addresses here. So let's remove
this BUG_ON() completely, as it's not really helpful.

Please also note, that BUG_ON() is not recommended any more in the Linux
kernel.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
2020-10-07 20:25:57 +02:00
Stefan Roese
72a53ac59b usb: xhci: xhci-dwc3.c: Use dev_remap_addr() instead of dev_get_addr()
On MIPS platforms, mapping of the base address is needed. This patch
switches from dev_get_addr() to dev_remap_addr() to get the mapped base
address of the xHCI controller.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
2020-10-07 20:25:57 +02:00
Aaron Williams
15afe725f3 ram: octeon: Add MIPS Octeon3 DDR4 support (part 3/3)
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.

Part 3 includes the DIMM SPD handling code and the Kconfig / Makefile
integration.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:57 +02:00
Aaron Williams
61674a17bc ram: octeon: Add MIPS Octeon3 DDR4 support (part 2/3)
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.

Part 2 includes the very complex Octeon 3 DDR4 configuration

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:57 +02:00
Aaron Williams
e13bb86588 ram: octeon: Add MIPS Octeon3 DDR4 support (part 1/3)
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.

Part 1 adds the base U-Boot RAM driver, which will be instantiated by
the DT based probing.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:57 +02:00
Tom Rini
42378e3cd2 bloblist enhancement for alignment
Update ofnode/dev_read phandle function
 sandbox keyboard enhancements and fixes
 -----BEGIN PGP SIGNATURE-----
 
 iQHFBAABCAAvFiEE1//at7WoVCu4umzW8Cm2NFgI+6QFAl98qrQRHHNqZ0BjaHJv
 bWl1bS5vcmcACgkQ8Cm2NFgI+6Tm5QwAnofBrQ5Y2lwJCUnaratH/J0p5aDXMu37
 SMshRdY4cQPNT1nBFf0fA8UYwTScUla48tPfMO/IxnoMwizxNRZQOH56vcm6w6ie
 73uWlOAl7paw0UGpLYnkuwGC3CoCT7wynTMy0Ap4994alq2pcTK75ra9ODLPn/Sh
 Qg4R4I1VoWbTJT4ZFYcjdMg1+B2hDPd+gVLjjGmOwazncG7aMmpYKJOcscZCuqv8
 Utg30XUxWMxclVPuzXAfREjx+Hhy0AG44ZYv3T44JaOtIAHU4Va/rzqrJRe+pR9V
 YwgjCQhAOuGRswqNJDeg5K8o64jW3vAVULG1HrOZ3gu19ZCmseAH4bNHgiy2SBMz
 CtVtapU+uXjktME2G0vX86Ip8kpxi07p1WeP83TmDFqiGnfEZxn5WH7bYc4l7KSf
 mfWhmrrY5K2ogN5iN8ahc7fGBdHziD+h/Blwn03LgTFHF8f6jxVNJlvjYiya97HN
 1LPk4NNYgPQI3mObL5szQ8FKJ69zSCFk
 =ZqpG
 -----END PGP SIGNATURE-----

Merge tag 'dm-pull-6oct20' of git://git.denx.de/u-boot-dm

bloblist enhancement for alignment
Update ofnode/dev_read phandle function
sandbox keyboard enhancements and fixes
2020-10-06 13:59:01 -04:00
Patrick Delaunay
89f68302ca dm: add cells_count parameter in *_count_phandle_with_args
The cell_count argument is required when cells_name is NULL.

This patch adds this parameter in live tree API
- of_count_phandle_with_args
- ofnode_count_phandle_with_args
- dev_count_phandle_with_args

This parameter solves issue when these API is used to count
the number of element of a cell without cell name. This parameter
allow to force the size cell.

For example:
  count = dev_count_phandle_with_args(dev, "array", NULL, 3);

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-06 09:07:54 -06:00
Tom Rini
987ab49366 - generate unique mac address from SoC serial on S400 board
- Add USB support for GXL and AXG SoCs
 - Update Gadget code to use the new GXL and AXG USB glue driver
 - Add a VIM3 board support to add dynamic PCIe enable in OS DT
 - Fix AXG pinmux with requesting GPIOs
 - Add missing GPIOA_18 for AXG pinctrl
 - Add Amlogic PWM driver
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAl97ReAACgkQd9zb2sjI
 SdHHVA/9HuEAzwuJyJoyQcXARIqMwoi6w4qntlmb+VTnxxlKCzLL1Ir68W2+5Y5S
 l+sVkxYDwTmYRs40FOnMdFM1r1Q7IqWwTemqQAcfmGLV+/+MwoDiludGat7JAp1i
 mo/FBcBMLrf3dIJnhCyl2Rezgu06GLCQMAJOlusTDaruUZUHBxPVpAhfRvtlYq1Q
 bCINZfgMcmv8EfReIOE6xGt0+9TKILqQamMByc2ZWdz5UBioqUdQ82arW1rdV/ze
 ATU7vrxNmNlUQnRsMBOry9chbeuNrAhD8sqVloGPUikhf93y0BG7eINmCYrLoXjN
 mopApyWzo3+50GI6It+P9vX6mWVJhd8gAJsvTkRn8ok3flGlRQPmFmAfkjngN/GH
 wdkZpKi/u/ndm2Id7ekZff/Fm/ZmL/kskrRWaWrnuxHNiSNiJvAl+PU7MzCGrgED
 E0MduY1hFpa7wc47xFtI0WKlcdNVQCTRwuZYVIZYlnhXeVupJyQ0dx1ggonlvvIZ
 3cgS2qzd8z2RxKzhnRDvjSfwy7gWFjqpljocyRP4osoWJybJu88MIUFK2GlPdc7x
 3UD/+R88FsIVsQuxzbwBuFZnP+Zo1JqCmspyX4sCeUBDNK4+MqOqIxBZry+q4qso
 usWrTofg2hfxS3FgUL0pQW5GF8JGm4uXcIjbe7fMi47GJ6Lp/ec=
 =rbAX
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-amlogic-20201005' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- generate unique mac address from SoC serial on S400 board
- Add USB support for GXL and AXG SoCs
- Update Gadget code to use the new GXL and AXG USB glue driver
- Add a VIM3 board support to add dynamic PCIe enable in OS DT
- Fix AXG pinmux with requesting GPIOs
- Add missing GPIOA_18 for AXG pinctrl
- Add Amlogic PWM driver
2020-10-06 08:36:10 -04:00
Tom Rini
b7e7831e5d Merge branch 'next'
Bring in the assorted changes that have been staged in the 'next' branch
prior to release.

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-05 14:10:59 -04:00
Neil Armstrong
2d481b2e3e pwm: Add driver for Amlogic Meson PWM controller
This adds the driver for the PWM controller found in the Amlogic SoCs.

This PWM is only a set of Gates, Dividers and Counters:
PWM output is achieved by calculating a clock that permits calculating
two periods (low and high). The counter then has to be set to switch after
N cycles for the first half period.
The hardware has no "polarity" setting. This driver reverses the period
cycles (the low length is inverted with the high length) for
PWM_POLARITY_INVERSED.

Disabling the PWM stops the output immediately (without waiting for the
current period to complete first).

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05 18:02:16 +02:00
Neil Armstrong
38c1c6f816 pinctrl: meson-axg: add missing GPIOA_18
Add the missing GPIOA_18 from the missing EE gpio list.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05 18:01:40 +02:00
Neil Armstrong
0f6bef4a95 pinctrl: meson-axg-pmx: fix gpio request
The AXG pmx driver gpio request offset needs the pin base to have the
correct pin number.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
2020-10-05 18:01:39 +02:00
Neil Armstrong
0ae8724d7e phy: meson-gxl-usb: depend on Meson AXG aswell
Enable build of meson-gxl-usb PHY for the AXG architecture aswell.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05 17:59:45 +02:00
Neil Armstrong
66d9427403 phy: meson-gxl: remove invalid USB3 PHY driver
The registers which are managed by the meson-gxl-usb3 PHY driver are
actually "USB control" registers (which are "glue" registers which
manage OTG detection and routing of the OTG capable port between the
DWC2 peripheral-only controller and the DWC3 host-only controller).

Drop the meson-gxl-usb3 PHY driver now that the dwc3-meson-gxl-usb
driver supports the USB control registers on GXL and GXM SoCs (these
were previously managed by the meson-gxl-usb3 PHY driver).

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05 17:59:45 +02:00
Neil Armstrong
46eddbc58f usb: dwc3: add Amlogic GXL & GXL DWC3 Glue
The USB support was initialy done with a set of PHYs and dwc3-of-simple
because the architecture of the USB complex was not understood correctly
at the time (and proper documentation was missing...).

But with the G12A family, the USB complex was correctly understood and
implemented correctly.

This adds a proper driver for the glue, based on the G12A one, but with
enough changes to require a different driver in U-Boot.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05 17:59:45 +02:00
Tom Rini
caebff09ef First set of u-boot-atmel features for 2021.01 cycle
-----BEGIN PGP SIGNATURE-----
 
 iQFQBAABCgA6FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAl960JkcHGV1Z2VuLmhy
 aXN0ZXZAbWljcm9jaGlwLmNvbQAKCRAesx4CDqwvyDaWCACYjvloDzXQaYaauWwR
 whFwgkUAQ8yjadj/12We/X2b7HGisNFNE80e/V4MU8RrJDFZmohZdLWMfRKez29X
 d+BG+OzVXxHWozny7ZQ2g1yYJbgCI7sVUeemQjUBZJ6aKPneQlVfwyfT2l88wOVK
 yQMqS+ZyVogihR9/NHCOlJHog+6OOoBmc16w1tymM6QcO8ZsYeA66ed8SLnjDb3N
 Rg2Ll2RR/lHuD/Fpxt1aUhybXFKSIOr4Qopo5X0hw5B3ibkp6JXGRE2wIwQYw6CA
 q+sKTg37CSzylipkQ5EOGdLcXD7r3KIGkSbUMb8wvt6dROarnIuQ+zJeF3sr+l2H
 hSoU
 =vHqZ
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-atmel-2021.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel into next

First set of u-boot-atmel features for 2021.01 cycle:

This feature set includes a new CPU driver for at91 family, new driver
for PIT64B hardware timer, support for new at91 family SoC named sama7g5
which adds: clock support, including conversion of the clock tree to
CCF; SoC support in mach-at91, pinctrl and mmc drivers update.  The
feature set also includes updates for mmc driver and some other minor
fixes and features regarding building without the old Atmel PIT and the
possibility to read a secondary MAC address from a second i2c EEPROM.
2020-10-05 10:54:27 -04:00
Tom Rini
17e76b33cc - stm32mp: DT alignment with Linux 5.9-rc4
- stm32mp: convert drivers to APIs which support live DT
 - stm32mp: gpio: minor fixes
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCgAdFiEE56Yx6b9SnloYCWtD4rK92eCqk3UFAl93OLYACgkQ4rK92eCq
 k3VQ3ggAlv+e3IXylevdLrCGtoPNb0mC3pB7fKcXedZ7YOHi+ag6MfLKFb3K8UCV
 1h8iUX3XpGxOuOzOlqu89UFZBZXkbKP3bPnOJD8AliTEcZN/rTdZK43qYbAVM3tL
 UvOtCXMzujmGwJsJqLQmXKK761fpcJFzEisajX+d6cz+at3oMF2Yoa/1RcC8Z7fi
 DHWaUME132H5A9pzmt84N83neJNgMmFIDyHBWjNSMkvdiE5jz8MAPFrua8FDyymS
 w0QmKmN0ub+5kJqXu4X/LCMZUjYozC3lfNbnwRIkXXKJtQuGEea963bBi7Gastdb
 gSCQKmrwjtxa4/g/bpalDTMAvirKnQ==
 =Q/62
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-stm32-20201003' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm into next

- stm32mp: DT alignment with Linux 5.9-rc4
- stm32mp: convert drivers to APIs which support live DT
- stm32mp: gpio: minor fixes
2020-10-05 10:54:10 -04:00
Claudiu Beznea
01c35f269f cpu: at91: add driver for CPU
Add basic CPU driver use to retrieve information about CPU itself.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-05 10:45:16 +03:00
Ovidiu Panait
0db912de15 pinctrl: bcm283x: Store the return value of dev_read_u32_default to int
Currently, the return value of dev_read_u32_default is stored in an u32,
causing the subsequent "if (function < 0)" to always be false:

u32 function;
...
function = dev_read_u32_default(config, "brcm,function", -1);
if (function < 0) {
        debug("Failed reading function for pinconfig %s (%d)\n",
                      config->name, function);
        return -EINVAL;
}

Make "function" variable an int to fix this.

Cc: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-10-02 17:32:28 +02:00
Ovidiu Panait
e020c07a02 pinctrl: bcm283x: Read address from DT in ofdata_to_platdata
Factor out reading IP base address to ofdata_to_platdata function, which
is designed for this purpose. Also, drop the dev->priv NULL check, since
this is already done by the dm core when allocating space using
priv_auto_alloc_size feature. (in drivers/core/device.c ->
device_ofdata_to_platdata).

Cc: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-10-02 17:32:28 +02:00
Ovidiu Panait
bab9be9e0d pinctrl: bcm283x: DM_FLAG_PRE_RELOC: Remove OF_CONTROL check
Remove CONFIG_IS_ENABLED(OF_CONTROL) check from DM_FLAG_PRE_RELOC, since
this driver only supports OF_CONTROL.

drivers/pinctrl/broadcom/Kconfig:
config PINCTRL_BCM283X
    depends on ARCH_BCM283X && PINCTRL_FULL && OF_CONTROL

Cc: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-10-02 17:32:28 +02:00
Patrick Delaunay
04e29ca5bb mailbox: stm32_ipcc: Convert to use APIs which support live DT
Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
driver can support live DT.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-02 15:05:14 +02:00
Patrick Delaunay
a04616be1b video: stm32_dsi: Convert to use APIs which support live DT
Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
driver can support live DT.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Yannick Fertré <yannick.fertre@st.com>
2020-10-02 15:05:14 +02:00
Patrick Delaunay
28c6ba861c video: stm32_ltdc: Convert to use APIs which support live DT
Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
driver can support live DT.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Yannick Fertré <yannick.fertre@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-02 15:05:14 +02:00
Patrick Delaunay
10bccd0dd3 pinctrl: stm32: Add header with SPDX licence
Cosmetics: Add header with SPDX licence

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-02 15:05:14 +02:00
Patrick Delaunay
d3bfad266c pinctrl: stm32: Convert to use APIs which support live DT
Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
driver can support live DT.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-02 15:05:14 +02:00
Patrick Delaunay
cb08e84d68 gpio: stm32: check result of ofnode_phandle_args
Add test on the size of ofnode_phandle_args result to avoid access
to uninitialized elements in args[] field.

This patch avoids the issue when gpio-ranges cell size is not 3 as
expected, for example:
	gpio-ranges = <&pinctrl 0>;
instead of
	gpio-ranges = <&pinctrl 0 112 16>;

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-02 15:05:14 +02:00
Patrick Delaunay
15c8cbfc74 gpio: stm32: cosmetic: cleanup gpio_stm32_probe
Move the variables definition at the beggining of the function
gpio_stm32_probe().

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-02 15:05:14 +02:00
Tom Rini
7e373a1a6a Merge branch 'next' of git://git.denx.de/u-boot-usb into next
- Assorted XHCI improvements
2020-10-01 14:52:56 -04:00
Tom Rini
f352c51f57 Revert "net: smc911x: Automatically Update ethaddr with MAC"
Upon further discussion on the mailing list, we should not get in the
situation where the generic code path to set ethaddr/etc correctly does
not work.  Revert this until someone can further debug the smc911x
driver regarding this issue.

This reverts commit 387cbf096e.

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-01 14:51:58 -04:00
Lad Prabhakar
e15e817f3e usb: xhci-rcar: Add support for R8A774A1 SoC
The R8A774A1 is compatible with the generic rcar-gen3-xhci controller.
This patch adds the compatibility flag, to support the xHCI controller.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-01 19:43:05 +02:00
Chunfeng Yun
a6837a0370 usb: xhci: convert to readx_poll_sleep_timeout()
Use readx_poll_sleep_timeout() to poll the register status

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-01 19:43:05 +02:00
Chunfeng Yun
23a54ccfb6 usb: xhci: use macros with parameter to fill ep_info2
Use macros with parameter to fill ep_info2, then some macros
for MASK and SHIFT can be removed

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-01 19:43:05 +02:00
Chunfeng Yun
bf58cf9ab1 usb: xhci: convert to TRB_TX_TYPE()
Use TRB_TX_TYPE() instead of (TRB_DATA_OUT/IN << TRB_TX_TYPE_SHIFT)

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-01 19:43:05 +02:00
Chunfeng Yun
4312638eaf usb: xhci: convert to TRB_LEN() and TRB_INTR_TARGET()
For normal TRB fields:
use TRB_LEN(x) instead of ((x) & TRB_LEN_MASK);
and use TRB_INTR_TARGET(x) instead of
(((x) & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT)

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-01 19:43:05 +02:00
Chunfeng Yun
a826d76f2b usb: xhci: convert to TRB_TYPE()
Use TRB_TYPE(p) instead of ((p) << TRB_TYPE_SHIFT)

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-01 19:43:05 +02:00
Chunfeng Yun
86d1fa17fb usb: xhci: convert to HCS_MAX_PORTS()
Use HCS_MAX_PORTS(p) instead of
((p & HCS_MAX_PORTS_MASK) >> HCS_MAX_PORTS_SHIFT)

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-01 19:43:05 +02:00
Chunfeng Yun
740820519c usb: xhci: add quirks flag to support MediaTek xHCI 0.96
There some vendor quirks for MTK xHCI 0.96 host controller:
1. It defines some extra SW scheduling parameters for HW
   to minimize the scheduling effort for synchronous and
   interrupt endpoints. The parameters are put into reserved
   DWs of slot context and endpoint context.
2. Its TDS in  Normal TRB defines a number of packets that
   remains to be transferred for a TD after processing all
   Max packets in all previous TRBs.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-01 19:43:05 +02:00
Chunfeng Yun
e3ea481bee usb: xhci: create one unified function to calculate TRB TD remainder
xhci versions 1.0 and later report the untransferred data remaining in a
TD a bit differently than older hosts.

We used to have separate functions for these, and needed to check host
version before calling the right function.

Now Mediatek host has an additional quirk on how it uses the TD Size
field for remaining data. To prevent yet another function for calculating
remainder we instead want to make one quirk friendly unified function.

Porting from the Linux:
c840d6ce772d("xhci: create one unified function to calculate TRB TD remainder.")
124c39371114("xhci: use boolean to indicate last trb in td remainder calculation")

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-01 19:43:05 +02:00
Chunfeng Yun
719d7d8df4 usb: xhci: add a member hci_version in xhci_ctrl struct
Add a member to save xHCI version, it's used some times.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-01 19:43:05 +02:00
Tom Rini
b084d8596d Merge branch 'next' of git://git.denx.de/u-boot-sh into next 2020-10-01 10:29:39 -04:00