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Merge branch 'next' of git://git.denx.de/u-boot-sh into next

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This commit is contained in:
Tom Rini 2020-10-01 10:29:39 -04:00
commit b084d8596d
37 changed files with 4690 additions and 116 deletions
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2
arch/arm/Kconfig
View file

@ -943,9 +943,9 @@ config ARCH_QEMU
config ARCH_RMOBILE
bool "Renesas ARM SoCs"
select BOARD_EARLY_INIT_F if !RZA1
select DM
select DM_SERIAL
imply BOARD_EARLY_INIT_F
imply CMD_DM
imply FAT_WRITE
imply SYS_THUMB_BUILD

10
arch/arm/dts/r8a774a1.dtsi
View file

@ -10,6 +10,8 @@
#include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
#include <dt-bindings/power/r8a774a1-sysc.h>
#define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4
/ {
compatible = "renesas,r8a774a1";
#address-cells = <2>;
@ -2250,7 +2252,7 @@
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
@ -2262,7 +2264,7 @@
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
@ -2274,7 +2276,7 @@
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
@ -2286,7 +2288,7 @@
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;

2630
arch/arm/dts/r8a774b1.dtsi Normal file
View file

File diff suppressed because it is too large Load diff

1664
arch/arm/dts/r8a774e1.dtsi Normal file
View file

File diff suppressed because it is too large Load diff

5
arch/arm/dts/r8a77950-salvator-x-u-boot.dts
View file

@ -8,6 +8,11 @@
#include "r8a77950-salvator-x.dts"
#include "r8a77950-u-boot.dtsi"
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "okay";
};
&sdhi0 {
sd-uhs-sdr12;
sd-uhs-sdr25;

5
arch/arm/dts/r8a77950-ulcb-u-boot.dts
View file

@ -19,6 +19,11 @@
};
};
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "okay";
};
&sdhi0 {
sd-uhs-sdr12;
sd-uhs-sdr25;

5
arch/arm/dts/r8a77960-salvator-x-u-boot.dts
View file

@ -8,6 +8,11 @@
#include "r8a77960-salvator-x.dts"
#include "r8a77960-u-boot.dtsi"
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "okay";
};
&sdhi0 {
sd-uhs-sdr12;
sd-uhs-sdr25;

5
arch/arm/dts/r8a77960-ulcb-u-boot.dts
View file

@ -19,6 +19,11 @@
};
};
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "okay";
};
&sdhi0 {
sd-uhs-sdr12;
sd-uhs-sdr25;

5
arch/arm/dts/r8a77965-salvator-x-u-boot.dts
View file

@ -8,6 +8,11 @@
#include "r8a77965-salvator-x.dts"
#include "r8a77965-u-boot.dtsi"
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "okay";
};
&sdhi0 {
sd-uhs-sdr12;
sd-uhs-sdr25;

5
arch/arm/dts/r8a77965-ulcb-u-boot.dts
View file

@ -19,6 +19,11 @@
};
};
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "okay";
};
&sdhi0 {
sd-uhs-sdr12;
sd-uhs-sdr25;

5
arch/arm/dts/r8a77990-ebisu-u-boot.dts
View file

@ -18,6 +18,11 @@
};
};
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "okay";
};
&sdhi0 {
sd-uhs-sdr12;
sd-uhs-sdr25;

5
arch/arm/dts/r8a77995-draak-u-boot.dts
View file

@ -7,3 +7,8 @@
#include "r8a77995-draak.dts"
#include "r8a77995-u-boot.dtsi"
&rpc {
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
status = "okay";
};

9
arch/arm/mach-rmobile/cpu_info-rcar.c
View file

@ -10,6 +10,7 @@
#define PRR_MASK 0x7fff
#define R8A7796_REV_1_0 0x5200
#define R8A7796_REV_1_1 0x5210
#define R8A7796_REV_1_3 0x5211
static u32 rmobile_get_prr(void)
{
@ -28,8 +29,9 @@ u32 rmobile_get_cpu_type(void)
u32 rmobile_get_cpu_rev_integer(void)
{
const u32 prr = rmobile_get_prr();
const u32 rev = prr & PRR_MASK;
if ((prr & PRR_MASK) == R8A7796_REV_1_1)
if (rev == R8A7796_REV_1_1 || rev == R8A7796_REV_1_3)
return 1;
else
return ((prr & 0x000000F0) >> 4) + 1;
@ -38,9 +40,12 @@ u32 rmobile_get_cpu_rev_integer(void)
u32 rmobile_get_cpu_rev_fraction(void)
{
const u32 prr = rmobile_get_prr();
const u32 rev = prr & PRR_MASK;
if ((prr & PRR_MASK) == R8A7796_REV_1_1)
if (rev == R8A7796_REV_1_1)
return 1;
else if (rev == R8A7796_REV_1_3)
return 3;
else
return prr & 0x0000000F;
}

6
arch/arm/mach-rmobile/lowlevel_init_gen3.S
View file

@ -31,6 +31,12 @@ ENTRY(save_boot_params)
b save_boot_params_ret
ENDPROC(save_boot_params)
.pushsection .text.s_init, "ax"
WEAK(s_init)
ret
ENDPROC(s_init)
.popsection
ENTRY(lowlevel_init)
mov x29, lr /* Save LR */

9
board/renesas/condor/condor.c
View file

@ -18,15 +18,6 @@
DECLARE_GLOBAL_DATA_PTR;
void s_init(void)
{
}
int board_early_init_f(void)
{
return 0;
}
int board_init(void)
{
/* adress of boot parameters */

19
board/renesas/draak/draak.c
View file

@ -30,10 +30,6 @@
DECLARE_GLOBAL_DATA_PTR;
void s_init(void)
{
}
#define GSX_MSTP112 BIT(12) /* 3DG */
#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
#define DVFS_MSTP926 BIT(26)
@ -75,23 +71,10 @@ int board_init(void)
}
#define RST_BASE 0xE6160000
#define RST_CA57RESCNT (RST_BASE + 0x40)
#define RST_CA53RESCNT (RST_BASE + 0x44)
#define RST_RSTOUTCR (RST_BASE + 0x58)
#define RST_CA57_CODE 0xA5A5000F
#define RST_CA53_CODE 0x5A5A000F
void reset_cpu(ulong addr)
{
unsigned long midr, cputype;
asm volatile("mrs %0, midr_el1" : "=r" (midr));
cputype = (midr >> 4) & 0xfff;
if (cputype == 0xd03)
writel(RST_CA53_CODE, RST_CA53RESCNT);
else if (cputype == 0xd07)
writel(RST_CA57_CODE, RST_CA57RESCNT);
else
hang();
writel(RST_CA53_CODE, RST_CA53RESCNT);
}

9
board/renesas/ebisu/ebisu.c
View file

@ -29,15 +29,6 @@
DECLARE_GLOBAL_DATA_PTR;
void s_init(void)
{
}
int board_early_init_f(void)
{
return 0;
}
int board_init(void)
{
/* adress of boot parameters */

4
board/renesas/salvator-x/salvator-x.c
View file

@ -31,10 +31,6 @@
DECLARE_GLOBAL_DATA_PTR;
void s_init(void)
{
}
#define DVFS_MSTP926 BIT(26)
#define HSUSB_MSTP704 BIT(4) /* HSUSB */

4
board/renesas/ulcb/ulcb.c
View file

@ -29,10 +29,6 @@
DECLARE_GLOBAL_DATA_PTR;
void s_init(void)
{
}
#define DVFS_MSTP926 BIT(26)
#define HSUSB_MSTP704 BIT(4) /* HSUSB */

1
configs/grpeach_defconfig
View file

@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="r7s72100-gr-peach-u-boot"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="ignore_loglevel"
# CONFIG_BOARD_EARLY_INIT_F is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_ELF is not set

4
configs/r8a77970_eagle_defconfig
View file

@ -20,6 +20,7 @@ CONFIG_DEFAULT_FDT_FILE="r8a77970-eagle.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_SPI=y
@ -41,6 +42,9 @@ CONFIG_SYSCON=y
CONFIG_BLK=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y

1
configs/r8a77980_condor_defconfig
View file

@ -10,6 +10,7 @@ CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_CONDOR=y
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_DEFAULT_DEVICE_TREE="r8a77980-condor-u-boot"
CONFIG_SMBIOS_PRODUCT_NAME=""
CONFIG_FIT=y

17
configs/r8a77990_ebisu_defconfig
View file

@ -9,6 +9,7 @@ CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_EBISU=y
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_DEFAULT_DEVICE_TREE="r8a77990-ebisu-u-boot"
CONFIG_SMBIOS_PRODUCT_NAME=""
CONFIG_FIT=y
@ -17,11 +18,14 @@ CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.2
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77990-ebisu.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_UPDATE_TFTP=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
@ -41,6 +45,9 @@ CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
@ -49,6 +56,13 @@ CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CFI_FLASH=y
CONFIG_RENESAS_RPC_HF=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BITBANGMII=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
@ -58,6 +72,9 @@ CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_RENESAS_RPC_SPI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_USB=y

11
configs/r8a77995_draak_defconfig
View file

@ -17,11 +17,14 @@ CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.2
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77995-draak.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_UPDATE_TFTP=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
@ -40,6 +43,9 @@ CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
@ -56,6 +62,8 @@ CONFIG_CFI_FLASH=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_RENESAS_RPC_HF=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BITBANGMII=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
@ -65,6 +73,9 @@ CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_RENESAS_RPC_SPI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_USB=y

16
configs/rcar3_salvator-x_defconfig
View file

@ -16,12 +16,15 @@ CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.2
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77950-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_UPDATE_TFTP=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
@ -44,6 +47,9 @@ CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
@ -52,6 +58,13 @@ CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CFI_FLASH=y
CONFIG_RENESAS_RPC_HF=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BITBANGMII=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
@ -64,6 +77,9 @@ CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_RENESAS_RPC_SPI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_USB=y

16
configs/rcar3_ulcb_defconfig
View file

@ -17,11 +17,14 @@ CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.2
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77950-ulcb.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_UPDATE_TFTP=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
@ -44,6 +47,9 @@ CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
@ -52,6 +58,13 @@ CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CFI_FLASH=y
CONFIG_RENESAS_RPC_HF=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BITBANGMII=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
@ -61,6 +74,9 @@ CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_RENESAS_RPC_SPI=y
CONFIG_SYSRESET=y
CONFIG_TEE=y
CONFIG_OPTEE=y

2
drivers/net/ravb.c
View file

@ -438,8 +438,6 @@ static int ravb_config(struct udevice *dev)
writel(mask, eth->iobase + RAVB_REG_ECMR);
phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f << 5) | 0x19);
return 0;
}

20
drivers/pinctrl/renesas/Kconfig
View file

@ -57,6 +57,16 @@ config PINCTRL_PFC_R8A7794
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R8A774A1
bool "Renesas RZ/G2 R8A774A1 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RZ/G2M R8A774A1 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R8A7795
bool "Renesas RCar Gen3 R8A7795 pin control driver"
depends on PINCTRL_PFC
@ -77,16 +87,6 @@ config PINCTRL_PFC_R8A7796
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R8A774A1
bool "Renesas RCar Gen3 R8A774A1 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RZG2M R8A774A1 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R8A77965
bool "Renesas RCar Gen3 R8A77965 pin control driver"
depends on PINCTRL_PFC

12
include/configs/ebisu.h
View file

@ -22,4 +22,16 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_FLASH_CFI_MTD
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 }
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_WRITE_SWAPPED_DATA
#endif /* __EBISU_H */

12
include/configs/salvator-x.h
View file

@ -19,4 +19,16 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_FLASH_CFI_MTD
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 }
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_WRITE_SWAPPED_DATA
#endif /* __SALVATOR_X_H */

12
include/configs/ulcb.h
View file

@ -19,4 +19,16 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_FLASH_CFI_MTD
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 }
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_WRITE_SWAPPED_DATA
#endif /* __ULCB_H */

96
include/dt-bindings/clock/r8a774a1-cpg-mssr.h
View file

@ -10,56 +10,50 @@
/* r8a774a1 CPG Core Clocks */
#define R8A774A1_CLK_Z 0
#define R8A774A1_CLK_Z2 1
#define R8A774A1_CLK_ZR 2
#define R8A774A1_CLK_ZG 3
#define R8A774A1_CLK_ZTR 4
#define R8A774A1_CLK_ZTRD2 5
#define R8A774A1_CLK_ZT 6
#define R8A774A1_CLK_ZX 7
#define R8A774A1_CLK_S0D1 8
#define R8A774A1_CLK_S0D2 9
#define R8A774A1_CLK_S0D3 10
#define R8A774A1_CLK_S0D4 11
#define R8A774A1_CLK_S0D6 12
#define R8A774A1_CLK_S0D8 13
#define R8A774A1_CLK_S0D12 14
#define R8A774A1_CLK_S1D1 15
#define R8A774A1_CLK_S1D2 16
#define R8A774A1_CLK_S1D4 17
#define R8A774A1_CLK_S2D1 18
#define R8A774A1_CLK_S2D2 19
#define R8A774A1_CLK_S2D4 20
#define R8A774A1_CLK_S3D1 21
#define R8A774A1_CLK_S3D2 22
#define R8A774A1_CLK_S3D4 23
#define R8A774A1_CLK_LB 24
#define R8A774A1_CLK_CL 25
#define R8A774A1_CLK_ZB3 26
#define R8A774A1_CLK_ZB3D2 27
#define R8A774A1_CLK_ZB3D4 28
#define R8A774A1_CLK_CR 29
#define R8A774A1_CLK_CRD2 30
#define R8A774A1_CLK_SD0H 31
#define R8A774A1_CLK_SD0 32
#define R8A774A1_CLK_SD1H 33
#define R8A774A1_CLK_SD1 34
#define R8A774A1_CLK_SD2H 35
#define R8A774A1_CLK_SD2 36
#define R8A774A1_CLK_SD3H 37
#define R8A774A1_CLK_SD3 38
#define R8A774A1_CLK_SSP2 39
#define R8A774A1_CLK_SSP1 40
#define R8A774A1_CLK_SSPRS 41
#define R8A774A1_CLK_RPC 42
#define R8A774A1_CLK_RPCD2 43
#define R8A774A1_CLK_MSO 44
#define R8A774A1_CLK_CANFD 45
#define R8A774A1_CLK_HDMI 46
#define R8A774A1_CLK_CSI0 47
#define R8A774A1_CLK_CSIREF 48
#define R8A774A1_CLK_CP 49
#define R8A774A1_CLK_CPEX 50
#define R8A774A1_CLK_R 51
#define R8A774A1_CLK_OSC 52
#define R8A774A1_CLK_ZG 2
#define R8A774A1_CLK_ZTR 3
#define R8A774A1_CLK_ZTRD2 4
#define R8A774A1_CLK_ZT 5
#define R8A774A1_CLK_ZX 6
#define R8A774A1_CLK_S0D1 7
#define R8A774A1_CLK_S0D2 8
#define R8A774A1_CLK_S0D3 9
#define R8A774A1_CLK_S0D4 10
#define R8A774A1_CLK_S0D6 11
#define R8A774A1_CLK_S0D8 12
#define R8A774A1_CLK_S0D12 13
#define R8A774A1_CLK_S1D2 14
#define R8A774A1_CLK_S1D4 15
#define R8A774A1_CLK_S2D1 16
#define R8A774A1_CLK_S2D2 17
#define R8A774A1_CLK_S2D4 18
#define R8A774A1_CLK_S3D1 19
#define R8A774A1_CLK_S3D2 20
#define R8A774A1_CLK_S3D4 21
#define R8A774A1_CLK_LB 22
#define R8A774A1_CLK_CL 23
#define R8A774A1_CLK_ZB3 24
#define R8A774A1_CLK_ZB3D2 25
#define R8A774A1_CLK_ZB3D4 26
#define R8A774A1_CLK_CR 27
#define R8A774A1_CLK_CRD2 28
#define R8A774A1_CLK_SD0H 29
#define R8A774A1_CLK_SD0 30
#define R8A774A1_CLK_SD1H 31
#define R8A774A1_CLK_SD1 32
#define R8A774A1_CLK_SD2H 33
#define R8A774A1_CLK_SD2 34
#define R8A774A1_CLK_SD3H 35
#define R8A774A1_CLK_SD3 36
#define R8A774A1_CLK_RPC 37
#define R8A774A1_CLK_RPCD2 38
#define R8A774A1_CLK_MSO 39
#define R8A774A1_CLK_HDMI 40
#define R8A774A1_CLK_CSI0 41
#define R8A774A1_CLK_CP 42
#define R8A774A1_CLK_CPEX 43
#define R8A774A1_CLK_R 44
#define R8A774A1_CLK_OSC 45
#define R8A774A1_CLK_CANFD 46
#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */

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include/dt-bindings/clock/r8a774b1-cpg-mssr.h Normal file
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/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a774b1 CPG Core Clocks */
#define R8A774B1_CLK_Z 0
#define R8A774B1_CLK_ZG 1
#define R8A774B1_CLK_ZTR 2
#define R8A774B1_CLK_ZTRD2 3
#define R8A774B1_CLK_ZT 4
#define R8A774B1_CLK_ZX 5
#define R8A774B1_CLK_S0D1 6
#define R8A774B1_CLK_S0D2 7
#define R8A774B1_CLK_S0D3 8
#define R8A774B1_CLK_S0D4 9
#define R8A774B1_CLK_S0D6 10
#define R8A774B1_CLK_S0D8 11
#define R8A774B1_CLK_S0D12 12
#define R8A774B1_CLK_S1D2 13
#define R8A774B1_CLK_S1D4 14
#define R8A774B1_CLK_S2D1 15
#define R8A774B1_CLK_S2D2 16
#define R8A774B1_CLK_S2D4 17
#define R8A774B1_CLK_S3D1 18
#define R8A774B1_CLK_S3D2 19
#define R8A774B1_CLK_S3D4 20
#define R8A774B1_CLK_LB 21
#define R8A774B1_CLK_CL 22
#define R8A774B1_CLK_ZB3 23
#define R8A774B1_CLK_ZB3D2 24
#define R8A774B1_CLK_CR 25
#define R8A774B1_CLK_DDR 26
#define R8A774B1_CLK_SD0H 27
#define R8A774B1_CLK_SD0 28
#define R8A774B1_CLK_SD1H 29
#define R8A774B1_CLK_SD1 30
#define R8A774B1_CLK_SD2H 31
#define R8A774B1_CLK_SD2 32
#define R8A774B1_CLK_SD3H 33
#define R8A774B1_CLK_SD3 34
#define R8A774B1_CLK_RPC 35
#define R8A774B1_CLK_RPCD2 36
#define R8A774B1_CLK_MSO 37
#define R8A774B1_CLK_HDMI 38
#define R8A774B1_CLK_CSI0 39
#define R8A774B1_CLK_CP 40
#define R8A774B1_CLK_CPEX 41
#define R8A774B1_CLK_R 42
#define R8A774B1_CLK_OSC 43
#define R8A774B1_CLK_CANFD 44
#endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */

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include/dt-bindings/clock/r8a774e1-cpg-mssr.h Normal file
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/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* R8A774E1 CPG Core Clocks */
#define R8A774E1_CLK_Z 0
#define R8A774E1_CLK_Z2 1
#define R8A774E1_CLK_ZG 2
#define R8A774E1_CLK_ZTR 3
#define R8A774E1_CLK_ZTRD2 4
#define R8A774E1_CLK_ZT 5
#define R8A774E1_CLK_ZX 6
#define R8A774E1_CLK_S0D1 7
#define R8A774E1_CLK_S0D2 8
#define R8A774E1_CLK_S0D3 9
#define R8A774E1_CLK_S0D4 10
#define R8A774E1_CLK_S0D6 11
#define R8A774E1_CLK_S0D8 12
#define R8A774E1_CLK_S0D12 13
#define R8A774E1_CLK_S1D2 14
#define R8A774E1_CLK_S1D4 15
#define R8A774E1_CLK_S2D1 16
#define R8A774E1_CLK_S2D2 17
#define R8A774E1_CLK_S2D4 18
#define R8A774E1_CLK_S3D1 19
#define R8A774E1_CLK_S3D2 20
#define R8A774E1_CLK_S3D4 21
#define R8A774E1_CLK_LB 22
#define R8A774E1_CLK_CL 23
#define R8A774E1_CLK_ZB3 24
#define R8A774E1_CLK_ZB3D2 25
#define R8A774E1_CLK_ZB3D4 26
#define R8A774E1_CLK_CR 27
#define R8A774E1_CLK_CRD2 28
#define R8A774E1_CLK_SD0H 29
#define R8A774E1_CLK_SD0 30
#define R8A774E1_CLK_SD1H 31
#define R8A774E1_CLK_SD1 32
#define R8A774E1_CLK_SD2H 33
#define R8A774E1_CLK_SD2 34
#define R8A774E1_CLK_SD3H 35
#define R8A774E1_CLK_SD3 36
#define R8A774E1_CLK_RPC 37
#define R8A774E1_CLK_RPCD2 38
#define R8A774E1_CLK_MSO 39
#define R8A774E1_CLK_HDMI 40
#define R8A774E1_CLK_CSI0 41
#define R8A774E1_CLK_CP 42
#define R8A774E1_CLK_CPEX 43
#define R8A774E1_CLK_R 44
#define R8A774E1_CLK_OSC 45
#define R8A774E1_CLK_CANFD 46
#endif /* __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ */

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include/dt-bindings/power/r8a774a1-sysc.h
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#define R8A774A1_PD_CA53_CPU2 7
#define R8A774A1_PD_CA53_CPU3 8
#define R8A774A1_PD_CA57_SCU 12
#define R8A774A1_PD_CR7 13
#define R8A774A1_PD_A3VC 14
#define R8A774A1_PD_3DG_A 17
#define R8A774A1_PD_3DG_B 18
#define R8A774A1_PD_CA53_SCU 21
#define R8A774A1_PD_A3IR 24
#define R8A774A1_PD_A2VC0 25
#define R8A774A1_PD_A2VC1 26

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/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A774B1_SYSC_H__
#define __DT_BINDINGS_POWER_R8A774B1_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A774B1_PD_CA57_CPU0 0
#define R8A774B1_PD_CA57_CPU1 1
#define R8A774B1_PD_A3VP 9
#define R8A774B1_PD_CA57_SCU 12
#define R8A774B1_PD_A3VC 14
#define R8A774B1_PD_3DG_A 17
#define R8A774B1_PD_3DG_B 18
#define R8A774B1_PD_A2VC1 26
/* Always-on power area */
#define R8A774B1_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ */

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/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
#define __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A774E1_PD_CA57_CPU0 0
#define R8A774E1_PD_CA57_CPU1 1
#define R8A774E1_PD_CA57_CPU2 2
#define R8A774E1_PD_CA57_CPU3 3
#define R8A774E1_PD_CA53_CPU0 5
#define R8A774E1_PD_CA53_CPU1 6
#define R8A774E1_PD_CA53_CPU2 7
#define R8A774E1_PD_CA53_CPU3 8
#define R8A774E1_PD_A3VP 9
#define R8A774E1_PD_CA57_SCU 12
#define R8A774E1_PD_A3VC 14
#define R8A774E1_PD_3DG_A 17
#define R8A774E1_PD_3DG_B 18
#define R8A774E1_PD_3DG_C 19
#define R8A774E1_PD_3DG_D 20
#define R8A774E1_PD_CA53_SCU 21
#define R8A774E1_PD_3DG_E 22
#define R8A774E1_PD_A2VC1 26
/* Always-on power area */
#define R8A774E1_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ */