As we aren't quite able to convert some platforms with a very small size
limit in SPL yet, we need to revert this for now.
This reverts commit 7b09477873.
Signed-off-by: Tom Rini <trini@konsulko.com>
As we aren't quite able to convert some platforms with a very small size
limit in SPL yet, we need to revert this for now.
This reverts commit 37434db29b.
Signed-off-by: Tom Rini <trini@konsulko.com>
This patch adds a command that enables the calculation of bit operations
(AND, OR, XOR) on binary data from the command line. Memory locations as
well as the contents of environment variables are eligible as sources
and destination of the binary data used in the operations.
The possible applications are manifold: Setting specific bits in
registers using the regular read-OR-write pattern, masking out bits in
bit values, implementation of simple OTP encryption using the XOR
operation, etc.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
A debug string still has the old name of a function being called; update
it.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Fix Kconfig alignment which should be <tab><space><space>.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
SPL ATF implementation requires FIT image with partitions where the one
is Firmware/ATF and another one Firmware/U-Boot. OS field is used for
recording that difference that's why make sense to show values there for
Firmware types.
For example:
Image 0 (atf)
Description: ATF bl31.bin
Created: Mon Mar 26 15:58:14 2018
Type: Firmware
Compression: uncompressed
Data Size: 51152 Bytes = 49.95 KiB = 0.05 MiB
Architecture: ARM
OS: ARM Trusted Firmware
Load Address: 0xfffe0000
Hash algo: md5
Hash value: 36a4212bbb698126bf5a248f0f4b5336
Image 1 (uboot)
Description: u-boot.bin
Created: Mon Mar 26 15:58:14 2018
Type: Firmware
Compression: uncompressed
Data Size: 761216 Bytes = 743.38 KiB = 0.73 MiB
Architecture: ARM
OS: U-Boot
Load Address: 0x08000000
Hash algo: md5
Hash value: f22960fe429be72296dc8dc59a47d566
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
SPL ATF support requires to have firmware property which should be also
listed by mkimage -l when images is created.
The patch is also using this macro in spl_fit to match keyword.
When image is created:
Default Configuration: 'config'
Configuration 0 (config)
Description: ATF with full u-boot
Kernel: unavailable
Firmware: atf
FDT: dtb
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Move am43xx_evm_qspiboot_defconfig to DM. This is required as SPI core
and TI QSPI driver no longer supports non DM interfaces.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
With U-boot runtime board detect for DTB selection a "default" dtb needs
to be created. This will be used temporarily until the "proper" dtb is
selected.
Also, add -u-boot.dtsi for AM437x SK and IDK to enable I2C for
board detection via DM_I2C.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
AM437x QSPI boot is a single stage boot and hence needs runtime DTB
selection to support AM437x-SK and AM437x-IDK with DM enabled. This is
required to move am43xx_evm_qspiboot_defconfig to use DM/DT.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Use CONFIG_IS_ENABLED to see if CONFIG_BLK is enabled. Otherwise
SPL compilation breaks on boards which do have CONFIG_BLK enabled but
not DM_MMC for the SPL as follows:
env/mmc.c: In function ‘init_mmc_for_env’:
env/mmc.c:164:6: warning: implicit declaration of function ‘blk_get_from_parent’; did you mean ‘efi_get_ram_base’? [-Wimplicit-function-declaration]
if (blk_get_from_parent(mmc->dev, &dev))
^~~~~~~~~~~~~~~~~~~
efi_get_ram_base
env/mmc.c:164:29: error: ‘struct mmc’ has no member named ‘dev’
if (blk_get_from_parent(mmc->dev, &dev))
^~
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>
As of commit 1a1fa24066 ("rtc: Set valid date after reset") the
command "date reset" will set the date/time to 2000-01-01 0:00:00 after
calling rtc_reset(). This means that the rx8025 implementation of
rtc_reset() does not need to call rtc_set().
Signed-off-by: Chris Packham <judge.packham@gmail.com>
As of commit 1a1fa24066 ("rtc: Set valid date after reset") the
command "date reset" will set the date/time to 2000-01-01 0:00:00 after
calling rtc_reset(). This means that the rs5c372 implementation of
rtc_reset() does not need to call rtc_set().
Signed-off-by: Chris Packham <judge.packham@gmail.com>
As of commit 1a1fa24066 ("rtc: Set valid date after reset") the
command "date reset" will set the date/time to 2000-01-01 0:00:00 after
calling rtc_reset(). This means that the mx27rtc implementation of
rtc_reset() can be an empty stub function.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
As of commit 1a1fa24066 ("rtc: Set valid date after reset") the
command "date reset" will set the date/time to 2000-01-01 0:00:00 after
calling rtc_reset(). This means that the ds1374 implementation of
rtc_reset() doesn't need to call rtc_set().
Signed-off-by: Chris Packham <judge.packham@gmail.com>
As of commit 1a1fa24066 ("rtc: Set valid date after reset") the
command "date reset" will set the date/time to 2000-01-01 0:00:00 after
calling rtc_reset(). This means that the ds1307 implementation of
rtc_reset() doesn't need to call rtc_set().
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add support of sysreset with generic driver "syscon-reboot"
provided by RCC, for U-boot and for SPL.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
No more use static frequency HSI = 64MHz for STGEN clock
but HSE (with higher accurency) by default.
Need to remove CONFIG_SYS_HZ_CLOCK as arch timer frequency
is provided at boot by BootRom and cp15 cntfrq and modified
during clock tree initialization if needed.
When HSI is no more used by any device, this internal
oscillator can be switched off to reduce consumption.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
The STGEN is the clock source for the Cortex A7 arch timer.
So after modification of its frequency, CP15 cntfreq is updated
and a new timer init is performed.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Manage dynamic value for armv7 arch clock timer,
when CONFIG_SYS_HZ_CLOCK is not defined.
Get frequency from CP15 cntfrq information, initialized for example
by first boot stage, clock driver or by BootRom.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Modifying the default environment via CONFIG_EXTRA_ENV_SETTINGS is
somewhat inflexible, partly because the cpp language does not allow
appending to an existing macro. This prevents reuse of "environment
fragments" for different boards, which in turn makes maintaining that
environment consistently tedious and error-prone.
This implements a Kconfig option for allowing one to define the entire
default environment in an external file, which can then, for example, be
generated programmatically as part of a Yocto recipe, or simply be kept
in version control separately from the U-boot repository.
Tested-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Bootrom loads SPL from SDCARD or eMMC
according BootPin selection.
Then SPL loads U-Boot on the same mmc device
with the following predefined GPT partitioning:
on SDCARD: gpt partitioning
1: SPL
2: SPL#2
3: U-Boot
4: bootable partition
on eMMC:
The 2 boot partitions are used for SPL (2 copy)
boot1: SPL
boot2: SPL#2
The user partition use gpt partitioning
1: U-Boot
2: bootable partition
This patch select the correct SPL partition
(3 for SDCARD on mmc0 and 1 for eMMC on mmc1)
according the BootRom information saved in TAMP register
and based on configuration flasg:
- CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
=> for BOOT_DEVICE_MMC1 or mmc 0 in U-Boot
- CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 (new)
=> for BOOT_DEVICE_MMC2 or mmc 1 in U-Boot
And the correct boot_targets is selected according the environment
variables boot_device and boot_instance, with preboot command,
to search the bootable partition with kernel on this device
(generic distro support).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
SPL copy BootRom boot mode information
in TAMP register 21.
This TAMP register information is used
after relocation to set 2 env variables
- boot_device
- boot_instance
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add command GPT support
Add EMMC boot support
Add the 2 other SDMMC instances for ED1:
- SDMMC2 = mmc 1, eMMC on the ED1 board
- SDMMC3 = extension connector, deactivated by default
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
The spl_boot_partition function has been added in order to have
the possibility to boot on a same binary from different mmc devices
with different partitions.
By default keep the current behavior, SPL use the partition defined
by CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Adds devicemodel support to the ISL1208 driver.
This patch drops the non-dm API as no board was using it anyway.
Also add it to Kconfig.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The mxsimage utility fails to compile against LibreSSL version < 2.7.0
because LibreSSL says it is OpenSSL 2.0, but it does not support the
complete OpenSSL 1.1 interface.
LibreSSL defines OPENSSL_VERSION_NUMBER with 0x20000000L and therefor
claims to have an API compatible with OpenSSL 2.0, but it implements
EVP_MD_CTX_new(), EVP_MD_CTX_free() and EVP_CIPHER_CTX_reset() only
starting with version 2.7.0, which is not yet released. OpenSSL
implements this function since version 1.1.0.
This commit will activate the compatibility code meant for
OpenSSL < 1.1.0 also for LibreSSL version < 2.7.0.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Reviewed-by: Jonathan Gray <jsg@jsg.id.au>
We should not evaluate the value of reg before its value is set.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
The boot scripts for booting from ramdisk are using
${fdtimage} when they really should be using ${fdtaddr}
This patch will fix it so the RAMdisk bootscripts operate
correctly.
Signed-off-by: Adam Ford <aford173@gmail.com>
This inhibits the re-inititialization of DDR during an RTC-only resume. If
this is not done, an L3 NOC error is produced as the DDR gets accessed
before the re-init has time to complete. Tested on AM437x GP EVM.
Signed-off-by: Russ Dill <Russ.Dill@ti.com>
[j-keerthy@ti.com Ported to Latest Master branch]
Signed-off-by: Keerthy <j-keerthy@ti.com>
Prevent EMIF control of DDR_RESET line on DDR3 am43xx platforms for
am43xx_evm_rtconly_config. Without this DDR is unstable and can become
corrupted after multiple iterations of RTC+DDR mode.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[j-keerthy@ti.com Ported to latest master branch]
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Kernel stores information to the RTC_SCRATCH0 and RTC_SCRATCH1 registers
for wakeup from RTC-only mode with DDR in self-refresh. Parse these
registers during SPL boot and jump to the kernel resume vector if the
device is waking up from RTC-only modewith DDR in Self-refresh.
The RTC scratch register layout used is:
SCRATCH0 : bits00-31 : kernel resume address
SCRATCH1 : bits00-15 : RTC magic value used to detect valid config
SCRATCH1 : bits16-31 : board type information populated by bootloader
During the normal boot path the SCRATCH1 : bits16-31 are updated with
the eeprom read board type data. In the rtc_only boot path the rtc
scratchpad register is read and the board type is determined and
correspondingly ddr dpll parameters are set. This is done so as to avoid
costly i2c read to eeprom.
RTC-only +DRR in self-refresh mode support is currently only enabled for
am43xx_evm_rtconly_config.
This is not to be used with epos evm builds.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
[j-keerthy@ti.com Rebased to latest u-boot master branch]
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Enable NETCONSOLE by default. Still requires changes to the boot
environment to enable on the platform.
Signed-of-by: Jason Kridner <jdk@ti.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
NETCONSOLE isn't compiled in with SPL, so the include file needs to recognize that.
Signed-off-by: Jason Kridner <jdk@ti.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Texas Instruments AM3358 based low-cost board using Octavo Systems OSD3358 SIP
with built-in TPS65217 PMIC and 512MB DDR3. Board features small 35mm x
55mm size, high-speed USB OTG, microSD and 72 0.1" expansion header
pins with 2xSPI, 2xI2C, 2xUART, USB, 8xADC, up-to-44 GPIO, PRU pins and much more.
https://beagleboard.org/pocket
This was tested using the am335x_evm_usbspl_defconfig.
Note that MII pins are enabled despite not having Ethernet on this
board. This avoids an issue where otherwise many timeout errors would be
generated. See https://e2e.ti.com/support/arm/sitara_arm/f/791/t/298976
for some related discussion.
Signed-off-by: Jason Kridner <jdk@ti.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
In preparation of migration to DM watchdog, clean up a bit.
The 8xx watchdog really is a HW watchdog, so declare it as is
then it goes through Kconfig
And the watchdog reset doesn't mind getting interrupted, so
no need to disable interrupts
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
