Commit graph

69221 commits

Author SHA1 Message Date
Simon Glass
dd30c5bb57 x86: sound: Correct error handling
A few functions have changed to return pin numbers or I2C addresses. The
error checking for some of the callers is therefore wrong. Fix them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 09:51:29 +08:00
Simon Glass
a0ed800376 x86: Show the interrupt pointer with 'irqinfo'
It is useful for this command to show the address of the interrupt table.
Add support for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 09:51:29 +08:00
Simon Glass
8bcfb7917a x86: nhlt: Fix a few bugs in the table generation
At present these tables do not have the correct header, and there is an
occasional incorrect value due to uninited data. Fix these bugs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 09:51:29 +08:00
Simon Glass
a87fff80ee x86: nhlt: Correct output of bytes and 16-bit data
At present these functions are incorrect. Fix them and add some logging
and checking to avoid future problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 09:51:29 +08:00
Simon Glass
d2cb7a22da x86: Allow putting some tables in the bloblist
At present all tables are placed starting at address f0000 in memory, and
can be up to 64KB in size. If the tables are very large, this may not
provide enough space.

Also if the tables point to other tables (such as console log or a ramoops
area) then we must allocate other memory anyway.

The bloblist is a nice place to put these tables since it is contiguous,
which makes it easy to reserve this memory for linux using the 820 tables.

Add an option to put some of the tables in the bloblist. For SMBIOS and
ACPI, create suitable pointers from the f0000 region to the new location
of the tables.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: squashed in http://patchwork.ozlabs.org/project/uboot/patch/
 20201105062407.1.I8091ad931cbbb5e3b6f6ababdf3f8d5db0d17bb9@changeid/]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 09:51:28 +08:00
Simon Glass
f36e4c7d80 x86: Use if instead of #ifdef in write_tables()
Use if() to remove the extra build path in this code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
cac9c6a38f x86: Add SMBIOS info for Coral
This is required by Chrome OS so that the audio and other unibuild
features work correctly. Add it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
726310166b x86: coral: Drop the duplicate PCIe settings
These settings are included twice. The second lot are correct, so drop the
others.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
dc0791d415 x86: Don't bother clearing global NVS
The bloblist guarantees that blobs are zeroed so there is no need to do
an additional memset(). Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
5019e201cc x86: acpi: Store the ACPI context in global_data
At present we create the ACPI context but then drop it after generation of
tables is complete. This is annoying because we have to then search for
tables later.

To fix this, allocate the context and store it in global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
38e498c3a2 x86: Allow writing tables to fail
At present write_tables() can fail but does not report this problem to its
caller. Fix this by changing the return type.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
653554b40a x86: Add support for private files
Some boards need to include binary data into the image for use during the
boot process. Add a node for these.

An example is the audio-codec configuration used by some audio drivers on
Intel platforms. If no private files are provided, they will be omitted.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
dac7778d74 x86: Add a layout for Chrome OS verified boot
Add definitions for part of the vboot context used with verified boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
6571d87315 x86: apl: Add core init for the SoC
Set up MSRs required for Apollo Lake. This enables Linux to use the
timers correctly. Also write the fixed MSRs for this platform.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
1779b8a96a Add an assembly guard around linux/bitops.h
This file can be included by any header but it includes C code. Guard it
to avoid errors when compiling ASL, etc.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Christian Gmeiner
43a218b653 coreboot: make use of smbios parser
If u-boot gets used as coreboot payload it might be nice to get
vendor, model and bios version from smbios. I am not sure about
the output of all the read information.

With qemu target for coreboot this could look this:

CBFS: Found @ offset 14f40 size 3b188
Checking segment from ROM address 0xffc15178
Checking segment from ROM address 0xffc15194
Loading segment from ROM address 0xffc15178
  code (compression=1)
  New segment dstaddr 0x01110000 memsize 0x889ef srcaddr 0xffc151b0 filesize 0x3b150
Loading Segment: addr: 0x01110000 memsz: 0x00000000000889ef filesz: 0x000000000003b150
using LZMA
Loading segment from ROM address 0xffc15194
  Entry Point 0x01110000
BS: BS_PAYLOAD_LOAD run times (exec / console): 77 / 1 ms
Jumping to boot code at 0x01110000(0x07fa7000)

U-Boot 2020.10-00536-g5dcf7cc590-dirty (Oct 07 2020 - 14:21:51 +0200)

CPU: x86_64, vendor AMD, device 663h
DRAM:  127.1 MiB
MMC:
Video: No video mode configured in coreboot!
Video: No video mode configured in coreboot!
Vendor: QEMU
Model: Standard PC (i440FX + PIIX, 1996)
Bios Version: 4.12-3152-g326a499f6f-dirty
Net:   e1000: 52:54:00:12:34:56
       eth0: e1000#0
No working controllers found
Finalizing coreboot
Hit any key to stop autoboot:  0

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Christian Gmeiner
415eab0655 smbios: add parsing API
Add a very simple API to be able to access SMBIOS strings
like vendor, model and bios version.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
9d20db0483 x86: Fix up driver names to avoid dtoc warnings
At present there are a lot of dtoc warnings reported when building
chromebook_coral, of the form:

   WARNING: the driver intel_apl_lpc was not found in the driver list

Correct these by using driver names that matches their compatible string.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
ed0f868d50 cros_ec: Fix up driver names to avoid dtoc warnings
Fix the dtoc warning in these file by using a driver name that matches the
compatible string.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Michal Simek
35b7ca768f arch: Move NEEDS_MANUAL_RELOC symbol to Kconfig
CONFIG_NEEDS_MANUAL_RELOC macro was out of Kconfig. Move it there to be
able to use compile-time checks to reduce the number of build paths.

Fixes: f9a882438966 ("dm: core: Convert #ifdef to if() in root.c") for Microblaze
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-11-04 10:13:44 -05:00
Heiko Schocher
46ce9e777c env: sf: fix init function behaviour
Michael wrote:
commit 92765f45bb ("env: Access Environment in SPI flashes before
relocation") at least breaks the Kontron sl28 board. I guess it also
breaks others which use a (late) SPI environment.

reason is, that env_init() sets the init bit, if there
is no init function defined in an environment driver,
and use default return value -ENOENT in this case
later for setting the default environment.

Change:
Environment driver can now implement an init
function and return, if this function does nothing,
simply -ENOENT.

env_init() now handles -ENOENT correct by setting the
inited bit for the environment driver. And if there
is no other environment driver whose init function
returns 0, load than the default environment.

This prevents that each environment driver needs to set the
default environment.

Fixes: 92765f45bb ("env: Access Environment in SPI flashes before relocation")
Reported-by: Michael Walle <michael@walle.cc>
Tested-by: Michael Walle <michael@walle.cc> [For the SF environment]
Signed-off-by: Heiko Schocher <hs@denx.de>
2020-11-03 10:04:25 -05:00
Tom Rini
7a8ac9df5d First set of u-boot-atmel fixes for 2021.01 cycle
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Merge tag 'u-boot-atmel-fixes-2021.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel

First set of u-boot-atmel fixes for 2021.01 cycle:

This specific feature set includes the patches for DT required to fix
the warnings for newer DTC version (1.6.0+), i2c and spi bus unit
address.
2020-11-02 09:01:28 -05:00
Eugen Hristev
ef8f34aea5 ARM: dts: at91: sama5d3xmb_cmp: fix SPI bus unit address
w+arch/arm/dts/.at91sam9260ek.dtb.pre.tmp:119.21-123.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:38 +02:00
Eugen Hristev
2733e6fe5d ARM: dts: at91: sam9260ek: fix SPI bus unit address
w+arch/arm/dts/.at91sam9260ek.dtb.pre.tmp:119.21-123.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:38 +02:00
Eugen Hristev
9f37458b30 ARM: dts: at91: sama5d3xmb: fix I2C bus unit address
w+arch/arm/dts/sama5d3xmb.dtsi:64.25-83.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f0018000/camera@0x30: I2C bus unit address format error, expected "30"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:38 +02:00
Eugen Hristev
e0df9e846c ARM: dts: at91: gurnard: fix SPI bus unit address
w+arch/arm/dts/.at91sam9g45-gurnard.dtb.pre.tmp:118.21-122.7: Warning (spi_bus_reg): /ahb/apb/spi@fffa4000/mtd_dataflash@0: SPI bus unit address format error, expected "1"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:38 +02:00
Eugen Hristev
397a28604c ARM: dts: at91: at91sam9g25ek: fix I2C bus unit address
w+arch/arm/dts/.at91sam9g25ek.dtb.pre.tmp:28.25-47.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f8010000/camera@0x30: I2C bus unit address format error, expected "30"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:38 +02:00
Eugen Hristev
6f668d2756 ARM: dts: at91: at91sam9g20ek_common: fix SPI bus unit address
w+arch/arm/dts/at91sam9g20ek_common.dtsi:100.21-104.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:37 +02:00
Eugen Hristev
f56a0ca685 ARM: dts: at91: at91sam9g20-taurus: fix SPI bus unit address
w+arch/arm/dts/.at91sam9g20-taurus.dtb.pre.tmp:79.18-83.4: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:37 +02:00
Eugen Hristev
a013df93e1 ARM: dts: at91: at91sam9261ek: fix SPI unit address warning
w+arch/arm/dts/.at91sam9261ek.dtb.pre.tmp:124.15-144.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/tsc2046@0: SPI bus unit address format error, expected "2"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:37 +02:00
Eugen Hristev
7d0cad03d5 ARM: dts: at91: vinco: fix I2C warning bus unit address
w+arch/arm/dts/.at91-vinco.dtb.pre.tmp:131.18-134.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f8024000/rtc@64: I2C bus unit address format error, expected "32"

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-11-02 08:58:37 +02:00
Tom Rini
41cab8edbc Pull request for UEFI sub-system for efi-2021-01-rc2 (2)
The series contains the following enhancements
 
 * preparatory patches for UEFI capsule updates
 * initialization of the emulated RTC using an environment variable
 
 and a bug fix
 
 * If DisconnectController() is called for a child controller that is the
   only child of the driver, the driver must be disconnected.
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Merge tag 'efi-2020-01-rc2-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for UEFI sub-system for efi-2021-01-rc2 (2)

The series contains the following enhancements

* preparatory patches for UEFI capsule updates
* initialization of the emulated RTC using an environment variable

and a bug fix

* If DisconnectController() is called for a child controller that is the
  only child of the driver, the driver must be disconnected.
2020-11-01 10:56:37 -05:00
Tom Rini
2c31d7e746 Merge tag 'u-boot-rockchip-20201031' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- New PX30 board: Engicam PX30.Core;
- Fix USB HID support for rock960;
- Remove host endianness dependency for rockchip mkimage;
- dts update for rk3288-tinker;
- Enable console MUX for some ROCKPi boards;
- Add config-based ddr selection for px30;
2020-10-30 23:13:13 -04:00
Tom Rini
63d4607e03 of-platdata and dtoc improvements
sandbox SPL tests
 binman support for compressed sections
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Merge tag 'dm-pull-30oct20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm

of-platdata and dtoc improvements
sandbox SPL tests
binman support for compressed sections
2020-10-30 15:24:30 -04:00
Heinrich Schuchardt
096912b5fe log: typo logl_pref in documentation
The name of structure element logl_prev is not matched by the
documentation.

%s/logl_pref/logl_prev/

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-30 14:38:04 -04:00
Tom Rini
7820052fde Merge branch '2020-10-30-misc-changes'
- Additional log improvements
- SPI flash environment improvements
2020-10-30 14:17:23 -04:00
Jagan Teki
43ed7a098d doc: rockchip: Document Rockchip miniloader flashing
This would be useful and recommended boot flow for new boards
which has doesn't have the DDR support yet in mainline.

Sometimes it is very useful for debugging mainline DDR support.

Documen it for px30 boot flow.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Jagan Teki
51656ae1d1 rockchip: Add Engicam PX30.Core C.TOUCH 2.0
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.

C.TOUCH 2.0 is a general purpose carrier board with capacitive
touch interface support.

PX30.Core needs to mount on top of this Carrier board for creating
complete PX30.Core C.TOUCH 2.0 board.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Jagan Teki
d432975cec arm64: dts: rockchip: px30: Add Engicam C.TOUCH 2.0
Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose
carrier board with capacitive touch interface.

Genaral features:
- TFT 10.1" industrial, 1280x800 LVDS display
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- LVDS panel connector

SOM's like PX30.Core needs to mount on top of this Carrier board
for creating complete PX30.Core C.TOUCH 2.0 board.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Jagan Teki
39c8b2c72a rockchip: Add Engicam PX30.Core EDIMM2.2 Starter Kit
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.

EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board from Engicam.

PX30.Core needs to mount on top of this Evaluation board for
creating complete PX30.Core EDIMM2.2 Starter Kit.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Jagan Teki
ce87a88b4d board: engicam: Attach i.MX6 common code
The existing common code for Engicam boards uses i.MX6,
so attach that into i.MX6 Engicam boards so-that adding
new SoC variants of Engicam boards become meaningful.

Add support for it.

Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Jagan Teki
cf1b86a3ae rockchip: px30: Add EVB_PX30 Kconfig help
TARGET_EVB_PX30 can be possible to use other px30 boards.

Add the help text for existing EVB, so-that the new boards
which are resuing this config option can mention their board
help text.

This would help to track which boards are using EVB_PX30 config.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Michael Trimarchi
9946bfd4a0 arm64: dts: rockchip: Add Engicam PX30.Core SOM
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.

General features:
- Rockchip PX30
- Up to 2GB DDR4
- eMMC 4 GB expandible
- rest of PX30 features

PX30.Core needs to mount on top of Engicam baseboards for creating
complete platform boards.

Possible baseboards are,
- EDIMM2.2
- C.TOUCH 2.0

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Jagan Teki
282ad86aaa arm64: dts: rockchip: px30: Add Engicam EDIMM2.2 Starter Kit
Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.

Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out

SOM's like PX30.Core needs to mount on top of this Evaluation board
for creating complete PX30.Core EDIMM2.2 Starter Kit.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-10-30 23:31:26 +08:00
Samuel Holland
29ef48efe1 rockchip: mkimage: Remove host endianness dependency
The Rockchip boot ROM expects little-endian values in the image header.
When running mkimage on a big-endian machine, these values need to be
byteswapped before writing or verifying the header.

This change fixes cross-compiling U-Boot SPL for the RK3399 SoC from a
big-endian ppc64 host machine.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 23:09:56 +08:00
Jagan Teki
d2ebd86d2e rockchip: Enable Console MUX in ROCKPi N8
Enable Console multiplexing in ROCKPi N8 which would is
required to video out the console buffer.

Enable it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 23:09:23 +08:00
Jagan Teki
9abece3985 video: rockchip: Support 4K resolution for rk3288, HDMI
Like, rk3399 the rk3288 also supports 4K resolution.

So, enable it for rk3288 with HDMI platforms.

Right now, rockchip video drivers are supporting for rk3288,
rk3399 SoC families, so mark the 4K resolution by default
if it's an HDMI video out.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Cc: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 23:09:01 +08:00
Jagan Teki
dfec5a4ec0 arm64: dts: rockchip: Add chosen node for ROCK-Pi N8
Add chosen node in -u-boot.dtsi for ROCK-Pi N8 board.

This will help to get serial out messages.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 23:09:01 +08:00
Jagan Teki
cffcd48109 rockchip: Enable Console MUX in ROCKPi N10
Enable Console multiplexing in ROCKPi N10 which would is
required to video out the console buffer.

Enable it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 23:09:00 +08:00
Sean Anderson
8ba0f89abe doc: Update logging documentation
This updates logging documentation with some examples of the new commands
added in the previous commits. It also removes some items from the to-do
list which have been implemented.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-30 11:00:13 -04:00