Commit graph

84414 commits

Author SHA1 Message Date
Tom Rini
b102bfa15e Merge branch '2023-02-02-assorted-networking-updates'
- DSA driver for the MV88E6xxx, assorted IPv6 fixes, TFTP fix, fsl-mc
  cleanup coding style and fsl_ls_mdio bugfix
2023-02-03 10:27:27 -05:00
Peter Robinson
01f372d8d6 udoo_neo: Select DM_SERIAL and drop iomux board level init
Convert to DM_SERIAL and drop the iomux board file
level init as it's handled as part of the DM serial
layer instead.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-02-03 13:10:01 +01:00
Peter Robinson
99a94c368c udoo_neo: Move to DM for REGULATOR/PMIC/I2C drivers
This moves over the PMIC power init to DM and the associated i2c and
regulator bits.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-02-03 13:10:01 +01:00
Marek Vasut
c64b840ef3 ARM: imx: mx5: Convert MX53 Menlo board to DM SERIAL
Convert the board from legacy serial code to DM SERIAL.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-02-03 12:41:17 +01:00
Sergei Antonov
9bc80c0bc0 net: ipv6: fix alignment errors on ARM
Commands "ping6" and "tftpboot ... -ipv6" did not work on ARM because
machine code expects 4-byte alignment and some structures from net6.h
are not aligned in memory.

Fix by adding __packed, since it is already used in this file.

Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
2023-02-02 14:44:53 -05:00
Ehsan Mohandesi
7db25d99b2 net: ipv6: Fixed IPv6 string to address conversion off-by-one error
One extra character was being checked in the IPv6 string which caused the
last character of the address to be neither '\0' nor ':'. This raises an
error condition and causes the function to always return an error. This
issue was resolved by this fix.

Signed-off-by: Ehsan Mohandesi <emohandesi@microsoft.com>
Reviewed-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
2023-02-02 14:44:53 -05:00
Sean Edmond
796e549822 net: ipv6: Fix IPv6 netmask parsing
It should be possible to specify a netmask when
setting a static IPv6 address.  For example:
setenv ip6addr 2001:cafe:cafe:cafe::100/64

The net_prefix_length and net_ip6 should be updated
properly.

Signed-off-by: Sean Edmond <seanedmond@microsoft.com>
Reviewed-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-02 14:44:53 -05:00
Ioana Ciornei
878a20aa15 drivers: net: fsl_ls_mdio: prevent a NULL pointer dereference
Prevent a NULL pointer dereference in the probe path by checking the
return valud of dev_read_addr_ptr() against NULL.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-02 14:44:53 -05:00
Ioana Ciornei
cfbd388ae7 drivers: net: fsl-mc: do not use multiple blank lines
Remove the instances in which we have multiple blank lines.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-02 14:44:53 -05:00
Ioana Ciornei
f45ed0b5ec drivers: net: fsl-mc: align parameters to the open paranthesis
There were some cases in which the function parameters were not aligned
to the open paranthesis. Fix those instances.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-02 14:44:53 -05:00
Ioana Ciornei
6dcf5e4477 drivers: net: fsl-mc: remove explicit cast
Remove all the explicit casts from the void* returned by calloc.
With this we also improve a bit the length of those lines and there is
no need to split the assignment.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-02 14:44:53 -05:00
Ioana Ciornei
8ecf1ca093 drivers: net: fsl-mc: do not prefix decimal values with 0x
The fsl-mc driver printed debug information which used the 0x prefix for
decimal values. This only confuses anyone looking through the log.
Because of this, just remove the prefix and use the "DPXY.<id>" notation
which is the standard one for the DPAA2 objects.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-02 14:44:53 -05:00
Ioana Ciornei
3ad24e4d36 drivers: net: fsl-mc: remove an useless break statement
The break statement is just after a goto statement, thus it will not get
executed. Just remove it.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-02 14:44:53 -05:00
Ioana Ciornei
32221ee236 drivers: net: fsl-mc: remove useless assignment of variable
The cur_ptr variable is set to the start of the log buffer but then it's
not used. Just remove the assignment altogether.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-02 14:44:53 -05:00
Sean Edmond
21a265c0d1 net: tftp: Fix for DATA ACK for block count out of order
In rfc7440, if an ACK is not received by the server or if the
last data block in a window is dropped, the server will timeout and
retransmit the window.  In this case, the block count received will be
less than the internal block count.  In this case, the client
should not ACK.  ACK should only be sent if the received block
count is greater than the expected block count.

Signed-off-by: Sean Edmond <seanedmond@linux.microsoft.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-02 14:44:53 -05:00
Tim Harvey
c3d9736d54 board: gw_ventana: enable MV88E61XX DSA support
Add MV88E61XX DSA support:
 - update dt to provide internal MDIO bus and port handles.
   U-Boot requires a more restrictive subset of the dt bindings
   required by Linux for the sake of simplifying code
 - update defconfig to remove old driver and enable new one
 - replace mv88e61xx_hw_reset weak override with board_phy_config support
   for register configuration that is outside the scope of the DSA driver

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
2023-02-02 14:44:53 -05:00
Tim Harvey
01e7dd050f net: add MV88E6xxx DSA driver
Add a DSA driver for the MV88E6xxx compatible Ethernet switches.

Cc: Marek Behún <marek.behun@nic.cz>
Cc: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-02-02 14:44:53 -05:00
Tim Harvey
3b8f99a3e7 net: fec: add support for DM_MDIO
Add support for DM_MDIO by registering a UCLASS_MDIO driver and
attempting to use it. This is necessary if wanting to use a DSA
driver for example hanging off of the FEC MAC.

Care is taken to fallback to non DM_MDIO mii bus as several boards define
DM_MDIO without having the proper device-tree configuration necessary
such as an mdio subnode, a phy-mode prop, and either a valid phy-handle
prop or fixed-phy subnode which will cause dm_eth_phy_connect() to fail.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-02-02 14:44:51 -05:00
Tim Harvey
8abb9f6b17 net: ksz9477: remove unnecessary xmit and recv functions
Remove the unnecessary xmit and recv functions.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-02-02 14:22:08 -05:00
Tim Harvey
54d11e2019 net: dsa: allow rcv() and xmit() to be optional
Allow rcv() and xmit() dsa driver ops to be optional in case a driver
does not care to mangle a packet as in U-Boot only one network port is
enabled at a time and thus no packet mangling is necessary.

Suggested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2023-02-02 14:22:08 -05:00
Tim Harvey
43c2a00a14 net: dsa: ensure dsa driver has proper ops
Add a function to sanity check a dsa driver having proper ops.

Suggested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-02-02 14:22:08 -05:00
Tim Harvey
c5868fcd25 net: dsa: move cpu port probe to dsa_post_probe
In order to ensure that a DSA driver probe gets called before
dsa_ops->port_probe move the port_probe of the cpu_port to
a post-probe function.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-02-02 14:22:08 -05:00
Tim Harvey
f54002d774 net: mdio-uclass: scan for dm mdio children on post-bind
If a DM_MDIO driver is used we need to scan the subnodes as well.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-02-02 14:22:08 -05:00
Tom Rini
9918b25d21 Merge commit 'refs/pipelines/15015' of https://source.denx.de/u-boot/custodians/u-boot-tegra 2023-02-02 12:44:12 -05:00
Svyatoslav Ryhel
412a4c6f1b ARM: tegra: include timer as default option
Enable TIMER and TEGRA_TIMER for TEGRA_ARMV7_COMMON and TEGRA210.
Additionally enable SPL_TIMER if build as SPL part and drop
deprecated configs from common header.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-02 10:16:41 -07:00
Svyatoslav Ryhel
adf869045d drivers: timer: add driver for ARMv7 based Tegra devices and T210
Add timer support for T20/T30/T114/T124 and T210 based devices.
Driver is based on DM, has device tree support and can be
used on SPL and early boot stage.

Arm64 Tegra (apart T210) according to comment in tegra-common.h use
architected timer.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Co-developed-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-02 10:16:41 -07:00
Svyatoslav Ryhel
87a758652b ARM: tegra: remap clock_osc_freq for all Tegra family
Enum clock_osc_freq was designed to use only with T20.
This patch remaps it to use additional frequencies, added in
T30+ SoC while maintaining backwards compatibility with T20.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20
Tested-by: Thierry Reding <treding@nvidia.com> # T30, T124, T210
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-02 10:16:41 -07:00
Tom Rini
57e1634836 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv 2023-02-02 09:25:59 -05:00
Tom Rini
4ea115b379 Merge https://source.denx.de/u-boot/custodians/u-boot-sh 2023-02-01 20:47:32 -05:00
Marek Vasut
1006b33b3a net: ravb: Drop SoC-specific compatible support
The current set of U-Boot upstream R-Car Gen3 DTs all contain generic
"renesas,etheravb-rcar-gen3" compatible strings, drop the SoC specific
compatible string support from U-Boot to reduce size and duplication.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:21 +01:00
Hai Pham
92ddeb45c0 configs: draak: Enable I2C support for R-Car D3
Enable I2C support on D3 Draak.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Hai Pham
1b4ca865b2 clk: renesas: rcar-gen3: Factor out CPG library
R-Car V3U has a CPG different enough to not be a generic Gen3 CPG but
similar enough to reuse code. Introduce a new CPG library, factor out
the SD clock and RPC clock handling and hook them to the generic Gen3
CPG driver so we have an equal state.

Based on Linux commit [1] and [2] by Wolfram Sang

[1] 8bb67d87346a ("clk: renesas: rcar-gen3: Factor out CPG library")
[2] 6f21d145b90f ("clk: renesas: cpg-lib: Move RPC clock registration to
the library")

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Add rcar_clk_* prefix to all functions
       - Rebase on changes to
         clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function
       - Use u32_encode_bits/GENMASK bitfield ops
2023-02-02 01:49:20 +01:00
Hai Pham
d8132ae37a clk: renesas: Add R8A77970 SD0H/SD0 clocks for SDHI
On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on
the other R-Car gen3 SoCs. Hence, new clock types are introduced
respectively.

Based on Linux commit 381081ffc294 ("clk: renesas: r8a77970: Add SD0H/SD0
clocks for SDHI") by Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Fix missing ~ in GENMASK(a, b), use clrsetbits_le32 instead
       - Do not modify r8a77970-cpg-mssr.c much, drop enum r8a77970_clk_types
         which is now part of common clock types in rcar-gen3-cpg.h instead
2023-02-02 01:49:20 +01:00
Hai Pham
4dbbc3f373 clk: renesas: Switch to new SD clock handling
The old SD handling code was huge and could not handle all the details
which showed up on R-Car Gen3 SoCs meanwhile. It is time to switch to
another design. Have SDnH a separate clock, use the existing divider
clocks and move the errata handling from the clock driver to the SDHI
driver where it belongs.

Based on Linux series by Wolfram Sang, commit bb6d3fa98a41 ("clk:
renesas: rcar-gen3: Switch to new SD clock handling") and commit
e5f7e81ee430a ("mmc: renesas_sdhi: Parse DT for SDnH")

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Add rcar_clk_* prefix to all functions
       - Fix missing ~ in GENMASK(a, b), use clrsetbits_le32 instead
       - Use DIV_ROUND_CLOSEST, else if parent clock = 199999992 and
         rate = 200000000, the divider would be 0 and table lookup
	 would fail.
       - Turn rcar_clk_get_table_val into signed integer, so it can
         return 0 as a valid value and negative values as errors.
       - Make the code operate on correct clock and add comment
         which explains the reasoning behind it.
       - Rebase on changes to
         clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function
2023-02-02 01:49:20 +01:00
Hai Pham
c287c184ae clk: renesas: Handle E3/D3 RPCSRC clock
The RPCSRC clock divider on R-Car D3 is very similar to the one on R-Car
E3, but uses a different pre-divider for the PLL0 parent.  Add a new
macro to describe it, reusing the existing clock type for R-Car E3.

As both E3/D3 RPCSRC clock divider are different from the rest of R-Car
Gen3, keep the original implementation from Linux.

Based on Linux commit 40745482eec8 ("clk: renesas: r8a774c0: Add RPC
clocks") by Lad Prabhakar and 9d18f81b3535 ("clk: renesas: r8a77995: Add
RPC clocks") by Geert Uytterhoeven.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Add D3 tweaks
2023-02-02 01:49:20 +01:00
Hai Pham
a1ec0bbc28 clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function
Introduce new helper function to handle clock type that uses
clk_div_table struct. Based vaguely on Linux code. Make use
of clk_div_table in RPC clocks handling.

The E3/D3 RPCSRC need to be handled differently and will be addressed in
subsequence patch.

Based on Linux commit db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC
clocks") by Sergei Shtylyov.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Squash patches to avoid adding unused code:
         clk: renesas: Make use of clk_div_table in RPC clocks handling
         clk: renesas: Introduce rcar_clk_get_rate64_div_table function
       - Move the new code to the beginning of clk-rcar-gen3 to avoid
         tables mixed with code
       - Use rcar_ prefix for get_table_div function
       - Get rid of custom macros, use GENMASK. Use custom field_get
         implementation as the generic FIELD_GET does not support
	 constant mask and u32_get_bits requires higher optimization level
       - Pass in the register bit mask instead of width/shift combination
       - Turn rcar_clk_get_rate64_div_table into s64, as it can return -EINVAL
2023-02-02 01:49:20 +01:00
Marek Vasut
d48c38db13 clk: renesas: Convert Gen2/Gen3 clock tables to clk-provider struct clk_div_table
Replace custom local structure with matching one from clk-provider.h .
No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Hai Pham
3c78ce8680 mmc: renesas-sdhi: Flag non-standard SDnH handling for V3M
V3M handles SDnH differently than other Gen3 SoCs, so let's add a
separate entry for that. This will allow better SDnH handling in the
future.

Based on Linux commit 627151b4966f ("mmc: renesas_sdhi: Flag
non-standard SDnH handling for V3M") by Wolfram Sang

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-02 01:49:20 +01:00
Hai Pham
89f9e729be mmc: renesas-sdhi: Drop R-Car H3 ES3.0 HS400 calibration table
It is unnecessary, so clean it up.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # update commit message, mention ES3.0
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-02 01:49:20 +01:00
Hai Pham
d919bb9830 mmc: renesas-sdhi: Add R8A77961 M3-W+ support
Support R8A77961 M3-W+ SoC.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-02 01:49:20 +01:00
Hai Pham
1cdabcc6a4 mmc: renesas-sdhi: Adjust HS400 calibration offsets for M3-W r1.3
Still uses 0x3 for now, adjust the offset value to TMPPORT3 accordingly

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-02 01:49:20 +01:00
Hai Pham
af95db514d mmc: renesas-sdhi: Adjust HS400 calibration tables
Adjust HS400 calibration tables based on Linux settings

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-02 01:49:20 +01:00
Hai Pham
6d7d4c4821 mmc: renesas-sdhi: Filter out HS400 on M3-W r1.2, V3M, V3H r1.x, D3
Further filter out HS400 support on certain SoCs.

Since M3-W r1.2 does not support HS400, drop the calibration table and
rename the one for M3-W r1.3 to r8a7796_rev13_calib_table

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-02 01:49:20 +01:00
Hai Pham
01cbce80c1 mmc: renesas-sdhi: R-Car M3 r1.3 also uses 4 tuning taps
Early ES revisions of M3-W SoCs requires 4-tap HS400. Reflect the status
from datasheet.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
a61a824169 clk: renesas: Drop core param from gen3_clk_get_rate64_pll_mul_reg
Drop 'core' parameter from gen3_clk_get_rate64_pll_mul_reg() function
as it is only used in debug print. No functional change except for the
debug print, which is disabled by default.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Hai Pham
21a8dbc369 clk: renesas: Use pre-defined offset for RPC clocks
Since commit f7b4e4c094 ("clk: renesas: Synchronize R-Car Gen3 tables
with Linux 5.12"), the custom macros for RPC clocks were dropped.

Use pre-defined offset for RPC clocks, same as what Linux does, instead
of retrieving it from the macros

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
326e05c5e2 clk: renesas: Add and enable CPG reset driver
Add trivial reset driver extension to the CPG clock driver. The change
turns current CPG UCLASS_CLK driver instance into an UCLASS_NOP proxy
driver, which in turn binds both generic rcar3_clk UCLASS_CLK clock
driver as well as generic rcar_rst UCLASS_RESET reset driver to the
CPG DT node. This way, any other drivers which use the 'reset' DT
property can now obtain valid reset handle backed by a reset driver.

The clock tables have been updated to represent the CPG driver and only
implement the generic CPG proxy driver bind call, which binds the clock
and reset drivers.

The DM_RESET is now enabled for all R-Car Gen3 platforms.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Hai Pham
d1c886f563 clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support
Add support for the R-Car M3-W+ (R8A77961) SoC.
R-Car M3-W+ is very similar to R-Car M3-W (R8A77960), which allows for
both SoCs to share a driver.

Based on Linux commit 2ba738d56db4 ("clk: renesas: r8a7796: Add R8A77961
CPG/MSSR support")

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Hai Pham
9d16ed44f0 clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960
Rename CONFIG_CLK_R8A7796 for R-Car M3-W (R8A77960) to
CONFIG_CLK_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961),
which will use CONFIG_CLK_R8A77961.

Based on Linux commit 92d1ebae9abf ("clk: renesas: Rename CLK_R8A7796
to CLK_R8A77960")

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
83fc4729a5 clk: renesas: Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.1.7
Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00