mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-03-16 23:07:00 +00:00
This commit is contained in:
Tom Rini
commit
4ea115b379
117 changed files with 12508 additions and 6804 deletions
|
|
@ -5,7 +5,7 @@
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|||
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||||
#include <dt-bindings/gpio/gpio.h>
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||||
#include <dt-bindings/input/input.h>
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||||
#include <dt-bindings/clk/versaclock.h>
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||||
#include <dt-bindings/clock/versaclock.h>
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||||
|
||||
/ {
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||||
backlight_lvds: backlight-lvds {
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||||
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@ -146,7 +146,7 @@
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|||
};
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||||
};
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||||
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||||
reg_audio: regulator_audio {
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||||
reg_audio: regulator-audio {
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||||
compatible = "regulator-fixed";
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||||
regulator-name = "audio-1.8V";
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||||
regulator-min-microvolt = <1800000>;
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@ -174,7 +174,7 @@
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vin-supply = <®_lcd>;
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||||
};
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||||
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||||
reg_cam0: regulator_camera {
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reg_cam0: regulator-cam0 {
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||||
compatible = "regulator-fixed";
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regulator-name = "reg_cam0";
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regulator-min-microvolt = <1800000>;
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@ -183,7 +183,7 @@
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enable-active-high;
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};
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||||
reg_cam1: regulator_camera {
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reg_cam1: regulator-cam1 {
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compatible = "regulator-fixed";
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regulator-name = "reg_cam1";
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regulator-min-microvolt = <1800000>;
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@ -272,8 +272,14 @@
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status = "okay";
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};
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&du_out_rgb {
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remote-endpoint = <&rgb_panel>;
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&du {
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ports {
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port@0 {
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du_out_rgb: endpoint {
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||||
remote-endpoint = <&rgb_panel>;
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||||
};
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};
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};
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};
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&ehci0 {
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@ -359,11 +365,10 @@
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clocks = <&x304_clk>;
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clock-names = "xin";
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assigned-clocks = <&versaclock6_bb 1>,
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<&versaclock6_bb 2>,
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<&versaclock6_bb 3>,
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<&versaclock6_bb 4>;
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assigned-clock-rates = <24000000>, <24000000>, <24000000>, <24576000>;
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assigned-clocks = <&versaclock6_bb 1>, <&versaclock6_bb 2>,
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<&versaclock6_bb 3>, <&versaclock6_bb 4>;
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assigned-clock-rates = <24000000>, <24000000>, <24000000>,
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<24576000>;
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OUT1 {
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idt,mode = <VC5_CMOS>;
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@ -4,7 +4,7 @@
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clk/versaclock.h>
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#include <dt-bindings/clock/versaclock.h>
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/ {
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memory@48000000 {
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@ -20,7 +20,7 @@
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clock-output-names = "osc_32k";
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};
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reg_1p8v: regulator0 {
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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@ -29,7 +29,7 @@
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regulator-always-on;
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};
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reg_3p3v: regulator1 {
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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@ -77,7 +77,7 @@
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};
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&gpio6 {
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usb_hub_reset {
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usb-hub-reset-hog {
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gpio-hog;
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gpios = <10 GPIO_ACTIVE_HIGH>;
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output-high;
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@ -293,7 +293,6 @@
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vqmmc-supply = <®_1p8v>;
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non-removable;
|
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cap-power-off-card;
|
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pm-ignore-notify;
|
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keep-power-in-suspend;
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mmc-pwrseq = <&wlan_pwrseq>;
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status = "okay";
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||||
|
|
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|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* Device Tree Source for the Silicon Linux sub board for CAT874 (CAT875)
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||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
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* Copyright (C) 2019 Renesas Electronics Corp.
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*/
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/ {
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@ -18,9 +18,12 @@
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pinctrl-names = "default";
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renesas,no-ether-link;
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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status = "okay";
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||||
|
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phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id001c.c915",
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"ethernet-phy-ieee802.3-c22";
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reg = <0>;
|
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interrupt-parent = <&gpio2>;
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||||
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
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||||
|
|
|
|||
548
arch/arm/dts/condor-common.dtsi
Normal file
548
arch/arm/dts/condor-common.dtsi
Normal file
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@ -0,0 +1,548 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
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* Device Tree Source for the Condor board with R-Car V3H
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*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
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* Copyright (C) 2018 Cogent Embedded, Inc.
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*/
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#include <dt-bindings/gpio/gpio.h>
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/ {
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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serial0 = &scif0;
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ethernet0 = &gether;
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};
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|
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chosen {
|
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stdout-path = "serial0:115200n8";
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||||
};
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|
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d1_8v: regulator-2 {
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compatible = "regulator-fixed";
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regulator-name = "D1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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d3_3v: regulator-0 {
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compatible = "regulator-fixed";
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regulator-name = "D3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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hdmi-out {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_con: endpoint {
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remote-endpoint = <&adv7511_out>;
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};
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};
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};
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lvds-decoder {
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compatible = "thine,thc63lvd1024";
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vcc-supply = <&d3_3v>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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thc63lvd1024_in: endpoint {
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remote-endpoint = <&lvds0_out>;
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};
|
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};
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port@2 {
|
||||
reg = <2>;
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||||
thc63lvd1024_out: endpoint {
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||||
remote-endpoint = <&adv7511_in>;
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||||
};
|
||||
};
|
||||
};
|
||||
};
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|
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memory@48000000 {
|
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0 0x48000000 0 0x78000000>;
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};
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vddq_vin01: regulator-1 {
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compatible = "regulator-fixed";
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regulator-name = "VDDQ_VIN01";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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x1_clk: x1-clock {
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||||
compatible = "fixed-clock";
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#clock-cells = <0>;
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||||
clock-frequency = <148500000>;
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||||
};
|
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};
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&canfd {
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pinctrl-0 = <&canfd0_pins>;
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||||
pinctrl-names = "default";
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status = "okay";
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||||
|
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channel0 {
|
||||
status = "okay";
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||||
};
|
||||
};
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||||
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&csi40 {
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status = "okay";
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||||
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ports {
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||||
port@0 {
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csi40_in: endpoint {
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||||
clock-lanes = <0>;
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||||
data-lanes = <1 2 3 4>;
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||||
remote-endpoint = <&max9286_out0>;
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};
|
||||
};
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||||
};
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};
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&csi41 {
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status = "okay";
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ports {
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port@0 {
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csi41_in: endpoint {
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clock-lanes = <0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
remote-endpoint = <&max9286_out1>;
|
||||
};
|
||||
};
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||||
};
|
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};
|
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|
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&du {
|
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clocks = <&cpg CPG_MOD 724>,
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<&x1_clk>;
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clock-names = "du.0", "dclkin.0";
|
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status = "okay";
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};
|
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|
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&extal_clk {
|
||||
clock-frequency = <16666666>;
|
||||
};
|
||||
|
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&extalr_clk {
|
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clock-frequency = <32768>;
|
||||
};
|
||||
|
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&gether {
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pinctrl-0 = <&gether_pins>;
|
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pinctrl-names = "default";
|
||||
|
||||
phy-mode = "rgmii-id";
|
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phy-handle = <&phy0>;
|
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renesas,no-ether-link;
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id0022.1622",
|
||||
"ethernet-phy-ieee802.3-c22";
|
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rxc-skew-ps = <1500>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
io_expander0: gpio@20 {
|
||||
compatible = "onnn,pca9654";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
io_expander1: gpio@21 {
|
||||
compatible = "onnn,pca9654";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
hdmi@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
|
||||
avdd-supply = <&d1_8v>;
|
||||
dvdd-supply = <&d1_8v>;
|
||||
pvdd-supply = <&d1_8v>;
|
||||
bgvdd-supply = <&d1_8v>;
|
||||
dvdd-3v-supply = <&d3_3v>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
gmsl0: gmsl-deserializer@48 {
|
||||
compatible = "maxim,max9286";
|
||||
reg = <0x48>;
|
||||
|
||||
maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
|
||||
enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
max9286_out0: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
remote-endpoint = <&csi40_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c-mux {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gmsl1: gmsl-deserializer@4a {
|
||||
compatible = "maxim,max9286";
|
||||
reg = <0x4a>;
|
||||
|
||||
maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
|
||||
enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
max9286_out1: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
remote-endpoint = <&csi41_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c-mux {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lvds0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
pinctrl-0 = <&mmc_pins>;
|
||||
pinctrl-1 = <&mmc_pins>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&d3_3v>;
|
||||
vqmmc-supply = <&vddq_vin01>;
|
||||
mmc-hs200-1_8v;
|
||||
bus-width = <8>;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pciec {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_bus_clk {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pfc {
|
||||
canfd0_pins: canfd0 {
|
||||
groups = "canfd0_data_a";
|
||||
function = "canfd0";
|
||||
};
|
||||
|
||||
gether_pins: gether {
|
||||
groups = "gether_mdio_a", "gether_rgmii",
|
||||
"gether_txcrefclk", "gether_txcrefclk_mega";
|
||||
function = "gether";
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
groups = "i2c0";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1 {
|
||||
groups = "i2c1";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
mmc_pins: mmc {
|
||||
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
|
||||
function = "mmc";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
qspi0_pins: qspi0 {
|
||||
groups = "qspi0_ctrl", "qspi0_data4";
|
||||
function = "qspi0";
|
||||
};
|
||||
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk_b";
|
||||
function = "scif_clk";
|
||||
};
|
||||
};
|
||||
|
||||
&rpc {
|
||||
pinctrl-0 = <&qspi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "spansion,s25fs512s", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
bootparam@0 {
|
||||
reg = <0x00000000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
cr7@40000 {
|
||||
reg = <0x00040000 0x080000>;
|
||||
read-only;
|
||||
};
|
||||
cert_header_sa3@c0000 {
|
||||
reg = <0x000c0000 0x080000>;
|
||||
read-only;
|
||||
};
|
||||
bl2@140000 {
|
||||
reg = <0x00140000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
cert_header_sa6@180000 {
|
||||
reg = <0x00180000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
bl31@1c0000 {
|
||||
reg = <0x001c0000 0x460000>;
|
||||
read-only;
|
||||
};
|
||||
uboot@640000 {
|
||||
reg = <0x00640000 0x0c0000>;
|
||||
read-only;
|
||||
};
|
||||
uboot-env@700000 {
|
||||
reg = <0x00700000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
dtb@740000 {
|
||||
reg = <0x00740000 0x080000>;
|
||||
};
|
||||
kernel@7c0000 {
|
||||
reg = <0x007c0000 0x1400000>;
|
||||
};
|
||||
user@1bc0000 {
|
||||
reg = <0x01bc0000 0x2440000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rwdt {
|
||||
timeout-sec = <60>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
};
|
||||
744
arch/arm/dts/draak.dtsi
Normal file
744
arch/arm/dts/draak.dtsi
Normal file
|
|
@ -0,0 +1,744 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the Draak board
|
||||
*
|
||||
* Copyright (C) 2016-2018 Renesas Electronics Corp.
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Renesas Draak board";
|
||||
compatible = "renesas,draak";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif2;
|
||||
ethernet0 = &avb;
|
||||
};
|
||||
|
||||
audio_clkout: audio-clkout {
|
||||
/*
|
||||
* This is same as <&rcar_sound 0>
|
||||
* but needed to avoid cs2000/rcar_sound probe dead-lock
|
||||
*/
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12288000>;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 50000>;
|
||||
|
||||
brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
|
||||
default-brightness-level = <10>;
|
||||
|
||||
power-supply = <®_12p0v>;
|
||||
enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
composite-in {
|
||||
compatible = "composite-video-connector";
|
||||
|
||||
port {
|
||||
composite_con_in: endpoint {
|
||||
remote-endpoint = <&adv7180_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-in {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&adv7612_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_out: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&keys_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
key-1 {
|
||||
gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_1>;
|
||||
label = "SW56-1";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-2 {
|
||||
gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_2>;
|
||||
label = "SW56-2";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-3 {
|
||||
gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_3>;
|
||||
label = "SW56-3";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-4 {
|
||||
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_4>;
|
||||
label = "SW56-4";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
};
|
||||
|
||||
lvds-decoder {
|
||||
compatible = "thine,thc63lvd1024";
|
||||
vcc-supply = <®_3p3v>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
thc63lvd1024_in: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
thc63lvd1024_out: endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x18000000>;
|
||||
};
|
||||
|
||||
reg_1p8v: regulator-1p8v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_12p0v: regulator-12p0v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "D12.0V";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sound_card: sound {
|
||||
compatible = "audio-graph-card";
|
||||
|
||||
dais = <&rsnd_port0 /* ak4613 */
|
||||
/* HDMI is not yet supported */
|
||||
>;
|
||||
};
|
||||
|
||||
vga {
|
||||
compatible = "vga-connector";
|
||||
|
||||
port {
|
||||
vga_in: endpoint {
|
||||
remote-endpoint = <&adv7123_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vga-encoder {
|
||||
compatible = "adi,adv7123";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7123_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7123_out: endpoint {
|
||||
remote-endpoint = <&vga_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
x12_clk: x12 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <74250000>;
|
||||
};
|
||||
|
||||
x19_clk: x19 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24576000>;
|
||||
};
|
||||
};
|
||||
|
||||
&audio_clk_b {
|
||||
/*
|
||||
* X11 is connected to VI4_FIELD/SCIF_CLK/AUDIO_CLKB,
|
||||
* and R-Car Sound uses AUDIO_CLKB.
|
||||
* Note is that schematic indicates VI4_FIELD conection only
|
||||
* not AUDIO_CLKB at SoC page.
|
||||
* And this VI4_FIELD/SCIF_CLK/AUDIO_CLKB is connected to SW60.
|
||||
* SW60 should be 1-2.
|
||||
*/
|
||||
|
||||
clock-frequency = <22579200>;
|
||||
};
|
||||
|
||||
&avb {
|
||||
pinctrl-0 = <&avb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
renesas,no-ether-link;
|
||||
phy-handle = <&phy0>;
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id0022.1622",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
rxc-skew-ps = <1500>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>;
|
||||
/*
|
||||
* TX clock internal delay mode is required for reliable
|
||||
* 1Gbps communication using the KSZ9031RNX phy present on
|
||||
* the Draak board, however, TX clock internal delay mode
|
||||
* isn't supported on R-Car D3(e). Thus, limit speed to
|
||||
* 100Mbps for reliable communication.
|
||||
*/
|
||||
max-speed = <100>;
|
||||
};
|
||||
};
|
||||
|
||||
&can0 {
|
||||
pinctrl-0 = <&can0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can1 {
|
||||
pinctrl-0 = <&can1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&x12_clk>;
|
||||
clock-names = "du.0", "du.1", "dclkin.0";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
du_out_rgb: endpoint {
|
||||
remote-endpoint = <&adv7123_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
&hsusb {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
ak4613: codec@10 {
|
||||
compatible = "asahi-kasei,ak4613";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x10>;
|
||||
clocks = <&rcar_sound 0>; /* audio_clkout */
|
||||
|
||||
asahi-kasei,in1-single-end;
|
||||
asahi-kasei,in2-single-end;
|
||||
asahi-kasei,out1-single-end;
|
||||
asahi-kasei,out2-single-end;
|
||||
asahi-kasei,out3-single-end;
|
||||
asahi-kasei,out4-single-end;
|
||||
asahi-kasei,out5-single-end;
|
||||
asahi-kasei,out6-single-end;
|
||||
|
||||
port {
|
||||
ak4613_endpoint: endpoint {
|
||||
remote-endpoint = <&rsnd_for_ak4613>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
composite-in@20 {
|
||||
compatible = "adi,adv7180cp";
|
||||
reg = <0x20>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7180_in: endpoint {
|
||||
remote-endpoint = <&composite_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
|
||||
/*
|
||||
* The VIN4 video input path is shared between
|
||||
* CVBS and HDMI inputs through SW[49-53]
|
||||
* switches.
|
||||
*
|
||||
* CVBS is the default selection, link it to
|
||||
* VIN4 here.
|
||||
*/
|
||||
adv7180_out: endpoint {
|
||||
remote-endpoint = <&vin4_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
hdmi-encoder@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>, <0x3f>, <0x3c>, <0x38>;
|
||||
reg-names = "main", "edid", "cec", "packet";
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-decoder@4c {
|
||||
compatible = "adi,adv7612";
|
||||
reg = <0x4c>;
|
||||
default-input = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
adv7612_in: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
/*
|
||||
* The VIN4 video input path is shared between
|
||||
* CVBS and HDMI inputs through SW[49-53]
|
||||
* switches.
|
||||
*
|
||||
* CVBS is the default selection, leave HDMI
|
||||
* not connected here.
|
||||
*/
|
||||
adv7612_out: endpoint {
|
||||
pclk-sample = <0>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cs2000: clk-multiplier@4f {
|
||||
#clock-cells = <0>;
|
||||
compatible = "cirrus,cs2000-cp";
|
||||
reg = <0x4f>;
|
||||
clocks = <&audio_clkout>, <&x19_clk>; /* audio_clkout_1, x19 */
|
||||
clock-names = "clk_in", "ref_clk";
|
||||
|
||||
assigned-clocks = <&cs2000>;
|
||||
assigned-clock-rates = <24576000>; /* 1/1 divide */
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "rohm,br24t01", "atmel,24c01";
|
||||
reg = <0x50>;
|
||||
pagesize = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lvds0 {
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 727>,
|
||||
<&x12_clk>,
|
||||
<&extal_clk>;
|
||||
clock-names = "fck", "dclkin.0", "extal";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lvds1 {
|
||||
/*
|
||||
* Even though the LVDS1 output is not connected, the encoder must be
|
||||
* enabled to supply a pixel clock to the DU for the DPAD output when
|
||||
* LVDS0 is in use.
|
||||
*/
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 727>,
|
||||
<&x12_clk>,
|
||||
<&extal_clk>;
|
||||
clock-names = "fck", "dclkin.0", "extal";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pfc {
|
||||
avb0_pins: avb {
|
||||
groups = "avb0_link", "avb0_mdio", "avb0_mii";
|
||||
function = "avb0";
|
||||
};
|
||||
|
||||
can0_pins: can0 {
|
||||
groups = "can0_data_a";
|
||||
function = "can0";
|
||||
};
|
||||
|
||||
can1_pins: can1 {
|
||||
groups = "can1_data_a";
|
||||
function = "can1";
|
||||
};
|
||||
|
||||
du_pins: du {
|
||||
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
|
||||
function = "du";
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
groups = "i2c0";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1 {
|
||||
groups = "i2c1";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
keys_pins: keys {
|
||||
pins = "GP_4_12", "GP_4_13", "GP_4_14", "GP_4_15";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pwm0_pins: pwm0 {
|
||||
groups = "pwm0_c";
|
||||
function = "pwm0";
|
||||
};
|
||||
|
||||
pwm1_pins: pwm1 {
|
||||
groups = "pwm1_c";
|
||||
function = "pwm1";
|
||||
};
|
||||
|
||||
rpc_pins: rpc {
|
||||
groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset",
|
||||
"rpc_int";
|
||||
function = "rpc";
|
||||
};
|
||||
|
||||
scif2_pins: scif2 {
|
||||
groups = "scif2_data";
|
||||
function = "scif2";
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
groups = "mmc_data8", "mmc_ctrl";
|
||||
function = "mmc";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi2_pins_uhs: sd2_uhs {
|
||||
groups = "mmc_data8", "mmc_ctrl";
|
||||
function = "mmc";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sound_pins: sound {
|
||||
groups = "ssi34_ctrl", "ssi3_data", "ssi4_data_a";
|
||||
function = "ssi";
|
||||
};
|
||||
|
||||
sound_clk_pins: sound-clk {
|
||||
groups = "audio_clk_a", "audio_clk_b",
|
||||
"audio_clkout", "audio_clkout1";
|
||||
function = "audio_clk";
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
||||
groups = "usb0";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
vin4_pins_cvbs: vin4 {
|
||||
groups = "vin4_data8", "vin4_sync", "vin4_clk";
|
||||
function = "vin4";
|
||||
};
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
pinctrl-0 = <&pwm0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-0 = <&pwm1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* Single DAI */
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
/* audio_clkout0/1 */
|
||||
#clock-cells = <1>;
|
||||
clock-frequency = <12288000 11289600>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
<&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>,
|
||||
<&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
|
||||
<&cs2000>, <&audio_clk_b>,
|
||||
<&cpg CPG_CORE R8A77995_CLK_ZA2>;
|
||||
|
||||
ports {
|
||||
rsnd_port0: port {
|
||||
rsnd_for_ak4613: endpoint {
|
||||
remote-endpoint = <&ak4613_endpoint>;
|
||||
dai-format = "left_j";
|
||||
bitclock-master = <&rsnd_for_ak4613>;
|
||||
frame-master = <&rsnd_for_ak4613>;
|
||||
playback = <&ssi3>, <&src5>, <&dvc0>;
|
||||
capture = <&ssi4>, <&src6>, <&dvc1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rpc {
|
||||
pinctrl-0 = <&rpc_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* Left disabled. To be enabled by firmware when unlocked. */
|
||||
|
||||
flash@0 {
|
||||
compatible = "cypress,hyperflash", "cfi-flash";
|
||||
reg = <0>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
bootparam@0 {
|
||||
reg = <0x00000000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
bl2@40000 {
|
||||
reg = <0x00040000 0x140000>;
|
||||
read-only;
|
||||
};
|
||||
cert_header_sa6@180000 {
|
||||
reg = <0x00180000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
bl31@1c0000 {
|
||||
reg = <0x001c0000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
tee@200000 {
|
||||
reg = <0x00200000 0x440000>;
|
||||
read-only;
|
||||
};
|
||||
uboot@640000 {
|
||||
reg = <0x00640000 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
dtb@740000 {
|
||||
reg = <0x00740000 0x080000>;
|
||||
};
|
||||
kernel@7c0000 {
|
||||
reg = <0x007c0000 0x1400000>;
|
||||
};
|
||||
user@1bc0000 {
|
||||
reg = <0x01bc0000 0x2440000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rwdt {
|
||||
timeout-sec = <60>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
pinctrl-0 = <&scif2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
/* used for on-board eMMC */
|
||||
pinctrl-0 = <&sdhi2_pins>;
|
||||
pinctrl-1 = <&sdhi2_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_1p8v>;
|
||||
bus-width = <8>;
|
||||
mmc-hs200-1_8v;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi4 {
|
||||
shared-pin;
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
renesas,no-otg-pins;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin4 {
|
||||
pinctrl-0 = <&vin4_pins_cvbs>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port {
|
||||
vin4_in: endpoint {
|
||||
remote-endpoint = <&adv7180_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
869
arch/arm/dts/ebisu.dtsi
Normal file
869
arch/arm/dts/ebisu.dtsi
Normal file
|
|
@ -0,0 +1,869 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the Ebisu board
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Renesas Ebisu board";
|
||||
compatible = "renesas,ebisu";
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
i2c5 = &i2c5;
|
||||
i2c6 = &i2c6;
|
||||
i2c7 = &i2c7;
|
||||
serial0 = &scif2;
|
||||
ethernet0 = &avb;
|
||||
mmc0 = &sdhi3;
|
||||
mmc1 = &sdhi0;
|
||||
mmc2 = &sdhi1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
audio_clkout: audio-clkout {
|
||||
/*
|
||||
* This is same as <&rcar_sound 0>
|
||||
* but needed to avoid cs2000/rcar_sound probe dead-lock
|
||||
*/
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <11289600>;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm3 0 50000>;
|
||||
|
||||
brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
|
||||
default-brightness-level = <10>;
|
||||
|
||||
power-supply = <®_12p0v>;
|
||||
};
|
||||
|
||||
cvbs-in {
|
||||
compatible = "composite-video-connector";
|
||||
label = "CVBS IN";
|
||||
|
||||
port {
|
||||
cvbs_con: endpoint {
|
||||
remote-endpoint = <&adv7482_ain7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-in {
|
||||
compatible = "hdmi-connector";
|
||||
label = "HDMI IN";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_in_con: endpoint {
|
||||
remote-endpoint = <&adv7482_hdmi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_out: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&keys_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
key-1 {
|
||||
gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_1>;
|
||||
label = "SW4-1";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-2 {
|
||||
gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_2>;
|
||||
label = "SW4-2";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-3 {
|
||||
gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_3>;
|
||||
label = "SW4-3";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
key-4 {
|
||||
gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_4>;
|
||||
label = "SW4-4";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
};
|
||||
|
||||
lvds-decoder {
|
||||
compatible = "thine,thc63lvd1024";
|
||||
vcc-supply = <®_3p3v>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
thc63lvd1024_in: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
thc63lvd1024_out: endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x38000000>;
|
||||
};
|
||||
|
||||
reg_1p8v: regulator-1p8v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_12p0v: regulator-12p0v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "D12.0V";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
rsnd_ak4613: sound {
|
||||
compatible = "simple-audio-card";
|
||||
|
||||
simple-audio-card,name = "rsnd-ak4613";
|
||||
simple-audio-card,format = "left_j";
|
||||
simple-audio-card,bitclock-master = <&sndcpu>;
|
||||
simple-audio-card,frame-master = <&sndcpu>;
|
||||
|
||||
sndcodec: simple-audio-card,codec {
|
||||
sound-dai = <&ak4613>;
|
||||
};
|
||||
|
||||
sndcpu: simple-audio-card,cpu {
|
||||
sound-dai = <&rcar_sound>;
|
||||
};
|
||||
};
|
||||
|
||||
vbus0_usb2: regulator-vbus0-usb2 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "USB20_VBUS_CN";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
|
||||
gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI0 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI0 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1>, <1800000 0>;
|
||||
};
|
||||
|
||||
vcc_sdhi1: regulator-vcc-sdhi1 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI1 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi1: regulator-vccq-sdhi1 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI1 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1>, <1800000 0>;
|
||||
};
|
||||
|
||||
vga {
|
||||
compatible = "vga-connector";
|
||||
|
||||
port {
|
||||
vga_in: endpoint {
|
||||
remote-endpoint = <&adv7123_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vga-encoder {
|
||||
compatible = "adi,adv7123";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7123_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7123_out: endpoint {
|
||||
remote-endpoint = <&vga_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
x12_clk: x12 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24576000>;
|
||||
};
|
||||
|
||||
x13_clk: x13 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <74250000>;
|
||||
};
|
||||
};
|
||||
|
||||
&audio_clk_a {
|
||||
clock-frequency = <22579200>;
|
||||
};
|
||||
|
||||
&avb {
|
||||
pinctrl-0 = <&avb_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-handle = <&phy0>;
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id0022.1622",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
rxc-skew-ps = <1500>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
|
||||
/*
|
||||
* TX clock internal delay mode is required for reliable
|
||||
* 1Gbps communication using the KSZ9031RNX phy present on
|
||||
* the Ebisu board, however, TX clock internal delay mode
|
||||
* isn't supported on R-Car E3(e). Thus, limit speed to
|
||||
* 100Mbps for reliable communication.
|
||||
*/
|
||||
max-speed = <100>;
|
||||
};
|
||||
};
|
||||
|
||||
&canfd {
|
||||
pinctrl-0 = <&canfd0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
channel0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&csi40 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
csi40_in: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
remote-endpoint = <&adv7482_txa>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&x13_clk>;
|
||||
clock-names = "du.0", "du.1", "dclkin.0";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
du_out_rgb: endpoint {
|
||||
remote-endpoint = <&adv7123_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
&hsusb {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
io_expander: gpio@20 {
|
||||
compatible = "onnn,pca9654";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
hdmi-encoder@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
video-receiver@70 {
|
||||
compatible = "adi,adv7482";
|
||||
reg = <0x70>;
|
||||
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupt-names = "intrq1", "intrq2";
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_LOW>,
|
||||
<17 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@7 {
|
||||
reg = <7>;
|
||||
|
||||
adv7482_ain7: endpoint {
|
||||
remote-endpoint = <&cvbs_con>;
|
||||
};
|
||||
};
|
||||
|
||||
port@8 {
|
||||
reg = <8>;
|
||||
|
||||
adv7482_hdmi: endpoint {
|
||||
remote-endpoint = <&hdmi_in_con>;
|
||||
};
|
||||
};
|
||||
|
||||
port@a {
|
||||
reg = <10>;
|
||||
|
||||
adv7482_txa: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
remote-endpoint = <&csi40_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
|
||||
ak4613: codec@10 {
|
||||
compatible = "asahi-kasei,ak4613";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x10>;
|
||||
clocks = <&rcar_sound 3>;
|
||||
|
||||
asahi-kasei,in1-single-end;
|
||||
asahi-kasei,in2-single-end;
|
||||
asahi-kasei,out1-single-end;
|
||||
asahi-kasei,out2-single-end;
|
||||
asahi-kasei,out3-single-end;
|
||||
asahi-kasei,out4-single-end;
|
||||
asahi-kasei,out5-single-end;
|
||||
asahi-kasei,out6-single-end;
|
||||
};
|
||||
|
||||
cs2000: clk-multiplier@4f {
|
||||
#clock-cells = <0>;
|
||||
compatible = "cirrus,cs2000-cp";
|
||||
reg = <0x4f>;
|
||||
clocks = <&audio_clkout>, <&x12_clk>;
|
||||
clock-names = "clk_in", "ref_clk";
|
||||
|
||||
assigned-clocks = <&cs2000>;
|
||||
assigned-clock-rates = <24576000>; /* 1/1 divide */
|
||||
};
|
||||
};
|
||||
|
||||
&i2c_dvfs {
|
||||
status = "okay";
|
||||
|
||||
clock-frequency = <400000>;
|
||||
|
||||
pmic: pmic@30 {
|
||||
pinctrl-0 = <&irq0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
compatible = "rohm,bd9571mwv";
|
||||
reg = <0x30>;
|
||||
interrupt-parent = <&intc_ex>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
rohm,ddr-backup-power = <0x1>;
|
||||
rohm,rstbmode-level;
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "rohm,br24t01", "atmel,24c01";
|
||||
reg = <0x50>;
|
||||
pagesize = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
&lvds0 {
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 727>,
|
||||
<&x13_clk>,
|
||||
<&extal_clk>;
|
||||
clock-names = "fck", "dclkin.0", "extal";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lvds1 {
|
||||
/*
|
||||
* Even though the LVDS1 output is not connected, the encoder must be
|
||||
* enabled to supply a pixel clock to the DU for the DPAD output when
|
||||
* LVDS0 is in use.
|
||||
*/
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 727>,
|
||||
<&x13_clk>,
|
||||
<&extal_clk>;
|
||||
clock-names = "fck", "dclkin.0", "extal";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_bus_clk {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&pciec0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pfc {
|
||||
avb_pins: avb {
|
||||
groups = "avb_link", "avb_mii";
|
||||
function = "avb";
|
||||
};
|
||||
|
||||
canfd0_pins: canfd0 {
|
||||
groups = "canfd0_data";
|
||||
function = "canfd0";
|
||||
};
|
||||
|
||||
du_pins: du {
|
||||
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
|
||||
function = "du";
|
||||
};
|
||||
|
||||
irq0_pins: irq0 {
|
||||
groups = "intc_ex_irq0";
|
||||
function = "intc_ex";
|
||||
};
|
||||
|
||||
keys_pins: keys {
|
||||
pins = "GP_5_10", "GP_5_11", "GP_5_12", "GP_5_13";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pwm3_pins: pwm3 {
|
||||
groups = "pwm3_b";
|
||||
function = "pwm3";
|
||||
};
|
||||
|
||||
pwm5_pins: pwm5 {
|
||||
groups = "pwm5_a";
|
||||
function = "pwm5";
|
||||
};
|
||||
|
||||
rpc_pins: rpc {
|
||||
groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset",
|
||||
"rpc_int";
|
||||
function = "rpc";
|
||||
};
|
||||
|
||||
scif2_pins: scif2 {
|
||||
groups = "scif2_data_a";
|
||||
function = "scif2";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi0_pins_uhs: sd0_uhs {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi1_pins: sd1 {
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi1_pins_uhs: sd1_uhs {
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi3_pins: sd3 {
|
||||
groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
|
||||
function = "sdhi3";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sound_clk_pins: sound_clk {
|
||||
groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a",
|
||||
"audio_clkout_a", "audio_clkout1_a";
|
||||
function = "audio_clk";
|
||||
};
|
||||
|
||||
sound_pins: sound {
|
||||
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
|
||||
function = "ssi";
|
||||
};
|
||||
|
||||
usb0_pins: usb {
|
||||
groups = "usb0_b", "usb0_id";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
usb30_pins: usb30 {
|
||||
groups = "usb30";
|
||||
function = "usb30";
|
||||
};
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
pinctrl-0 = <&pwm3_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm5 {
|
||||
pinctrl-0 = <&pwm5_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* Single DAI */
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
/* audio_clkout0/1/2/3 */
|
||||
#clock-cells = <1>;
|
||||
clock-frequency = <12288000 11289600>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
/* update <audio_clk_b> to <cs2000> */
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
|
||||
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
|
||||
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
|
||||
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
|
||||
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
|
||||
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
|
||||
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
|
||||
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
|
||||
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
|
||||
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
|
||||
<&audio_clk_a>, <&cs2000>, <&audio_clk_c>,
|
||||
<&cpg CPG_CORE R8A77990_CLK_ZA2>;
|
||||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0>, <&src0>, <&dvc0>;
|
||||
capture = <&ssi1>, <&src1>, <&dvc1>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&rpc {
|
||||
pinctrl-0 = <&rpc_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* Left disabled. To be enabled by firmware when unlocked. */
|
||||
|
||||
flash@0 {
|
||||
compatible = "cypress,hyperflash", "cfi-flash";
|
||||
reg = <0>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
bootparam@0 {
|
||||
reg = <0x00000000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
bl2@40000 {
|
||||
reg = <0x00040000 0x140000>;
|
||||
read-only;
|
||||
};
|
||||
cert_header_sa6@180000 {
|
||||
reg = <0x00180000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
bl31@1c0000 {
|
||||
reg = <0x001c0000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
tee@200000 {
|
||||
reg = <0x00200000 0x440000>;
|
||||
read-only;
|
||||
};
|
||||
uboot@640000 {
|
||||
reg = <0x00640000 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
dtb@740000 {
|
||||
reg = <0x00740000 0x080000>;
|
||||
};
|
||||
kernel@7c0000 {
|
||||
reg = <0x007c0000 0x1400000>;
|
||||
};
|
||||
user@1bc0000 {
|
||||
reg = <0x01bc0000 0x2440000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rwdt {
|
||||
timeout-sec = <60>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
pinctrl-0 = <&scif2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-1 = <&sdhi0_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi1 {
|
||||
pinctrl-0 = <&sdhi1_pins>;
|
||||
pinctrl-1 = <&sdhi1_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi1>;
|
||||
vqmmc-supply = <&vccq_sdhi1>;
|
||||
cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi3 {
|
||||
/* used for on-board 8bit eMMC */
|
||||
pinctrl-0 = <&sdhi3_pins>;
|
||||
pinctrl-1 = <&sdhi3_pins>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_1p8v>;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
bus-width = <8>;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
non-removable;
|
||||
full-pwr-cycle-in-suspend;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
shared-pin;
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vbus-supply = <&vbus0_usb2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_peri0 {
|
||||
companion = <&xhci0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xhci0 {
|
||||
pinctrl-0 = <&usb30_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
* Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
|
||||
* HiHope RZ/G2[MN] Rev.3.0/4.0 main board common parts
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
|
@ -80,7 +80,7 @@
|
|||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_pins &sound_clk_pins>;
|
||||
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -91,7 +91,11 @@
|
|||
#clock-cells = <1>;
|
||||
clock-frequency = <12288000 11289600>;
|
||||
|
||||
/* update <audio_clk_b> to <cs2000> */
|
||||
/*
|
||||
* Update <audio_clk_b> to <cs2000>
|
||||
* Switch SW2404 should be at position 1 so that clock from
|
||||
* CS2000 is connected to AUDIO_CLKB_A
|
||||
*/
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
|
||||
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* Device Tree Source for the RZ/G2[HMN] HiHope sub board common parts
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
* Copyright (C) 2019 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
/ {
|
||||
|
|
@ -19,10 +19,13 @@
|
|||
pinctrl-0 = <&avb_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-txid";
|
||||
tx-internal-delay-ps = <2000>;
|
||||
rx-internal-delay-ps = <1800>;
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id001c.c915",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
|
|
|||
|
|
@ -14,6 +14,14 @@
|
|||
compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1";
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
i2c5 = &i2c5;
|
||||
i2c6 = &i2c6;
|
||||
i2c7 = &iic_pmic;
|
||||
serial0 = &scif2;
|
||||
serial1 = &hscif0;
|
||||
serial2 = &hscif1;
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 connected to
|
||||
* sub board
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include "r8a774a1-hihope-rzg2m.dts"
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 main board
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
|
|||
|
|
@ -17,17 +17,6 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
i2c5 = &i2c5;
|
||||
i2c6 = &i2c6;
|
||||
i2c7 = &i2c_dvfs;
|
||||
};
|
||||
|
||||
/*
|
||||
* The external audio clocks are configured as 0 Hz fixed frequency
|
||||
* clocks by default.
|
||||
|
|
@ -58,7 +47,7 @@
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cluster0_opp: opp_table0 {
|
||||
cluster0_opp: opp-table-0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
|
|
@ -76,10 +65,11 @@
|
|||
opp-hz = /bits/ 64 <1500000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
opp-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1_opp: opp_table1 {
|
||||
cluster1_opp: opp-table-1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
|
|
@ -282,6 +272,7 @@
|
|||
compatible = "renesas,r8a774a1-wdt",
|
||||
"renesas,rcar-gen3-wdt";
|
||||
reg = <0 0xe6020000 0 0x0c>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 402>;
|
||||
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 402>;
|
||||
|
|
@ -714,7 +705,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c_dvfs: i2c@e60b0000 {
|
||||
iic_pmic: i2c@e60b0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,iic-r8a774a1",
|
||||
|
|
@ -1127,6 +1118,7 @@
|
|||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii";
|
||||
|
|
@ -1176,6 +1168,7 @@
|
|||
reg = <0 0xe66c0000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch_int", "g_int";
|
||||
clocks = <&cpg CPG_MOD 914>,
|
||||
<&cpg CPG_CORE R8A774A1_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
|
|
@ -1696,12 +1689,12 @@
|
|||
* clkout : #clock-cells = <0>; <&rcar_sound>;
|
||||
* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
|
||||
*/
|
||||
compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3";
|
||||
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
||||
<0 0xec5a0000 0 0x100>, /* ADG */
|
||||
<0 0xec540000 0 0x1000>, /* SSIU */
|
||||
<0 0xec541000 0 0x280>, /* SSI */
|
||||
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
|
||||
compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3";
|
||||
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
||||
<0 0xec5a0000 0 0x100>, /* ADG */
|
||||
<0 0xec540000 0 0x1000>, /* SSIU */
|
||||
<0 0xec541000 0 0x280>, /* SSI */
|
||||
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
|
||||
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
|
||||
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
|
|
@ -2008,7 +2001,7 @@
|
|||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu40: ssiu-32 {
|
||||
dmas = <&audma0 0x71>, <&audma1 0x72>;
|
||||
dmas = <&audma0 0x71>, <&audma1 0x72>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu41: ssiu-33 {
|
||||
|
|
@ -2274,7 +2267,8 @@
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee100000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774A1_CLK_SD0H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
|
|
@ -2286,7 +2280,8 @@
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee120000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 313>;
|
||||
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774A1_CLK_SD1H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 313>;
|
||||
|
|
@ -2298,7 +2293,8 @@
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774A1_CLK_SD2H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 312>;
|
||||
|
|
@ -2310,7 +2306,8 @@
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee160000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 311>;
|
||||
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774A1_CLK_SD3H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 311>;
|
||||
|
|
@ -2326,7 +2323,6 @@
|
|||
reg-names = "regs", "dirmap", "wbuf";
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
clock-names = "rpc";
|
||||
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -2573,6 +2569,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -2628,6 +2628,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -2723,8 +2727,6 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb: endpoint {
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
|
@ -2761,8 +2763,6 @@
|
|||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -2774,7 +2774,7 @@
|
|||
};
|
||||
|
||||
thermal-zones {
|
||||
sensor_thermal1: sensor-thermal1 {
|
||||
sensor1_thermal: sensor1-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 0>;
|
||||
|
|
@ -2789,7 +2789,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
sensor_thermal2: sensor-thermal2 {
|
||||
sensor2_thermal: sensor2-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 1>;
|
||||
|
|
@ -2804,7 +2804,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
sensor_thermal3: sensor-thermal3 {
|
||||
sensor3_thermal: sensor3-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 2>;
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
|
||||
/ {
|
||||
model = "Beacon Embedded Works RZ/G2N Development Kit";
|
||||
compatible = "beacon,beacon-rzg2n", "renesas,r8a774b1";
|
||||
compatible = "beacon,beacon-rzg2n", "renesas,r8a774b1";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif2;
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cluster0_opp: opp_table0 {
|
||||
cluster0_opp: opp-table-0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
|
|
@ -156,6 +156,7 @@
|
|||
compatible = "renesas,r8a774b1-wdt",
|
||||
"renesas,rcar-gen3-wdt";
|
||||
reg = <0 0xe6020000 0 0x0c>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 402>;
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 402>;
|
||||
|
|
@ -588,7 +589,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c_dvfs: i2c@e60b0000 {
|
||||
iic_pmic: i2c@e60b0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,iic-r8a774b1",
|
||||
|
|
@ -1001,6 +1002,7 @@
|
|||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii";
|
||||
|
|
@ -1050,6 +1052,7 @@
|
|||
reg = <0 0xe66c0000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch_int", "g_int";
|
||||
clocks = <&cpg CPG_MOD 914>,
|
||||
<&cpg CPG_CORE R8A774B1_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
|
|
@ -1570,7 +1573,7 @@
|
|||
* clkout : #clock-cells = <0>; <&rcar_sound>;
|
||||
* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
|
||||
*/
|
||||
compatible = "renesas,rcar_sound-r8a774b1", "renesas,rcar_sound-gen3";
|
||||
compatible = "renesas,rcar_sound-r8a774b1", "renesas,rcar_sound-gen3";
|
||||
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
||||
<0 0xec5a0000 0 0x100>, /* ADG */
|
||||
<0 0xec540000 0 0x1000>, /* SSIU */
|
||||
|
|
@ -1882,7 +1885,7 @@
|
|||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu40: ssiu-32 {
|
||||
dmas = <&audma0 0x71>, <&audma1 0x72>;
|
||||
dmas = <&audma0 0x71>, <&audma1 0x72>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu41: ssiu-33 {
|
||||
|
|
@ -2132,7 +2135,8 @@
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee100000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774B1_CLK_SD0H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
|
|
@ -2144,7 +2148,8 @@
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee120000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 313>;
|
||||
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774B1_CLK_SD1H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 313>;
|
||||
|
|
@ -2156,7 +2161,8 @@
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774B1_CLK_SD2H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 312>;
|
||||
|
|
@ -2168,7 +2174,8 @@
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee160000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 311>;
|
||||
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774B1_CLK_SD3H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 311>;
|
||||
|
|
@ -2184,7 +2191,6 @@
|
|||
reg-names = "regs", "dirmap", "wbuf";
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
clock-names = "rpc";
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -2419,6 +2425,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -2474,6 +2484,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -2569,8 +2583,6 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb: endpoint {
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
|
@ -2607,8 +2619,6 @@
|
|||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -2620,7 +2630,7 @@
|
|||
};
|
||||
|
||||
thermal-zones {
|
||||
sensor_thermal1: sensor-thermal1 {
|
||||
sensor1_thermal: sensor1-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 0>;
|
||||
|
|
@ -2635,7 +2645,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
sensor_thermal2: sensor-thermal2 {
|
||||
sensor2_thermal: sensor2-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 1>;
|
||||
|
|
@ -2650,7 +2660,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
sensor_thermal3: sensor-thermal3 {
|
||||
sensor3_thermal: sensor3-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 2>;
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874)
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
* Copyright (C) 2019 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
@ -17,6 +17,8 @@
|
|||
aliases {
|
||||
serial0 = &scif2;
|
||||
serial1 = &hscif2;
|
||||
mmc0 = &sdhi0;
|
||||
mmc1 = &sdhi3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
|
@ -170,7 +172,7 @@
|
|||
|
||||
ports {
|
||||
port@0 {
|
||||
endpoint {
|
||||
du_out_rgb: endpoint {
|
||||
remote-endpoint = <&tda19988_in>;
|
||||
};
|
||||
};
|
||||
|
|
@ -351,7 +353,7 @@
|
|||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_pins &sound_clk_pins>;
|
||||
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* Single DAI */
|
||||
|
|
@ -365,7 +367,7 @@
|
|||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0 &src0 &dvc0>;
|
||||
playback = <&ssi0>, <&src0>, <&dvc0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* Device Tree Source for the Silicon Linux RZ/G2E evaluation kit (EK874)
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
* Copyright (C) 2019 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include "r8a774c0-cat874.dts"
|
||||
|
|
|
|||
|
|
@ -35,7 +35,6 @@
|
|||
/delete-node/ &rcar_sound;
|
||||
/delete-node/ &audma0;
|
||||
/delete-node/ &sdhi1;
|
||||
/delete-node/ &sdhi3;
|
||||
/delete-node/ &vspb0;
|
||||
/delete-node/ &vspd0;
|
||||
/delete-node/ &vspd1;
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* Device Tree Source for the RZ/G2E (R8A774C0) SoC
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
* Copyright (C) 2018-2019 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
|
||||
|
|
@ -44,7 +44,7 @@
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cluster1_opp: opp_table10 {
|
||||
cluster1_opp: opp-table-1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
opp-800000000 {
|
||||
|
|
@ -145,6 +145,7 @@
|
|||
compatible = "renesas,r8a774c0-wdt",
|
||||
"renesas,rcar-gen3-wdt";
|
||||
reg = <0 0xe6020000 0 0x0c>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 402>;
|
||||
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 402>;
|
||||
|
|
@ -574,11 +575,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c_dvfs: i2c@e60b0000 {
|
||||
iic_pmic: i2c@e60b0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,iic-r8a774c0";
|
||||
reg = <0 0xe60b0000 0 0x15>;
|
||||
compatible = "renesas,iic-r8a774c0",
|
||||
"renesas,rcar-gen3-iic",
|
||||
"renesas,rmobile-iic";
|
||||
reg = <0 0xe60b0000 0 0x425>;
|
||||
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 926>;
|
||||
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
|
||||
|
|
@ -957,6 +960,7 @@
|
|||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii";
|
||||
|
|
@ -1005,6 +1009,7 @@
|
|||
reg = <0 0xe66c0000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch_int", "g_int";
|
||||
clocks = <&cpg CPG_MOD 914>,
|
||||
<&cpg CPG_CORE R8A774C0_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
|
|
@ -1276,7 +1281,7 @@
|
|||
|
||||
vin4csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin4>;
|
||||
remote-endpoint = <&csi40vin4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1304,7 +1309,7 @@
|
|||
|
||||
vin5csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin5>;
|
||||
remote-endpoint = <&csi40vin5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1325,11 +1330,11 @@
|
|||
*/
|
||||
compatible = "renesas,rcar_sound-r8a774c0",
|
||||
"renesas,rcar_sound-gen3";
|
||||
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
||||
<0 0xec5a0000 0 0x100>, /* ADG */
|
||||
<0 0xec540000 0 0x1000>, /* SSIU */
|
||||
<0 0xec541000 0 0x280>, /* SSI */
|
||||
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
|
||||
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
||||
<0 0xec5a0000 0 0x100>, /* ADG */
|
||||
<0 0xec540000 0 0x1000>, /* SSIU */
|
||||
<0 0xec541000 0 0x280>, /* SSI */
|
||||
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
|
||||
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
|
||||
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
|
|
@ -1623,7 +1628,8 @@
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee100000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774C0_CLK_SD0H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
|
|
@ -1635,7 +1641,8 @@
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee120000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 313>;
|
||||
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774C0_CLK_SD1H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 313>;
|
||||
|
|
@ -1647,13 +1654,30 @@
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee160000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 311>;
|
||||
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774C0_CLK_SD3H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 311>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rpc: spi@ee200000 {
|
||||
compatible = "renesas,r8a774c0-rpc-if",
|
||||
"renesas,rcar-gen3-rpc-if";
|
||||
reg = <0 0xee200000 0 0x200>,
|
||||
<0 0x08000000 0 0x4000000>,
|
||||
<0 0xee208000 0 0x100>;
|
||||
reg-names = "regs", "dirmap", "wbuf";
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
@ -1806,6 +1830,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -1843,8 +1871,6 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
|
|
@ -1886,8 +1912,6 @@
|
|||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1913,8 +1937,6 @@
|
|||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds1_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1929,7 +1951,7 @@
|
|||
cpu-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&thermal 0>;
|
||||
thermal-sensors = <&thermal>;
|
||||
sustainable-power = <717>;
|
||||
|
||||
cooling-maps {
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
|
||||
/ {
|
||||
model = "Beacon Embedded Works RZ/G2H Development Kit";
|
||||
compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1";
|
||||
compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif2;
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cluster0_opp: opp_table0 {
|
||||
cluster0_opp: opp-table-0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
|
|
@ -69,7 +69,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
cluster1_opp: opp_table1 {
|
||||
cluster1_opp: opp-table-1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
|
|
@ -769,7 +769,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c_dvfs: i2c@e60b0000 {
|
||||
iic_pmic: i2c@e60b0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,iic-r8a774e1",
|
||||
|
|
@ -1230,6 +1230,7 @@
|
|||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii";
|
||||
|
|
@ -1279,6 +1280,7 @@
|
|||
reg = <0 0xe66c0000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch_int", "g_int";
|
||||
clocks = <&cpg CPG_MOD 914>,
|
||||
<&cpg CPG_CORE R8A774E1_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
|
|
@ -1783,7 +1785,7 @@
|
|||
* clkout : #clock-cells = <0>; <&rcar_sound>;
|
||||
* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
|
||||
*/
|
||||
compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3";
|
||||
compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3";
|
||||
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
||||
<0 0xec5a0000 0 0x100>, /* ADG */
|
||||
<0 0xec540000 0 0x1000>, /* SSIU */
|
||||
|
|
@ -2042,7 +2044,7 @@
|
|||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu40: ssiu-32 {
|
||||
dmas = <&audma0 0x71>, <&audma1 0x72>;
|
||||
dmas = <&audma0 0x71>, <&audma1 0x72>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu41: ssiu-33 {
|
||||
|
|
@ -2361,7 +2363,8 @@
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee100000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774E1_CLK_SD0H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
|
|
@ -2374,7 +2377,8 @@
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee120000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 313>;
|
||||
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774E1_CLK_SD1H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 313>;
|
||||
|
|
@ -2387,7 +2391,8 @@
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774E1_CLK_SD2H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 312>;
|
||||
|
|
@ -2400,7 +2405,8 @@
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee160000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 311>;
|
||||
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774E1_CLK_SD3H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 311>;
|
||||
|
|
@ -2417,7 +2423,6 @@
|
|||
reg-names = "regs", "dirmap", "wbuf";
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
clock-names = "rpc";
|
||||
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -2709,6 +2714,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -2764,6 +2773,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -2844,8 +2857,6 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb: endpoint {
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
|
@ -2882,8 +2893,6 @@
|
|||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -2895,7 +2904,7 @@
|
|||
};
|
||||
|
||||
thermal-zones {
|
||||
sensor_thermal1: sensor-thermal1 {
|
||||
sensor1_thermal: sensor1-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 0>;
|
||||
|
|
@ -2910,7 +2919,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
sensor_thermal2: sensor-thermal2 {
|
||||
sensor2_thermal: sensor2-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 1>;
|
||||
|
|
@ -2925,7 +2934,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
sensor_thermal3: sensor-thermal3 {
|
||||
sensor3_thermal: sensor3-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 2>;
|
||||
|
|
|
|||
|
|
@ -53,6 +53,9 @@
|
|||
i2c11 = &i2cexio1;
|
||||
i2c12 = &i2chdmi;
|
||||
i2c13 = &i2cpwr;
|
||||
mmc0 = &mmcif1;
|
||||
mmc1 = &sdhi0;
|
||||
mmc2 = &sdhi2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
|
@ -78,6 +81,9 @@
|
|||
keyboard {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&keyboard_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
one {
|
||||
linux,code = <KEY_1>;
|
||||
label = "SW2-1";
|
||||
|
|
@ -343,7 +349,6 @@
|
|||
composite-in@20 {
|
||||
compatible = "adi,adv7180";
|
||||
reg = <0x20>;
|
||||
remote = <&vin1>;
|
||||
|
||||
port {
|
||||
adv7180: endpoint {
|
||||
|
|
@ -364,8 +369,6 @@
|
|||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -439,7 +442,7 @@
|
|||
compatible = "dlg,da9063-rtc";
|
||||
};
|
||||
|
||||
wdt {
|
||||
watchdog {
|
||||
compatible = "dlg,da9063-watchdog";
|
||||
};
|
||||
};
|
||||
|
|
@ -659,10 +662,15 @@
|
|||
groups = "audio_clk_a";
|
||||
function = "audio_clk";
|
||||
};
|
||||
|
||||
keyboard_pins: keyboard {
|
||||
pins = "GP_1_14", "GP_1_24", "GP_1_26", "GP_1_28";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-0 = <ðer_pins>, <&phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
|
|
@ -670,10 +678,13 @@
|
|||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-id0022.1537",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
micrel,led-mode = <1>;
|
||||
reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -910,7 +921,7 @@
|
|||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_pins &sound_clk_pins>;
|
||||
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* Single DAI */
|
||||
|
|
@ -920,8 +931,8 @@
|
|||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0 &src2 &dvc0>;
|
||||
capture = <&ssi1 &src3 &dvc1>;
|
||||
playback = <&ssi0>, <&src2>, <&dvc0>;
|
||||
capture = <&ssi1>, <&src3>, <&dvc1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -191,7 +191,7 @@
|
|||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-0 = <ðer_pins>, <&phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
|
|
@ -199,10 +199,13 @@
|
|||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-id0022.1537",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
|
||||
micrel,led-mode = <1>;
|
||||
reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -296,8 +299,6 @@
|
|||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -322,7 +323,7 @@
|
|||
|
||||
&iic3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&iic3_pins &pmic_irq_pins>;
|
||||
pinctrl-0 = <&iic3_pins>, <&pmic_irq_pins>;
|
||||
status = "okay";
|
||||
|
||||
pmic@58 {
|
||||
|
|
@ -340,7 +341,7 @@
|
|||
compatible = "dlg,da9063-rtc";
|
||||
};
|
||||
|
||||
wdt {
|
||||
watchdog {
|
||||
compatible = "dlg,da9063-watchdog";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -69,7 +69,6 @@
|
|||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "renesas,apmu";
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
|
|
@ -78,6 +77,7 @@
|
|||
clock-frequency = <1300000000>;
|
||||
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
|
||||
power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
|
||||
enable-method = "renesas,apmu";
|
||||
next-level-cache = <&L2_CA15>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
voltage-tolerance = <1>; /* 1% */
|
||||
|
|
@ -99,6 +99,7 @@
|
|||
clock-frequency = <1300000000>;
|
||||
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
|
||||
power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
|
||||
enable-method = "renesas,apmu";
|
||||
next-level-cache = <&L2_CA15>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
voltage-tolerance = <1>; /* 1% */
|
||||
|
|
@ -120,6 +121,7 @@
|
|||
clock-frequency = <1300000000>;
|
||||
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
|
||||
power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
|
||||
enable-method = "renesas,apmu";
|
||||
next-level-cache = <&L2_CA15>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
voltage-tolerance = <1>; /* 1% */
|
||||
|
|
@ -141,6 +143,7 @@
|
|||
clock-frequency = <1300000000>;
|
||||
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
|
||||
power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
|
||||
enable-method = "renesas,apmu";
|
||||
next-level-cache = <&L2_CA15>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
voltage-tolerance = <1>; /* 1% */
|
||||
|
|
@ -162,6 +165,7 @@
|
|||
clock-frequency = <780000000>;
|
||||
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
|
||||
power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
|
||||
enable-method = "renesas,apmu";
|
||||
next-level-cache = <&L2_CA7>;
|
||||
capacity-dmips-mhz = <539>;
|
||||
};
|
||||
|
|
@ -173,6 +177,7 @@
|
|||
clock-frequency = <780000000>;
|
||||
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
|
||||
power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
|
||||
enable-method = "renesas,apmu";
|
||||
next-level-cache = <&L2_CA7>;
|
||||
capacity-dmips-mhz = <539>;
|
||||
};
|
||||
|
|
@ -184,6 +189,7 @@
|
|||
clock-frequency = <780000000>;
|
||||
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
|
||||
power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
|
||||
enable-method = "renesas,apmu";
|
||||
next-level-cache = <&L2_CA7>;
|
||||
capacity-dmips-mhz = <539>;
|
||||
};
|
||||
|
|
@ -195,6 +201,7 @@
|
|||
clock-frequency = <780000000>;
|
||||
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
|
||||
power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
|
||||
enable-method = "renesas,apmu";
|
||||
next-level-cache = <&L2_CA7>;
|
||||
capacity-dmips-mhz = <539>;
|
||||
};
|
||||
|
|
@ -267,6 +274,7 @@
|
|||
compatible = "renesas,r8a7790-wdt",
|
||||
"renesas,rcar-gen2-wdt";
|
||||
reg = <0 0xe6020000 0 0x0c>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 402>;
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 402>;
|
||||
|
|
@ -363,7 +371,7 @@
|
|||
resets = <&cpg 907>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
pfc: pinctrl@e6060000 {
|
||||
compatible = "renesas,pfc-r8a7790";
|
||||
reg = <0 0xe6060000 0 0x250>;
|
||||
};
|
||||
|
|
@ -381,13 +389,13 @@
|
|||
apmu@e6151000 {
|
||||
compatible = "renesas,r8a7790-apmu", "renesas,apmu";
|
||||
reg = <0 0xe6151000 0 0x188>;
|
||||
cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
|
||||
cpus = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
|
||||
};
|
||||
|
||||
apmu@e6152000 {
|
||||
compatible = "renesas,r8a7790-apmu", "renesas,apmu";
|
||||
reg = <0 0xe6152000 0 0x188>;
|
||||
cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
|
||||
cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
|
|
@ -427,7 +435,7 @@
|
|||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
ipmmu_sy0: mmu@e6280000 {
|
||||
ipmmu_sy0: iommu@e6280000 {
|
||||
compatible = "renesas,ipmmu-r8a7790",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xe6280000 0 0x1000>;
|
||||
|
|
@ -437,7 +445,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_sy1: mmu@e6290000 {
|
||||
ipmmu_sy1: iommu@e6290000 {
|
||||
compatible = "renesas,ipmmu-r8a7790",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xe6290000 0 0x1000>;
|
||||
|
|
@ -446,7 +454,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_ds: mmu@e6740000 {
|
||||
ipmmu_ds: iommu@e6740000 {
|
||||
compatible = "renesas,ipmmu-r8a7790",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xe6740000 0 0x1000>;
|
||||
|
|
@ -456,7 +464,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_mp: mmu@ec680000 {
|
||||
ipmmu_mp: iommu@ec680000 {
|
||||
compatible = "renesas,ipmmu-r8a7790",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xec680000 0 0x1000>;
|
||||
|
|
@ -465,7 +473,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_mx: mmu@fe951000 {
|
||||
ipmmu_mx: iommu@fe951000 {
|
||||
compatible = "renesas,ipmmu-r8a7790",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xfe951000 0 0x1000>;
|
||||
|
|
@ -475,7 +483,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_rt: mmu@ffc80000 {
|
||||
ipmmu_rt: iommu@ffc80000 {
|
||||
compatible = "renesas,ipmmu-r8a7790",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xffc80000 0 0x1000>;
|
||||
|
|
@ -646,7 +654,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphy: usb-phy@e6590100 {
|
||||
usbphy: usb-phy-controller@e6590100 {
|
||||
compatible = "renesas,usb-phy-r8a7790",
|
||||
"renesas,rcar-gen2-usb-phy";
|
||||
reg = <0 0xe6590100 0 0x100>;
|
||||
|
|
@ -658,11 +666,11 @@
|
|||
resets = <&cpg 704>;
|
||||
status = "disabled";
|
||||
|
||||
usb0: usb-channel@0 {
|
||||
usb0: usb-phy@0 {
|
||||
reg = <0>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
usb2: usb-channel@2 {
|
||||
usb2: usb-phy@2 {
|
||||
reg = <2>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
|
@ -768,6 +776,7 @@
|
|||
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -1467,7 +1476,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
sdhi0: mmc@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a7790",
|
||||
"renesas,rcar-gen2-sdhi";
|
||||
reg = <0 0xee100000 0 0x328>;
|
||||
|
|
@ -1482,7 +1491,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi1: sd@ee120000 {
|
||||
sdhi1: mmc@ee120000 {
|
||||
compatible = "renesas,sdhi-r8a7790",
|
||||
"renesas,rcar-gen2-sdhi";
|
||||
reg = <0 0xee120000 0 0x328>;
|
||||
|
|
@ -1497,7 +1506,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi2: sd@ee140000 {
|
||||
sdhi2: mmc@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a7790",
|
||||
"renesas,rcar-gen2-sdhi";
|
||||
reg = <0 0xee140000 0 0x100>;
|
||||
|
|
@ -1512,7 +1521,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi3: sd@ee160000 {
|
||||
sdhi3: mmc@ee160000 {
|
||||
compatible = "renesas,sdhi-r8a7790",
|
||||
"renesas,rcar-gen2-sdhi";
|
||||
reg = <0 0xee160000 0 0x100>;
|
||||
|
|
@ -1719,6 +1728,8 @@
|
|||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>;
|
||||
clock-names = "du.0", "du.1", "du.2";
|
||||
resets = <&cpg 724>;
|
||||
reset-names = "du.0";
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
|
|
|
|||
|
|
@ -53,6 +53,9 @@
|
|||
i2c12 = &i2cexio1;
|
||||
i2c13 = &i2chdmi;
|
||||
i2c14 = &i2cexio4;
|
||||
mmc0 = &sdhi0;
|
||||
mmc1 = &sdhi1;
|
||||
mmc2 = &sdhi2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
|
@ -78,6 +81,9 @@
|
|||
keyboard {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&keyboard_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
key-1 {
|
||||
gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_1>;
|
||||
|
|
@ -366,7 +372,6 @@
|
|||
composite-in@20 {
|
||||
compatible = "adi,adv7180";
|
||||
reg = <0x20>;
|
||||
remote = <&vin1>;
|
||||
|
||||
port {
|
||||
adv7180: endpoint {
|
||||
|
|
@ -387,8 +392,6 @@
|
|||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -618,10 +621,15 @@
|
|||
groups = "audio_clk_a";
|
||||
function = "audio_clk";
|
||||
};
|
||||
|
||||
keyboard_pins: keyboard {
|
||||
pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-0 = <ðer_pins>, <&phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
|
|
@ -629,10 +637,13 @@
|
|||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-id0022.1537",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
micrel,led-mode = <1>;
|
||||
reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -794,7 +805,7 @@
|
|||
compatible = "dlg,da9063-rtc";
|
||||
};
|
||||
|
||||
wdt {
|
||||
watchdog {
|
||||
compatible = "dlg,da9063-watchdog";
|
||||
};
|
||||
};
|
||||
|
|
@ -880,7 +891,7 @@
|
|||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_pins &sound_clk_pins>;
|
||||
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* Single DAI */
|
||||
|
|
@ -890,8 +901,8 @@
|
|||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0 &src2 &dvc0>;
|
||||
capture = <&ssi1 &src3 &dvc1>;
|
||||
playback = <&ssi0>, <&src2>, <&dvc0>;
|
||||
capture = <&ssi1>, <&src3>, <&dvc1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -28,6 +28,8 @@
|
|||
serial0 = &scif0;
|
||||
i2c9 = &gpioi2c2;
|
||||
i2c10 = &i2chdmi;
|
||||
mmc0 = &sdhi0;
|
||||
mmc1 = &sdhi2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
|
@ -162,7 +164,6 @@
|
|||
composite-in@20 {
|
||||
compatible = "adi,adv7180";
|
||||
reg = <0x20>;
|
||||
remote = <&vin0>;
|
||||
|
||||
port {
|
||||
adv7180: endpoint {
|
||||
|
|
@ -181,8 +182,6 @@
|
|||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -295,7 +294,7 @@
|
|||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-0 = <ðer_pins>, <&phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
|
|
@ -303,10 +302,13 @@
|
|||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-id0022.1537",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
micrel,led-mode = <1>;
|
||||
reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -388,7 +390,7 @@
|
|||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-controller;
|
||||
|
||||
wdt {
|
||||
watchdog {
|
||||
compatible = "dlg,da9063-watchdog";
|
||||
};
|
||||
};
|
||||
|
|
@ -496,7 +498,7 @@
|
|||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&ssi_pins &audio_clk_pins>;
|
||||
pinctrl-0 = <&ssi_pins>, <&audio_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
|
|
|
|||
|
|
@ -68,7 +68,6 @@
|
|||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "renesas,apmu";
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
|
|
@ -77,6 +76,7 @@
|
|||
clock-frequency = <1500000000>;
|
||||
clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
|
||||
power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
|
||||
enable-method = "renesas,apmu";
|
||||
next-level-cache = <&L2_CA15>;
|
||||
voltage-tolerance = <1>; /* 1% */
|
||||
clock-latency = <300000>; /* 300 us */
|
||||
|
|
@ -97,6 +97,7 @@
|
|||
clock-frequency = <1500000000>;
|
||||
clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
|
||||
power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
|
||||
enable-method = "renesas,apmu";
|
||||
next-level-cache = <&L2_CA15>;
|
||||
voltage-tolerance = <1>; /* 1% */
|
||||
clock-latency = <300000>; /* 300 us */
|
||||
|
|
@ -160,6 +161,7 @@
|
|||
compatible = "renesas,r8a7791-wdt",
|
||||
"renesas,rcar-gen2-wdt";
|
||||
reg = <0 0xe6020000 0 0x0c>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 402>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 402>;
|
||||
|
|
@ -286,11 +288,22 @@
|
|||
resets = <&cpg 904>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
pfc: pinctrl@e6060000 {
|
||||
compatible = "renesas,pfc-r8a7791";
|
||||
reg = <0 0xe6060000 0 0x250>;
|
||||
};
|
||||
|
||||
tpu: pwm@e60f0000 {
|
||||
compatible = "renesas,tpu-r8a7791", "renesas,tpu";
|
||||
reg = <0 0xe60f0000 0 0x148>;
|
||||
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 304>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 304>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a7791-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
|
|
@ -304,7 +317,7 @@
|
|||
apmu@e6152000 {
|
||||
compatible = "renesas,r8a7791-apmu", "renesas,apmu";
|
||||
reg = <0 0xe6152000 0 0x188>;
|
||||
cpus = <&cpu0 &cpu1>;
|
||||
cpus = <&cpu0>, <&cpu1>;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
|
|
@ -350,7 +363,7 @@
|
|||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
ipmmu_sy0: mmu@e6280000 {
|
||||
ipmmu_sy0: iommu@e6280000 {
|
||||
compatible = "renesas,ipmmu-r8a7791",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xe6280000 0 0x1000>;
|
||||
|
|
@ -360,7 +373,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_sy1: mmu@e6290000 {
|
||||
ipmmu_sy1: iommu@e6290000 {
|
||||
compatible = "renesas,ipmmu-r8a7791",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xe6290000 0 0x1000>;
|
||||
|
|
@ -369,7 +382,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_ds: mmu@e6740000 {
|
||||
ipmmu_ds: iommu@e6740000 {
|
||||
compatible = "renesas,ipmmu-r8a7791",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xe6740000 0 0x1000>;
|
||||
|
|
@ -379,7 +392,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_mp: mmu@ec680000 {
|
||||
ipmmu_mp: iommu@ec680000 {
|
||||
compatible = "renesas,ipmmu-r8a7791",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xec680000 0 0x1000>;
|
||||
|
|
@ -388,7 +401,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_mx: mmu@fe951000 {
|
||||
ipmmu_mx: iommu@fe951000 {
|
||||
compatible = "renesas,ipmmu-r8a7791",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xfe951000 0 0x1000>;
|
||||
|
|
@ -398,7 +411,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_rt: mmu@ffc80000 {
|
||||
ipmmu_rt: iommu@ffc80000 {
|
||||
compatible = "renesas,ipmmu-r8a7791",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xffc80000 0 0x1000>;
|
||||
|
|
@ -407,7 +420,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_gp: mmu@e62a0000 {
|
||||
ipmmu_gp: iommu@e62a0000 {
|
||||
compatible = "renesas,ipmmu-r8a7791",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xe62a0000 0 0x1000>;
|
||||
|
|
@ -595,7 +608,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphy: usb-phy@e6590100 {
|
||||
usbphy: usb-phy-controller@e6590100 {
|
||||
compatible = "renesas,usb-phy-r8a7791",
|
||||
"renesas,rcar-gen2-usb-phy";
|
||||
reg = <0 0xe6590100 0 0x100>;
|
||||
|
|
@ -607,11 +620,11 @@
|
|||
resets = <&cpg 704>;
|
||||
status = "disabled";
|
||||
|
||||
usb0: usb-channel@0 {
|
||||
usb0: usb-phy@0 {
|
||||
reg = <0>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
usb2: usb-channel@2 {
|
||||
usb2: usb-phy@2 {
|
||||
reg = <2>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
|
@ -717,6 +730,7 @@
|
|||
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -1067,6 +1081,76 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm0: pwm@e6e30000 {
|
||||
compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
|
||||
reg = <0 0xe6e30000 0 0x8>;
|
||||
clocks = <&cpg CPG_MOD 523>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 523>;
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1: pwm@e6e31000 {
|
||||
compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
|
||||
reg = <0 0xe6e31000 0 0x8>;
|
||||
clocks = <&cpg CPG_MOD 523>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 523>;
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2: pwm@e6e32000 {
|
||||
compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
|
||||
reg = <0 0xe6e32000 0 0x8>;
|
||||
clocks = <&cpg CPG_MOD 523>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 523>;
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm3: pwm@e6e33000 {
|
||||
compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
|
||||
reg = <0 0xe6e33000 0 0x8>;
|
||||
clocks = <&cpg CPG_MOD 523>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 523>;
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm4: pwm@e6e34000 {
|
||||
compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
|
||||
reg = <0 0xe6e34000 0 0x8>;
|
||||
clocks = <&cpg CPG_MOD 523>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 523>;
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm5: pwm@e6e35000 {
|
||||
compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
|
||||
reg = <0 0xe6e35000 0 0x8>;
|
||||
clocks = <&cpg CPG_MOD 523>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 523>;
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm6: pwm@e6e36000 {
|
||||
compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
|
||||
reg = <0 0xe6e36000 0 0x8>;
|
||||
clocks = <&cpg CPG_MOD 523>;
|
||||
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 523>;
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
adc: adc@e6e54000 {
|
||||
compatible = "renesas,r8a7791-gyroadc",
|
||||
"renesas,rcar-gyroadc";
|
||||
|
|
@ -1482,7 +1566,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
sdhi0: mmc@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a7791",
|
||||
"renesas,rcar-gen2-sdhi";
|
||||
reg = <0 0xee100000 0 0x328>;
|
||||
|
|
@ -1497,7 +1581,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi1: sd@ee140000 {
|
||||
sdhi1: mmc@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a7791",
|
||||
"renesas,rcar-gen2-sdhi";
|
||||
reg = <0 0xee140000 0 0x100>;
|
||||
|
|
@ -1512,7 +1596,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi2: sd@ee160000 {
|
||||
sdhi2: mmc@ee160000 {
|
||||
compatible = "renesas,sdhi-r8a7791",
|
||||
"renesas,rcar-gen2-sdhi";
|
||||
reg = <0 0xee160000 0 0x100>;
|
||||
|
|
@ -1681,9 +1765,10 @@
|
|||
reg = <0 0xfeb00000 0 0x40000>;
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>;
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
|
||||
clock-names = "du.0", "du.1";
|
||||
resets = <&cpg 724>;
|
||||
reset-names = "du.0";
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
|
|
|
|||
|
|
@ -112,6 +112,9 @@
|
|||
keyboard {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&keyboard_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
key-1 {
|
||||
linux,code = <KEY_1>;
|
||||
label = "SW2-1";
|
||||
|
|
@ -235,6 +238,11 @@
|
|||
function = "du1";
|
||||
};
|
||||
|
||||
keyboard_pins: keyboard {
|
||||
pins = "GP_3_10", "GP_3_11", "GP_3_12", "GP_3_15", "GP_11_02";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pmic_irq_pins: pmicirq {
|
||||
groups = "intc_irq2";
|
||||
function = "intc";
|
||||
|
|
@ -289,8 +297,6 @@
|
|||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -329,14 +335,14 @@
|
|||
compatible = "dlg,da9063-rtc";
|
||||
};
|
||||
|
||||
wdt {
|
||||
watchdog {
|
||||
compatible = "dlg,da9063-watchdog";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du0_pins &du1_pins>;
|
||||
pinctrl-0 = <&du0_pins>, <&du1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x1_clk>, <&x2_clk>;
|
||||
|
|
|
|||
|
|
@ -45,7 +45,6 @@
|
|||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "renesas,apmu";
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
|
|
@ -54,6 +53,7 @@
|
|||
clock-frequency = <1000000000>;
|
||||
clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
|
||||
power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
|
||||
enable-method = "renesas,apmu";
|
||||
next-level-cache = <&L2_CA15>;
|
||||
};
|
||||
|
||||
|
|
@ -64,6 +64,7 @@
|
|||
clock-frequency = <1000000000>;
|
||||
clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
|
||||
power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
|
||||
enable-method = "renesas,apmu";
|
||||
next-level-cache = <&L2_CA15>;
|
||||
};
|
||||
|
||||
|
|
@ -110,6 +111,7 @@
|
|||
compatible = "renesas,r8a7792-wdt",
|
||||
"renesas,rcar-gen2-wdt";
|
||||
reg = <0 0xe6020000 0 0x0c>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 402>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 402>;
|
||||
|
|
@ -296,7 +298,7 @@
|
|||
resets = <&cpg 913>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
pfc: pinctrl@e6060000 {
|
||||
compatible = "renesas,pfc-r8a7792";
|
||||
reg = <0 0xe6060000 0 0x144>;
|
||||
};
|
||||
|
|
@ -314,7 +316,7 @@
|
|||
apmu@e6152000 {
|
||||
compatible = "renesas,r8a7792-apmu", "renesas,apmu";
|
||||
reg = <0 0xe6152000 0 0x188>;
|
||||
cpus = <&cpu0 &cpu1>;
|
||||
cpus = <&cpu0>, <&cpu1>;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
|
|
@ -537,6 +539,7 @@
|
|||
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -780,7 +783,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
sdhi0: mmc@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a7792",
|
||||
"renesas,rcar-gen2-sdhi";
|
||||
reg = <0 0xee100000 0 0x328>;
|
||||
|
|
@ -852,9 +855,10 @@
|
|||
reg = <0 0xfeb00000 0 0x40000>;
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>;
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
|
||||
clock-names = "du.0", "du.1";
|
||||
resets = <&cpg 724>;
|
||||
reset-names = "du.0";
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
|
|
|
|||
|
|
@ -49,6 +49,9 @@
|
|||
i2c10 = &gpioi2c4;
|
||||
i2c11 = &i2chdmi;
|
||||
i2c12 = &i2cexio4;
|
||||
mmc0 = &sdhi0;
|
||||
mmc1 = &sdhi1;
|
||||
mmc2 = &sdhi2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
|
@ -61,9 +64,12 @@
|
|||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
keyboard {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&keyboard_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
key-1 {
|
||||
gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_1>;
|
||||
|
|
@ -334,9 +340,8 @@
|
|||
composite-in@20 {
|
||||
compatible = "adi,adv7180cp";
|
||||
reg = <0x20>;
|
||||
remote = <&vin1>;
|
||||
|
||||
port {
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
|
@ -366,8 +371,6 @@
|
|||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -396,7 +399,7 @@
|
|||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
default-input = <0>;
|
||||
|
||||
port {
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
|
@ -567,6 +570,11 @@
|
|||
function = "audio_clk";
|
||||
};
|
||||
|
||||
keyboard_pins: keyboard {
|
||||
pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
vin0_pins: vin0 {
|
||||
groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
|
||||
function = "vin0";
|
||||
|
|
@ -579,7 +587,7 @@
|
|||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-0 = <ðer_pins>, <&phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
|
|
@ -587,10 +595,13 @@
|
|||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-id0022.1537",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
micrel,led-mode = <1>;
|
||||
reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -729,7 +740,7 @@
|
|||
compatible = "dlg,da9063-rtc";
|
||||
};
|
||||
|
||||
wdt {
|
||||
watchdog {
|
||||
compatible = "dlg,da9063-watchdog";
|
||||
};
|
||||
};
|
||||
|
|
@ -753,7 +764,7 @@
|
|||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_pins &sound_clk_pins>;
|
||||
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* Single DAI */
|
||||
|
|
@ -763,8 +774,8 @@
|
|||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0 &src2 &dvc0>;
|
||||
capture = <&ssi1 &src3 &dvc1>;
|
||||
playback = <&ssi0>, <&src2>, <&dvc0>;
|
||||
capture = <&ssi1>, <&src3>, <&dvc1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -60,7 +60,6 @@
|
|||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "renesas,apmu";
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
|
|
@ -69,6 +68,7 @@
|
|||
clock-frequency = <1500000000>;
|
||||
clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
|
||||
power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
|
||||
enable-method = "renesas,apmu";
|
||||
voltage-tolerance = <1>; /* 1% */
|
||||
clock-latency = <300000>; /* 300 us */
|
||||
|
||||
|
|
@ -89,6 +89,7 @@
|
|||
clock-frequency = <1500000000>;
|
||||
clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
|
||||
power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
|
||||
enable-method = "renesas,apmu";
|
||||
voltage-tolerance = <1>; /* 1% */
|
||||
clock-latency = <300000>; /* 300 us */
|
||||
|
||||
|
|
@ -145,6 +146,7 @@
|
|||
compatible = "renesas,r8a7793-wdt",
|
||||
"renesas,rcar-gen2-wdt";
|
||||
reg = <0 0xe6020000 0 0x0c>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 402>;
|
||||
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 402>;
|
||||
|
|
@ -271,7 +273,7 @@
|
|||
resets = <&cpg 904>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
pfc: pinctrl@e6060000 {
|
||||
compatible = "renesas,pfc-r8a7793";
|
||||
reg = <0 0xe6060000 0 0x250>;
|
||||
};
|
||||
|
|
@ -290,7 +292,7 @@
|
|||
apmu@e6152000 {
|
||||
compatible = "renesas,r8a7793-apmu", "renesas,apmu";
|
||||
reg = <0 0xe6152000 0 0x188>;
|
||||
cpus = <&cpu0 &cpu1>;
|
||||
cpus = <&cpu0>, <&cpu1>;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
|
|
@ -336,7 +338,7 @@
|
|||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
ipmmu_sy0: mmu@e6280000 {
|
||||
ipmmu_sy0: iommu@e6280000 {
|
||||
compatible = "renesas,ipmmu-r8a7793",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xe6280000 0 0x1000>;
|
||||
|
|
@ -346,7 +348,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_sy1: mmu@e6290000 {
|
||||
ipmmu_sy1: iommu@e6290000 {
|
||||
compatible = "renesas,ipmmu-r8a7793",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xe6290000 0 0x1000>;
|
||||
|
|
@ -355,7 +357,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_ds: mmu@e6740000 {
|
||||
ipmmu_ds: iommu@e6740000 {
|
||||
compatible = "renesas,ipmmu-r8a7793",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xe6740000 0 0x1000>;
|
||||
|
|
@ -365,7 +367,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_mp: mmu@ec680000 {
|
||||
ipmmu_mp: iommu@ec680000 {
|
||||
compatible = "renesas,ipmmu-r8a7793",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xec680000 0 0x1000>;
|
||||
|
|
@ -374,7 +376,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_mx: mmu@fe951000 {
|
||||
ipmmu_mx: iommu@fe951000 {
|
||||
compatible = "renesas,ipmmu-r8a7793",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xfe951000 0 0x1000>;
|
||||
|
|
@ -384,7 +386,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_rt: mmu@ffc80000 {
|
||||
ipmmu_rt: iommu@ffc80000 {
|
||||
compatible = "renesas,ipmmu-r8a7793",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xffc80000 0 0x1000>;
|
||||
|
|
@ -393,7 +395,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_gp: mmu@e62a0000 {
|
||||
ipmmu_gp: iommu@e62a0000 {
|
||||
compatible = "renesas,ipmmu-r8a7793",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xe62a0000 0 0x1000>;
|
||||
|
|
@ -1227,7 +1229,7 @@
|
|||
dma-channels = <13>;
|
||||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
sdhi0: mmc@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a7793",
|
||||
"renesas,rcar-gen2-sdhi";
|
||||
reg = <0 0xee100000 0 0x328>;
|
||||
|
|
@ -1242,7 +1244,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi1: sd@ee140000 {
|
||||
sdhi1: mmc@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a7793",
|
||||
"renesas,rcar-gen2-sdhi";
|
||||
reg = <0 0xee140000 0 0x100>;
|
||||
|
|
@ -1257,7 +1259,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi2: sd@ee160000 {
|
||||
sdhi2: mmc@ee160000 {
|
||||
compatible = "renesas,sdhi-r8a7793",
|
||||
"renesas,rcar-gen2-sdhi";
|
||||
reg = <0 0xee160000 0 0x100>;
|
||||
|
|
@ -1341,9 +1343,10 @@
|
|||
reg = <0 0xfeb00000 0 0x40000>;
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>;
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
|
||||
clock-names = "du.0", "du.1";
|
||||
resets = <&cpg 724>;
|
||||
reset-names = "du.0";
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
/dts-v1/;
|
||||
#include "r8a7794.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Alt";
|
||||
|
|
@ -19,6 +20,9 @@
|
|||
i2c10 = &gpioi2c4;
|
||||
i2c11 = &i2chdmi;
|
||||
i2c12 = &i2cexio4;
|
||||
mmc0 = &mmcif0;
|
||||
mmc1 = &sdhi0;
|
||||
mmc2 = &sdhi1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
|
@ -91,6 +95,42 @@
|
|||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
keyboard {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&keyboard_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
one {
|
||||
linux,code = <KEY_1>;
|
||||
label = "SW2-1";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
two {
|
||||
linux,code = <KEY_2>;
|
||||
label = "SW2-2";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
three {
|
||||
linux,code = <KEY_3>;
|
||||
label = "SW2-3";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
four {
|
||||
linux,code = <KEY_4>;
|
||||
label = "SW2-4";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
vga-encoder {
|
||||
compatible = "adi,adv7123";
|
||||
|
||||
|
|
@ -167,7 +207,6 @@
|
|||
composite-in@20 {
|
||||
compatible = "adi,adv7180";
|
||||
reg = <0x20>;
|
||||
remote = <&vin0>;
|
||||
|
||||
port {
|
||||
adv7180: endpoint {
|
||||
|
|
@ -317,6 +356,11 @@
|
|||
groups = "usb1";
|
||||
function = "usb1";
|
||||
};
|
||||
|
||||
keyboard_pins: keyboard {
|
||||
pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
&cmt0 {
|
||||
|
|
@ -331,7 +375,7 @@
|
|||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-0 = <ðer_pins>, <&phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
|
|
@ -339,10 +383,13 @@
|
|||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-id0022.1537",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
|
||||
micrel,led-mode = <1>;
|
||||
reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -416,7 +463,7 @@
|
|||
compatible = "dlg,da9063-rtc";
|
||||
};
|
||||
|
||||
wdt {
|
||||
watchdog {
|
||||
compatible = "dlg,da9063-watchdog";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -31,6 +31,8 @@
|
|||
serial0 = &scif2;
|
||||
i2c9 = &gpioi2c1;
|
||||
i2c10 = &i2chdmi;
|
||||
mmc0 = &mmcif0;
|
||||
mmc1 = &sdhi1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
|
@ -43,9 +45,12 @@
|
|||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
keyboard {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&keyboard_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
key-3 {
|
||||
gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_3>;
|
||||
|
|
@ -236,7 +241,6 @@
|
|||
composite-in@20 {
|
||||
compatible = "adi,adv7180";
|
||||
reg = <0x20>;
|
||||
remote = <&vin0>;
|
||||
|
||||
port {
|
||||
adv7180: endpoint {
|
||||
|
|
@ -255,8 +259,6 @@
|
|||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -359,6 +361,11 @@
|
|||
function = "du1";
|
||||
};
|
||||
|
||||
keyboard_pins: keyboard {
|
||||
pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
ssi_pins: sound {
|
||||
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
|
||||
function = "ssi";
|
||||
|
|
@ -382,7 +389,7 @@
|
|||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-0 = <ðer_pins>, <&phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
|
|
@ -390,10 +397,13 @@
|
|||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-id0022.1537",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
|
||||
micrel,led-mode = <1>;
|
||||
reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -423,7 +433,7 @@
|
|||
compatible = "dlg,da9063-rtc";
|
||||
};
|
||||
|
||||
wdt {
|
||||
watchdog {
|
||||
compatible = "dlg,da9063-watchdog";
|
||||
};
|
||||
};
|
||||
|
|
@ -520,7 +530,7 @@
|
|||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du0_pins &du1_pins>;
|
||||
pinctrl-0 = <&du0_pins>, <&du1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -543,7 +553,7 @@
|
|||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&ssi_pins &audio_clk_pins>;
|
||||
pinctrl-0 = <&ssi_pins>, <&audio_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
|
|
|
|||
|
|
@ -62,7 +62,6 @@
|
|||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "renesas,apmu";
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
|
|
@ -71,6 +70,7 @@
|
|||
clock-frequency = <1000000000>;
|
||||
clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
|
||||
power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
|
||||
enable-method = "renesas,apmu";
|
||||
next-level-cache = <&L2_CA7>;
|
||||
};
|
||||
|
||||
|
|
@ -81,6 +81,7 @@
|
|||
clock-frequency = <1000000000>;
|
||||
clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
|
||||
power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
|
||||
enable-method = "renesas,apmu";
|
||||
next-level-cache = <&L2_CA7>;
|
||||
};
|
||||
|
||||
|
|
@ -127,6 +128,7 @@
|
|||
compatible = "renesas,r8a7794-wdt",
|
||||
"renesas,rcar-gen2-wdt";
|
||||
reg = <0 0xe6020000 0 0x0c>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 402>;
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 402>;
|
||||
|
|
@ -238,7 +240,7 @@
|
|||
resets = <&cpg 905>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
pfc: pinctrl@e6060000 {
|
||||
compatible = "renesas,pfc-r8a7794";
|
||||
reg = <0 0xe6060000 0 0x11c>;
|
||||
};
|
||||
|
|
@ -256,7 +258,7 @@
|
|||
apmu@e6151000 {
|
||||
compatible = "renesas,r8a7794-apmu", "renesas,apmu";
|
||||
reg = <0 0xe6151000 0 0x188>;
|
||||
cpus = <&cpu0 &cpu1>;
|
||||
cpus = <&cpu0>, <&cpu1>;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
|
|
@ -290,7 +292,7 @@
|
|||
resets = <&cpg 407>;
|
||||
};
|
||||
|
||||
ipmmu_sy0: mmu@e6280000 {
|
||||
ipmmu_sy0: iommu@e6280000 {
|
||||
compatible = "renesas,ipmmu-r8a7794",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xe6280000 0 0x1000>;
|
||||
|
|
@ -300,7 +302,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_sy1: mmu@e6290000 {
|
||||
ipmmu_sy1: iommu@e6290000 {
|
||||
compatible = "renesas,ipmmu-r8a7794",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xe6290000 0 0x1000>;
|
||||
|
|
@ -309,7 +311,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_ds: mmu@e6740000 {
|
||||
ipmmu_ds: iommu@e6740000 {
|
||||
compatible = "renesas,ipmmu-r8a7794",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xe6740000 0 0x1000>;
|
||||
|
|
@ -319,7 +321,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_mp: mmu@ec680000 {
|
||||
ipmmu_mp: iommu@ec680000 {
|
||||
compatible = "renesas,ipmmu-r8a7794",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xec680000 0 0x1000>;
|
||||
|
|
@ -328,7 +330,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_mx: mmu@fe951000 {
|
||||
ipmmu_mx: iommu@fe951000 {
|
||||
compatible = "renesas,ipmmu-r8a7794",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xfe951000 0 0x1000>;
|
||||
|
|
@ -338,7 +340,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_gp: mmu@e62a0000 {
|
||||
ipmmu_gp: iommu@e62a0000 {
|
||||
compatible = "renesas,ipmmu-r8a7794",
|
||||
"renesas,ipmmu-vmsa";
|
||||
reg = <0 0xe62a0000 0 0x1000>;
|
||||
|
|
@ -504,7 +506,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphy: usb-phy@e6590100 {
|
||||
usbphy: usb-phy-controller@e6590100 {
|
||||
compatible = "renesas,usb-phy-r8a7794",
|
||||
"renesas,rcar-gen2-usb-phy";
|
||||
reg = <0 0xe6590100 0 0x100>;
|
||||
|
|
@ -516,11 +518,11 @@
|
|||
resets = <&cpg 704>;
|
||||
status = "disabled";
|
||||
|
||||
usb0: usb-channel@0 {
|
||||
usb0: usb-phy@0 {
|
||||
reg = <0>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
usb2: usb-channel@2 {
|
||||
usb2: usb-phy@2 {
|
||||
reg = <2>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
|
@ -598,6 +600,7 @@
|
|||
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -1232,7 +1235,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
sdhi0: mmc@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a7794",
|
||||
"renesas,rcar-gen2-sdhi";
|
||||
reg = <0 0xee100000 0 0x328>;
|
||||
|
|
@ -1247,7 +1250,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi1: sd@ee140000 {
|
||||
sdhi1: mmc@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a7794",
|
||||
"renesas,rcar-gen2-sdhi";
|
||||
reg = <0 0xee140000 0 0x100>;
|
||||
|
|
@ -1262,7 +1265,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi2: sd@ee160000 {
|
||||
sdhi2: mmc@ee160000 {
|
||||
compatible = "renesas,sdhi-r8a7794",
|
||||
"renesas,rcar-gen2-sdhi";
|
||||
reg = <0 0xee160000 0 0x100>;
|
||||
|
|
@ -1356,6 +1359,8 @@
|
|||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
|
||||
clock-names = "du.0", "du.1";
|
||||
resets = <&cpg 724>;
|
||||
reset-names = "du.0";
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
|
|
|
|||
|
|
@ -47,111 +47,3 @@
|
|||
clock-names = "du.0", "du.1", "du.2", "du.3",
|
||||
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
|
||||
};
|
||||
|
||||
&ehci2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
rcar_dw_hdmi0_out: endpoint {
|
||||
remote-endpoint = <&hdmi0_con>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dw_hdmi0_snd_in: endpoint {
|
||||
remote-endpoint = <&rsnd_endpoint1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi0_con {
|
||||
remote-endpoint = <&rcar_dw_hdmi0_out>;
|
||||
};
|
||||
|
||||
&hdmi1 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
rcar_dw_hdmi1_out: endpoint {
|
||||
remote-endpoint = <&hdmi1_con>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dw_hdmi1_snd_in: endpoint {
|
||||
remote-endpoint = <&rsnd_endpoint2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi1_con {
|
||||
remote-endpoint = <&rcar_dw_hdmi1_out>;
|
||||
};
|
||||
|
||||
&ohci2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pfc {
|
||||
usb2_pins: usb2 {
|
||||
groups = "usb2";
|
||||
function = "usb2";
|
||||
};
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
ports {
|
||||
/* rsnd_port0 is on salvator-common */
|
||||
rsnd_port1: port@1 {
|
||||
reg = <1>;
|
||||
rsnd_endpoint1: endpoint {
|
||||
remote-endpoint = <&dw_hdmi0_snd_in>;
|
||||
|
||||
dai-format = "i2s";
|
||||
bitclock-master = <&rsnd_endpoint1>;
|
||||
frame-master = <&rsnd_endpoint1>;
|
||||
|
||||
playback = <&ssi2>;
|
||||
};
|
||||
};
|
||||
rsnd_port2: port@2 {
|
||||
reg = <2>;
|
||||
rsnd_endpoint2: endpoint {
|
||||
remote-endpoint = <&dw_hdmi1_snd_in>;
|
||||
|
||||
dai-format = "i2s";
|
||||
bitclock-master = <&rsnd_endpoint2>;
|
||||
frame-master = <&rsnd_endpoint2>;
|
||||
|
||||
playback = <&ssi3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sound_card {
|
||||
dais = <&rsnd_port0 /* ak4613 */
|
||||
&rsnd_port1 /* HDMI0 */
|
||||
&rsnd_port2>; /* HDMI1 */
|
||||
};
|
||||
|
||||
&usb2_phy2 {
|
||||
pinctrl-0 = <&usb2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board
|
||||
* Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board with R-Car H3 ES1.x
|
||||
*
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
* Copyright (C) 2016 Cogent Embedded, Inc.
|
||||
|
|
|
|||
|
|
@ -7,6 +7,8 @@
|
|||
|
||||
#include "r8a77951.dtsi"
|
||||
|
||||
#undef SOC_HAS_USB2_CH3
|
||||
|
||||
&audma0 {
|
||||
iommus = <&ipmmu_mp1 0>, <&ipmmu_mp1 1>,
|
||||
<&ipmmu_mp1 2>, <&ipmmu_mp1 3>,
|
||||
|
|
@ -29,8 +31,13 @@
|
|||
<&ipmmu_mp1 30>, <&ipmmu_mp1 31>;
|
||||
};
|
||||
|
||||
&cluster0_opp {
|
||||
/delete-node/ opp-1600000000;
|
||||
/delete-node/ opp-1700000000;
|
||||
};
|
||||
|
||||
&du {
|
||||
vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd3 0>;
|
||||
renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd3 0>;
|
||||
};
|
||||
|
||||
&fcpvb1 {
|
||||
|
|
@ -77,7 +84,7 @@
|
|||
/delete-node/ dma-controller@e6460000;
|
||||
/delete-node/ dma-controller@e6470000;
|
||||
|
||||
ipmmu_mp1: mmu@ec680000 {
|
||||
ipmmu_mp1: iommu@ec680000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xec680000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 5>;
|
||||
|
|
@ -85,7 +92,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_sy: mmu@e7730000 {
|
||||
ipmmu_sy: iommu@e7730000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xe7730000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 8>;
|
||||
|
|
@ -93,11 +100,11 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
/delete-node/ mmu@fd950000;
|
||||
/delete-node/ mmu@fd960000;
|
||||
/delete-node/ mmu@fd970000;
|
||||
/delete-node/ mmu@febe0000;
|
||||
/delete-node/ mmu@fe980000;
|
||||
/delete-node/ iommu@fd950000;
|
||||
/delete-node/ iommu@fd960000;
|
||||
/delete-node/ iommu@fd970000;
|
||||
/delete-node/ iommu@febe0000;
|
||||
/delete-node/ iommu@fe980000;
|
||||
|
||||
xhci1: usb@ee040000 {
|
||||
compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
|
||||
|
|
@ -187,6 +194,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -11,22 +11,16 @@
|
|||
|
||||
#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
|
||||
|
||||
#define SOC_HAS_HDMI1
|
||||
#define SOC_HAS_SATA
|
||||
#define SOC_HAS_USB2_CH2
|
||||
#define SOC_HAS_USB2_CH3
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7795";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
i2c5 = &i2c5;
|
||||
i2c6 = &i2c6;
|
||||
i2c7 = &i2c_dvfs;
|
||||
};
|
||||
|
||||
/*
|
||||
* The external audio clocks are configured as 0 Hz fixed frequency
|
||||
* clocks by default.
|
||||
|
|
@ -57,7 +51,7 @@
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cluster0_opp: opp_table0 {
|
||||
cluster0_opp: opp-table-0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
|
|
@ -91,7 +85,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
cluster1_opp: opp_table1 {
|
||||
cluster1_opp: opp-table-1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
|
|
@ -364,6 +358,7 @@
|
|||
rwdt: watchdog@e6020000 {
|
||||
compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
|
||||
reg = <0 0xe6020000 0 0x0c>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 402>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 402>;
|
||||
|
|
@ -490,7 +485,7 @@
|
|||
resets = <&cpg 905>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
pfc: pinctrl@e6060000 {
|
||||
compatible = "renesas,pfc-r8a7795";
|
||||
reg = <0 0xe6060000 0 0x50c>;
|
||||
};
|
||||
|
|
@ -616,6 +611,71 @@
|
|||
resets = <&cpg 407>;
|
||||
};
|
||||
|
||||
tmu0: timer@e61e0000 {
|
||||
compatible = "renesas,tmu-r8a7795", "renesas,tmu";
|
||||
reg = <0 0xe61e0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 125>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 125>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu1: timer@e6fc0000 {
|
||||
compatible = "renesas,tmu-r8a7795", "renesas,tmu";
|
||||
reg = <0 0xe6fc0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 124>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 124>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu2: timer@e6fd0000 {
|
||||
compatible = "renesas,tmu-r8a7795", "renesas,tmu";
|
||||
reg = <0 0xe6fd0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 123>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 123>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu3: timer@e6fe0000 {
|
||||
compatible = "renesas,tmu-r8a7795", "renesas,tmu";
|
||||
reg = <0 0xe6fe0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 122>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 122>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu4: timer@ffc00000 {
|
||||
compatible = "renesas,tmu-r8a7795", "renesas,tmu";
|
||||
reg = <0 0xffc00000 0 0x30>;
|
||||
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 121>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 121>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -1073,7 +1133,7 @@
|
|||
<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
|
||||
};
|
||||
|
||||
ipmmu_ds0: mmu@e6740000 {
|
||||
ipmmu_ds0: iommu@e6740000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xe6740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 0>;
|
||||
|
|
@ -1081,7 +1141,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_ds1: mmu@e7740000 {
|
||||
ipmmu_ds1: iommu@e7740000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xe7740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 1>;
|
||||
|
|
@ -1089,7 +1149,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_hc: mmu@e6570000 {
|
||||
ipmmu_hc: iommu@e6570000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xe6570000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 2>;
|
||||
|
|
@ -1097,7 +1157,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_ir: mmu@ff8b0000 {
|
||||
ipmmu_ir: iommu@ff8b0000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xff8b0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 3>;
|
||||
|
|
@ -1105,7 +1165,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_mm: mmu@e67b0000 {
|
||||
ipmmu_mm: iommu@e67b0000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xe67b0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
@ -1114,7 +1174,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_mp0: mmu@ec670000 {
|
||||
ipmmu_mp0: iommu@ec670000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xec670000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 4>;
|
||||
|
|
@ -1122,7 +1182,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_pv0: mmu@fd800000 {
|
||||
ipmmu_pv0: iommu@fd800000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xfd800000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 6>;
|
||||
|
|
@ -1130,7 +1190,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_pv1: mmu@fd950000 {
|
||||
ipmmu_pv1: iommu@fd950000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xfd950000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 7>;
|
||||
|
|
@ -1138,7 +1198,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_pv2: mmu@fd960000 {
|
||||
ipmmu_pv2: iommu@fd960000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xfd960000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 8>;
|
||||
|
|
@ -1146,7 +1206,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_pv3: mmu@fd970000 {
|
||||
ipmmu_pv3: iommu@fd970000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xfd970000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 9>;
|
||||
|
|
@ -1154,7 +1214,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_rt: mmu@ffc80000 {
|
||||
ipmmu_rt: iommu@ffc80000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xffc80000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 10>;
|
||||
|
|
@ -1162,7 +1222,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vc0: mmu@fe6b0000 {
|
||||
ipmmu_vc0: iommu@fe6b0000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xfe6b0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 12>;
|
||||
|
|
@ -1170,7 +1230,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vc1: mmu@fe6f0000 {
|
||||
ipmmu_vc1: iommu@fe6f0000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xfe6f0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 13>;
|
||||
|
|
@ -1178,7 +1238,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vi0: mmu@febd0000 {
|
||||
ipmmu_vi0: iommu@febd0000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xfebd0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 14>;
|
||||
|
|
@ -1186,7 +1246,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vi1: mmu@febe0000 {
|
||||
ipmmu_vi1: iommu@febe0000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xfebe0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 15>;
|
||||
|
|
@ -1194,7 +1254,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vp0: mmu@fe990000 {
|
||||
ipmmu_vp0: iommu@fe990000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xfe990000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 16>;
|
||||
|
|
@ -1202,7 +1262,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vp1: mmu@fe980000 {
|
||||
ipmmu_vp1: iommu@fe980000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xfe980000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 17>;
|
||||
|
|
@ -1247,9 +1307,12 @@
|
|||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii";
|
||||
rx-internal-delay-ps = <0>;
|
||||
tx-internal-delay-ps = <0>;
|
||||
iommus = <&ipmmu_ds0 16>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -1294,6 +1357,7 @@
|
|||
reg = <0 0xe66c0000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch_int", "g_int";
|
||||
clocks = <&cpg CPG_MOD 914>,
|
||||
<&cpg CPG_CORE R8A7795_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
|
|
@ -1945,12 +2009,12 @@
|
|||
* clkout : #clock-cells = <0>; <&rcar_sound>;
|
||||
* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
|
||||
*/
|
||||
compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3";
|
||||
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
||||
<0 0xec5a0000 0 0x100>, /* ADG */
|
||||
<0 0xec540000 0 0x1000>, /* SSIU */
|
||||
<0 0xec541000 0 0x280>, /* SSI */
|
||||
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
|
||||
compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3";
|
||||
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
||||
<0 0xec5a0000 0 0x100>, /* ADG */
|
||||
<0 0xec540000 0 0x1000>, /* SSIU */
|
||||
<0 0xec541000 0 0x280>, /* SSI */
|
||||
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
|
||||
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
|
||||
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
|
|
@ -2204,7 +2268,7 @@
|
|||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu40: ssiu-32 {
|
||||
dmas = <&audma0 0x71>, <&audma1 0x72>;
|
||||
dmas = <&audma0 0x71>, <&audma1 0x72>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu41: ssiu-33 {
|
||||
|
|
@ -2339,6 +2403,18 @@
|
|||
};
|
||||
};
|
||||
|
||||
mlp: mlp@ec520000 {
|
||||
compatible = "renesas,r8a7795-mlp",
|
||||
"renesas,rcar-gen3-mlp";
|
||||
reg = <0 0xec520000 0 0x800>;
|
||||
interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 802>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 802>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
audma0: dma-controller@ec700000 {
|
||||
compatible = "renesas,dmac-r8a7795",
|
||||
"renesas,rcar-dmac";
|
||||
|
|
@ -2590,12 +2666,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
sdhi0: mmc@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a7795",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee100000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7795_CLK_SD0H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
|
|
@ -2603,12 +2680,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi1: sd@ee120000 {
|
||||
sdhi1: mmc@ee120000 {
|
||||
compatible = "renesas,sdhi-r8a7795",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee120000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 313>;
|
||||
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7795_CLK_SD1H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 313>;
|
||||
|
|
@ -2616,12 +2694,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi2: sd@ee140000 {
|
||||
sdhi2: mmc@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a7795",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7795_CLK_SD2H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 312>;
|
||||
|
|
@ -2629,12 +2708,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi3: sd@ee160000 {
|
||||
sdhi3: mmc@ee160000 {
|
||||
compatible = "renesas,sdhi-r8a7795",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee160000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 311>;
|
||||
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7795_CLK_SD3H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 311>;
|
||||
|
|
@ -2642,6 +2722,22 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
rpc: spi@ee200000 {
|
||||
compatible = "renesas,r8a7795-rpc-if",
|
||||
"renesas,rcar-gen3-rpc-if";
|
||||
reg = <0 0xee200000 0 0x200>,
|
||||
<0 0x08000000 0 0x04000000>,
|
||||
<0 0xee208000 0 0x100>;
|
||||
reg-names = "regs", "dirmap", "wbuf";
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata: sata@ee300000 {
|
||||
compatible = "renesas,sata-r8a7795",
|
||||
"renesas,rcar-gen3-sata";
|
||||
|
|
@ -2725,6 +2821,44 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pciec0_ep: pcie-ep@fe000000 {
|
||||
compatible = "renesas,r8a7795-pcie-ep",
|
||||
"renesas,rcar-gen3-pcie-ep";
|
||||
reg = <0x0 0xfe000000 0 0x80000>,
|
||||
<0x0 0xfe100000 0 0x100000>,
|
||||
<0x0 0xfe200000 0 0x200000>,
|
||||
<0x0 0x30000000 0 0x8000000>,
|
||||
<0x0 0x38000000 0 0x8000000>;
|
||||
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 319>;
|
||||
clock-names = "pcie";
|
||||
resets = <&cpg 319>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pciec1_ep: pcie-ep@ee800000 {
|
||||
compatible = "renesas,r8a7795-pcie-ep",
|
||||
"renesas,rcar-gen3-pcie-ep";
|
||||
reg = <0x0 0xee800000 0 0x80000>,
|
||||
<0x0 0xee900000 0 0x100000>,
|
||||
<0x0 0xeea00000 0 0x200000>,
|
||||
<0x0 0xc0000000 0 0x8000000>,
|
||||
<0x0 0xc8000000 0 0x8000000>;
|
||||
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
|
||||
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 318>;
|
||||
clock-names = "pcie";
|
||||
resets = <&cpg 318>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
imr-lx4@fe860000 {
|
||||
compatible = "renesas,r8a7795-imr-lx4",
|
||||
"renesas,imr-lx4";
|
||||
|
|
@ -2992,6 +3126,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -3047,6 +3185,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -3086,6 +3228,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -3177,14 +3323,15 @@
|
|||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>,
|
||||
<&cpg CPG_MOD 721>;
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>;
|
||||
clock-names = "du.0", "du.1", "du.2", "du.3";
|
||||
resets = <&cpg 724>, <&cpg 722>;
|
||||
reset-names = "du.0", "du.2";
|
||||
|
||||
renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>;
|
||||
vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
|
||||
renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>,
|
||||
<&vspd0 1>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -3194,8 +3341,6 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb: endpoint {
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
|
@ -3238,8 +3383,6 @@
|
|||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -3251,7 +3394,7 @@
|
|||
};
|
||||
|
||||
thermal-zones {
|
||||
sensor_thermal1: sensor-thermal1 {
|
||||
sensor1_thermal: sensor1-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 0>;
|
||||
|
|
@ -3266,7 +3409,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
sensor_thermal2: sensor-thermal2 {
|
||||
sensor2_thermal: sensor2-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 1>;
|
||||
|
|
@ -3281,7 +3424,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
sensor_thermal3: sensor-thermal3 {
|
||||
sensor3_thermal: sensor3-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 2>;
|
||||
|
|
|
|||
|
|
@ -35,49 +35,3 @@
|
|||
clock-names = "du.0", "du.1", "du.2",
|
||||
"dclkin.0", "dclkin.1", "dclkin.2";
|
||||
};
|
||||
|
||||
&hdmi0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
rcar_dw_hdmi0_out: endpoint {
|
||||
remote-endpoint = <&hdmi0_con>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dw_hdmi0_snd_in: endpoint {
|
||||
remote-endpoint = <&rsnd_endpoint1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi0_con {
|
||||
remote-endpoint = <&rcar_dw_hdmi0_out>;
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
ports {
|
||||
/* rsnd_port0 is on salvator-common */
|
||||
rsnd_port1: port@1 {
|
||||
reg = <1>;
|
||||
rsnd_endpoint1: endpoint {
|
||||
remote-endpoint = <&dw_hdmi0_snd_in>;
|
||||
|
||||
dai-format = "i2s";
|
||||
bitclock-master = <&rsnd_endpoint1>;
|
||||
frame-master = <&rsnd_endpoint1>;
|
||||
|
||||
playback = <&ssi2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sound_card {
|
||||
dais = <&rsnd_port0 /* ak4613 */
|
||||
&rsnd_port1>; /* HDMI0 */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board
|
||||
* Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board with R-Car M3-W
|
||||
*
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
* Copyright (C) 2016 Cogent Embedded, Inc.
|
||||
|
|
|
|||
|
|
@ -16,17 +16,6 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
i2c5 = &i2c5;
|
||||
i2c6 = &i2c6;
|
||||
i2c7 = &i2c_dvfs;
|
||||
};
|
||||
|
||||
/*
|
||||
* The external audio clocks are configured as 0 Hz fixed frequency
|
||||
* clocks by default.
|
||||
|
|
@ -57,24 +46,25 @@
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cluster0_opp: opp_table0 {
|
||||
cluster0_opp: opp-table-0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
opp-microvolt = <820000>;
|
||||
opp-microvolt = <830000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt = <820000>;
|
||||
opp-microvolt = <830000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1500000000 {
|
||||
opp-hz = /bits/ 64 <1500000000>;
|
||||
opp-microvolt = <820000>;
|
||||
opp-microvolt = <830000>;
|
||||
clock-latency-ns = <300000>;
|
||||
opp-suspend;
|
||||
};
|
||||
opp-1600000000 {
|
||||
opp-hz = /bits/ 64 <1600000000>;
|
||||
|
|
@ -96,7 +86,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
cluster1_opp: opp_table1 {
|
||||
cluster1_opp: opp-table-1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
|
|
@ -333,6 +323,7 @@
|
|||
compatible = "renesas,r8a7796-wdt",
|
||||
"renesas,rcar-gen3-wdt";
|
||||
reg = <0 0xe6020000 0 0x0c>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 402>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 402>;
|
||||
|
|
@ -459,7 +450,7 @@
|
|||
resets = <&cpg 905>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
pfc: pinctrl@e6060000 {
|
||||
compatible = "renesas,pfc-r8a7796";
|
||||
reg = <0 0xe6060000 0 0x50c>;
|
||||
};
|
||||
|
|
@ -585,6 +576,71 @@
|
|||
resets = <&cpg 407>;
|
||||
};
|
||||
|
||||
tmu0: timer@e61e0000 {
|
||||
compatible = "renesas,tmu-r8a7796", "renesas,tmu";
|
||||
reg = <0 0xe61e0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 125>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 125>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu1: timer@e6fc0000 {
|
||||
compatible = "renesas,tmu-r8a7796", "renesas,tmu";
|
||||
reg = <0 0xe6fc0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 124>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 124>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu2: timer@e6fd0000 {
|
||||
compatible = "renesas,tmu-r8a7796", "renesas,tmu";
|
||||
reg = <0 0xe6fd0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 123>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 123>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu3: timer@e6fe0000 {
|
||||
compatible = "renesas,tmu-r8a7796", "renesas,tmu";
|
||||
reg = <0 0xe6fe0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 122>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 122>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu4: timer@ffc00000 {
|
||||
compatible = "renesas,tmu-r8a7796", "renesas,tmu";
|
||||
reg = <0 0xffc00000 0 0x30>;
|
||||
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 121>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 121>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -862,6 +918,15 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
arm_cc630p: crypto@e6601000 {
|
||||
compatible = "arm,cryptocell-630p-ree";
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x0 0xe6601000 0 0x1000>;
|
||||
clocks = <&cpg CPG_MOD 229>;
|
||||
resets = <&cpg 229>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
compatible = "renesas,dmac-r8a7796",
|
||||
"renesas,rcar-dmac";
|
||||
|
|
@ -988,7 +1053,7 @@
|
|||
<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
|
||||
};
|
||||
|
||||
ipmmu_ds0: mmu@e6740000 {
|
||||
ipmmu_ds0: iommu@e6740000 {
|
||||
compatible = "renesas,ipmmu-r8a7796";
|
||||
reg = <0 0xe6740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 0>;
|
||||
|
|
@ -996,7 +1061,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_ds1: mmu@e7740000 {
|
||||
ipmmu_ds1: iommu@e7740000 {
|
||||
compatible = "renesas,ipmmu-r8a7796";
|
||||
reg = <0 0xe7740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 1>;
|
||||
|
|
@ -1004,7 +1069,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_hc: mmu@e6570000 {
|
||||
ipmmu_hc: iommu@e6570000 {
|
||||
compatible = "renesas,ipmmu-r8a7796";
|
||||
reg = <0 0xe6570000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 2>;
|
||||
|
|
@ -1012,7 +1077,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_ir: mmu@ff8b0000 {
|
||||
ipmmu_ir: iommu@ff8b0000 {
|
||||
compatible = "renesas,ipmmu-r8a7796";
|
||||
reg = <0 0xff8b0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 3>;
|
||||
|
|
@ -1020,7 +1085,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_mm: mmu@e67b0000 {
|
||||
ipmmu_mm: iommu@e67b0000 {
|
||||
compatible = "renesas,ipmmu-r8a7796";
|
||||
reg = <0 0xe67b0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
@ -1029,7 +1094,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_mp: mmu@ec670000 {
|
||||
ipmmu_mp: iommu@ec670000 {
|
||||
compatible = "renesas,ipmmu-r8a7796";
|
||||
reg = <0 0xec670000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 4>;
|
||||
|
|
@ -1037,7 +1102,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_pv0: mmu@fd800000 {
|
||||
ipmmu_pv0: iommu@fd800000 {
|
||||
compatible = "renesas,ipmmu-r8a7796";
|
||||
reg = <0 0xfd800000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 5>;
|
||||
|
|
@ -1045,7 +1110,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_pv1: mmu@fd950000 {
|
||||
ipmmu_pv1: iommu@fd950000 {
|
||||
compatible = "renesas,ipmmu-r8a7796";
|
||||
reg = <0 0xfd950000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 6>;
|
||||
|
|
@ -1053,7 +1118,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_rt: mmu@ffc80000 {
|
||||
ipmmu_rt: iommu@ffc80000 {
|
||||
compatible = "renesas,ipmmu-r8a7796";
|
||||
reg = <0 0xffc80000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 7>;
|
||||
|
|
@ -1061,7 +1126,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vc0: mmu@fe6b0000 {
|
||||
ipmmu_vc0: iommu@fe6b0000 {
|
||||
compatible = "renesas,ipmmu-r8a7796";
|
||||
reg = <0 0xfe6b0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 8>;
|
||||
|
|
@ -1069,7 +1134,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vi0: mmu@febd0000 {
|
||||
ipmmu_vi0: iommu@febd0000 {
|
||||
compatible = "renesas,ipmmu-r8a7796";
|
||||
reg = <0 0xfebd0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 9>;
|
||||
|
|
@ -1114,9 +1179,12 @@
|
|||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii";
|
||||
rx-internal-delay-ps = <0>;
|
||||
tx-internal-delay-ps = <0>;
|
||||
iommus = <&ipmmu_ds0 16>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -1161,6 +1229,7 @@
|
|||
reg = <0 0xe66c0000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch_int", "g_int";
|
||||
clocks = <&cpg CPG_MOD 914>,
|
||||
<&cpg CPG_CORE R8A7796_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
|
|
@ -1812,12 +1881,12 @@
|
|||
* clkout : #clock-cells = <0>; <&rcar_sound>;
|
||||
* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
|
||||
*/
|
||||
compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3";
|
||||
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
||||
<0 0xec5a0000 0 0x100>, /* ADG */
|
||||
<0 0xec540000 0 0x1000>, /* SSIU */
|
||||
<0 0xec541000 0 0x280>, /* SSI */
|
||||
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
|
||||
compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3";
|
||||
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
||||
<0 0xec5a0000 0 0x100>, /* ADG */
|
||||
<0 0xec540000 0 0x1000>, /* SSIU */
|
||||
<0 0xec541000 0 0x280>, /* SSI */
|
||||
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
|
||||
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
|
||||
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
|
|
@ -2124,7 +2193,7 @@
|
|||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu40: ssiu-32 {
|
||||
dmas = <&audma0 0x71>, <&audma1 0x72>;
|
||||
dmas = <&audma0 0x71>, <&audma1 0x72>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu41: ssiu-33 {
|
||||
|
|
@ -2206,6 +2275,18 @@
|
|||
};
|
||||
};
|
||||
|
||||
mlp: mlp@ec520000 {
|
||||
compatible = "renesas,r8a7796-mlp",
|
||||
"renesas,rcar-gen3-mlp";
|
||||
reg = <0 0xec520000 0 0x800>;
|
||||
interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 802>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 802>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
audma0: dma-controller@ec700000 {
|
||||
compatible = "renesas,dmac-r8a7796",
|
||||
"renesas,rcar-dmac";
|
||||
|
|
@ -2385,12 +2466,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
sdhi0: mmc@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a7796",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee100000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7796_CLK_SD0H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
|
|
@ -2398,12 +2480,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi1: sd@ee120000 {
|
||||
sdhi1: mmc@ee120000 {
|
||||
compatible = "renesas,sdhi-r8a7796",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee120000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 313>;
|
||||
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7796_CLK_SD1H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 313>;
|
||||
|
|
@ -2411,12 +2494,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi2: sd@ee140000 {
|
||||
sdhi2: mmc@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a7796",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7796_CLK_SD2H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 312>;
|
||||
|
|
@ -2424,12 +2508,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi3: sd@ee160000 {
|
||||
sdhi3: mmc@ee160000 {
|
||||
compatible = "renesas,sdhi-r8a7796",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee160000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 311>;
|
||||
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7796_CLK_SD3H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 311>;
|
||||
|
|
@ -2437,6 +2522,22 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
rpc: spi@ee200000 {
|
||||
compatible = "renesas,r8a7796-rpc-if",
|
||||
"renesas,rcar-gen3-rpc-if";
|
||||
reg = <0 0xee200000 0 0x200>,
|
||||
<0 0x08000000 0 0x04000000>,
|
||||
<0 0xee208000 0 0x100>;
|
||||
reg-names = "regs", "dirmap", "wbuf";
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
@ -2685,6 +2786,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -2740,6 +2845,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -2818,13 +2927,14 @@
|
|||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>;
|
||||
clock-names = "du.0", "du.1", "du.2";
|
||||
resets = <&cpg 724>, <&cpg 722>;
|
||||
reset-names = "du.0", "du.2";
|
||||
|
||||
renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>;
|
||||
vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
|
||||
renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -2834,8 +2944,6 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb: endpoint {
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
|
@ -2872,8 +2980,6 @@
|
|||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -2885,7 +2991,7 @@
|
|||
};
|
||||
|
||||
thermal-zones {
|
||||
sensor_thermal1: sensor-thermal1 {
|
||||
sensor1_thermal: sensor1-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 0>;
|
||||
|
|
@ -2900,7 +3006,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
sensor_thermal2: sensor-thermal2 {
|
||||
sensor2_thermal: sensor2-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 1>;
|
||||
|
|
@ -2915,7 +3021,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
sensor_thermal3: sensor-thermal3 {
|
||||
sensor3_thermal: sensor3-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 2>;
|
||||
|
|
|
|||
|
|
@ -30,48 +30,3 @@
|
|||
clock-names = "du.0", "du.1", "du.3",
|
||||
"dclkin.0", "dclkin.1", "dclkin.3";
|
||||
};
|
||||
|
||||
&hdmi0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
rcar_dw_hdmi0_out: endpoint {
|
||||
remote-endpoint = <&hdmi0_con>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dw_hdmi0_snd_in: endpoint {
|
||||
remote-endpoint = <&rsnd_endpoint1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi0_con {
|
||||
remote-endpoint = <&rcar_dw_hdmi0_out>;
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
ports {
|
||||
rsnd_port1: port@1 {
|
||||
reg = <1>;
|
||||
rsnd_endpoint1: endpoint {
|
||||
remote-endpoint = <&dw_hdmi0_snd_in>;
|
||||
|
||||
dai-format = "i2s";
|
||||
bitclock-master = <&rsnd_endpoint1>;
|
||||
frame-master = <&rsnd_endpoint1>;
|
||||
|
||||
playback = <&ssi2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sound_card {
|
||||
dais = <&rsnd_port0 /* ak4613 */
|
||||
&rsnd_port1>; /* HDMI0 */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the M3NULCB (R-Car Starter Kit Pro) board
|
||||
* Device Tree Source for the M3NULCB (R-Car Starter Kit Pro) board with R-Car M3-N
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
* Copyright (C) 2018 Cogent Embedded, Inc.
|
||||
|
|
|
|||
|
|
@ -14,22 +14,13 @@
|
|||
|
||||
#define CPG_AUDIO_CLK_I R8A77965_CLK_S0D4
|
||||
|
||||
#define SOC_HAS_SATA
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a77965";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
i2c5 = &i2c5;
|
||||
i2c6 = &i2c6;
|
||||
i2c7 = &i2c_dvfs;
|
||||
};
|
||||
|
||||
/*
|
||||
* The external audio clocks are configured as 0 Hz fixed frequency
|
||||
* clocks by default.
|
||||
|
|
@ -60,7 +51,7 @@
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cluster0_opp: opp_table0 {
|
||||
cluster0_opp: opp-table-0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
|
|
@ -111,6 +102,7 @@
|
|||
power-domains = <&sysc R8A77965_PD_CA57_CPU0>;
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
#cooling-cells = <2>;
|
||||
dynamic-power-coefficient = <854>;
|
||||
clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
|
||||
|
|
@ -124,6 +116,7 @@
|
|||
power-domains = <&sysc R8A77965_PD_CA57_CPU1>;
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
|
|
@ -134,6 +127,19 @@
|
|||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
CPU_SLEEP_0: cpu-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <400>;
|
||||
exit-latency-us = <500>;
|
||||
min-residency-us = <4000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
extal_clk: extal {
|
||||
|
|
@ -188,6 +194,7 @@
|
|||
compatible = "renesas,r8a77965-wdt",
|
||||
"renesas,rcar-gen3-wdt";
|
||||
reg = <0 0xe6020000 0 0x0c>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 402>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 402>;
|
||||
|
|
@ -314,7 +321,7 @@
|
|||
resets = <&cpg 905>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
pfc: pinctrl@e6060000 {
|
||||
compatible = "renesas,pfc-r8a77965";
|
||||
reg = <0 0xe6060000 0 0x50c>;
|
||||
};
|
||||
|
|
@ -440,6 +447,71 @@
|
|||
resets = <&cpg 407>;
|
||||
};
|
||||
|
||||
tmu0: timer@e61e0000 {
|
||||
compatible = "renesas,tmu-r8a77965", "renesas,tmu";
|
||||
reg = <0 0xe61e0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 125>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 125>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu1: timer@e6fc0000 {
|
||||
compatible = "renesas,tmu-r8a77965", "renesas,tmu";
|
||||
reg = <0 0xe6fc0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 124>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 124>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu2: timer@e6fd0000 {
|
||||
compatible = "renesas,tmu-r8a77965", "renesas,tmu";
|
||||
reg = <0 0xe6fd0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 123>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 123>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu3: timer@e6fe0000 {
|
||||
compatible = "renesas,tmu-r8a77965", "renesas,tmu";
|
||||
reg = <0 0xe6fe0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 122>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 122>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu4: timer@ffc00000 {
|
||||
compatible = "renesas,tmu-r8a77965", "renesas,tmu";
|
||||
reg = <0 0xffc00000 0 0x30>;
|
||||
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 121>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 121>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -717,6 +789,15 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
arm_cc630p: crypto@e6601000 {
|
||||
compatible = "arm,cryptocell-630p-ree";
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x0 0xe6601000 0 0x1000>;
|
||||
clocks = <&cpg CPG_MOD 229>;
|
||||
resets = <&cpg 229>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
compatible = "renesas,dmac-r8a77965",
|
||||
"renesas,rcar-dmac";
|
||||
|
|
@ -843,7 +924,7 @@
|
|||
<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
|
||||
};
|
||||
|
||||
ipmmu_ds0: mmu@e6740000 {
|
||||
ipmmu_ds0: iommu@e6740000 {
|
||||
compatible = "renesas,ipmmu-r8a77965";
|
||||
reg = <0 0xe6740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 0>;
|
||||
|
|
@ -851,7 +932,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_ds1: mmu@e7740000 {
|
||||
ipmmu_ds1: iommu@e7740000 {
|
||||
compatible = "renesas,ipmmu-r8a77965";
|
||||
reg = <0 0xe7740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 1>;
|
||||
|
|
@ -859,7 +940,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_hc: mmu@e6570000 {
|
||||
ipmmu_hc: iommu@e6570000 {
|
||||
compatible = "renesas,ipmmu-r8a77965";
|
||||
reg = <0 0xe6570000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 2>;
|
||||
|
|
@ -867,7 +948,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_mm: mmu@e67b0000 {
|
||||
ipmmu_mm: iommu@e67b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77965";
|
||||
reg = <0 0xe67b0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
@ -876,7 +957,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_mp: mmu@ec670000 {
|
||||
ipmmu_mp: iommu@ec670000 {
|
||||
compatible = "renesas,ipmmu-r8a77965";
|
||||
reg = <0 0xec670000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 4>;
|
||||
|
|
@ -884,7 +965,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_pv0: mmu@fd800000 {
|
||||
ipmmu_pv0: iommu@fd800000 {
|
||||
compatible = "renesas,ipmmu-r8a77965";
|
||||
reg = <0 0xfd800000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 6>;
|
||||
|
|
@ -892,7 +973,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_rt: mmu@ffc80000 {
|
||||
ipmmu_rt: iommu@ffc80000 {
|
||||
compatible = "renesas,ipmmu-r8a77965";
|
||||
reg = <0 0xffc80000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 10>;
|
||||
|
|
@ -900,7 +981,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vc0: mmu@fe6b0000 {
|
||||
ipmmu_vc0: iommu@fe6b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77965";
|
||||
reg = <0 0xfe6b0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 12>;
|
||||
|
|
@ -908,7 +989,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vi0: mmu@febd0000 {
|
||||
ipmmu_vi0: iommu@febd0000 {
|
||||
compatible = "renesas,ipmmu-r8a77965";
|
||||
reg = <0 0xfebd0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 14>;
|
||||
|
|
@ -916,7 +997,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vp0: mmu@fe990000 {
|
||||
ipmmu_vp0: iommu@fe990000 {
|
||||
compatible = "renesas,ipmmu-r8a77965";
|
||||
reg = <0 0xfe990000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 16>;
|
||||
|
|
@ -961,9 +1042,12 @@
|
|||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii";
|
||||
rx-internal-delay-ps = <0>;
|
||||
tx-internal-delay-ps = <0>;
|
||||
iommus = <&ipmmu_ds0 16>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -1008,6 +1092,7 @@
|
|||
reg = <0 0xe66c0000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch_int", "g_int";
|
||||
clocks = <&cpg CPG_MOD 914>,
|
||||
<&cpg CPG_CORE R8A77965_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
|
|
@ -1526,6 +1611,126 @@
|
|||
};
|
||||
};
|
||||
|
||||
drif00: rif@e6f40000 {
|
||||
compatible = "renesas,r8a77965-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f40000 0 0x84>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 515>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x20>, <&dmac2 0x20>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 515>;
|
||||
renesas,bonding = <&drif01>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif01: rif@e6f50000 {
|
||||
compatible = "renesas,r8a77965-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f50000 0 0x84>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 514>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x22>, <&dmac2 0x22>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 514>;
|
||||
renesas,bonding = <&drif00>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif10: rif@e6f60000 {
|
||||
compatible = "renesas,r8a77965-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f60000 0 0x84>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 513>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x24>, <&dmac2 0x24>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 513>;
|
||||
renesas,bonding = <&drif11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif11: rif@e6f70000 {
|
||||
compatible = "renesas,r8a77965-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f70000 0 0x84>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 512>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x26>, <&dmac2 0x26>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 512>;
|
||||
renesas,bonding = <&drif10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif20: rif@e6f80000 {
|
||||
compatible = "renesas,r8a77965-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f80000 0 0x84>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 511>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x28>, <&dmac2 0x28>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 511>;
|
||||
renesas,bonding = <&drif21>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif21: rif@e6f90000 {
|
||||
compatible = "renesas,r8a77965-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f90000 0 0x84>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 510>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 510>;
|
||||
renesas,bonding = <&drif20>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif30: rif@e6fa0000 {
|
||||
compatible = "renesas,r8a77965-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6fa0000 0 0x84>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 509>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 509>;
|
||||
renesas,bonding = <&drif31>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif31: rif@e6fb0000 {
|
||||
compatible = "renesas,r8a77965-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6fb0000 0 0x84>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 508>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 508>;
|
||||
renesas,bonding = <&drif30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rcar_sound: sound@ec500000 {
|
||||
/*
|
||||
* #sound-dai-cells is required
|
||||
|
|
@ -1539,12 +1744,12 @@
|
|||
* clkout : #clock-cells = <0>; <&rcar_sound>;
|
||||
* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
|
||||
*/
|
||||
compatible = "renesas,rcar_sound-r8a77965", "renesas,rcar_sound-gen3";
|
||||
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
||||
<0 0xec5a0000 0 0x100>, /* ADG */
|
||||
<0 0xec540000 0 0x1000>, /* SSIU */
|
||||
<0 0xec541000 0 0x280>, /* SSI */
|
||||
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
|
||||
compatible = "renesas,rcar_sound-r8a77965", "renesas,rcar_sound-gen3";
|
||||
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
||||
<0 0xec5a0000 0 0x100>, /* ADG */
|
||||
<0 0xec540000 0 0x1000>, /* SSIU */
|
||||
<0 0xec541000 0 0x280>, /* SSI */
|
||||
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
|
||||
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
|
||||
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
|
|
@ -1798,7 +2003,7 @@
|
|||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu40: ssiu-32 {
|
||||
dmas = <&audma0 0x71>, <&audma1 0x72>;
|
||||
dmas = <&audma0 0x71>, <&audma1 0x72>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu41: ssiu-33 {
|
||||
|
|
@ -1933,6 +2138,18 @@
|
|||
};
|
||||
};
|
||||
|
||||
mlp: mlp@ec520000 {
|
||||
compatible = "renesas,r8a77965-mlp",
|
||||
"renesas,rcar-gen3-mlp";
|
||||
reg = <0 0xec520000 0 0x800>;
|
||||
interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 802>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 802>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
audma0: dma-controller@ec700000 {
|
||||
compatible = "renesas,dmac-r8a77965",
|
||||
"renesas,rcar-dmac";
|
||||
|
|
@ -2096,12 +2313,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
sdhi0: mmc@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a77965",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee100000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77965_CLK_SD0H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
|
|
@ -2109,12 +2327,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi1: sd@ee120000 {
|
||||
sdhi1: mmc@ee120000 {
|
||||
compatible = "renesas,sdhi-r8a77965",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee120000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 313>;
|
||||
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77965_CLK_SD1H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 313>;
|
||||
|
|
@ -2122,12 +2341,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi2: sd@ee140000 {
|
||||
sdhi2: mmc@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a77965",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77965_CLK_SD2H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 312>;
|
||||
|
|
@ -2135,12 +2355,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi3: sd@ee160000 {
|
||||
sdhi3: mmc@ee160000 {
|
||||
compatible = "renesas,sdhi-r8a77965",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee160000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 311>;
|
||||
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77965_CLK_SD3H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 311>;
|
||||
|
|
@ -2148,6 +2369,22 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
rpc: spi@ee200000 {
|
||||
compatible = "renesas,r8a77965-rpc-if",
|
||||
"renesas,rcar-gen3-rpc-if";
|
||||
reg = <0 0xee200000 0 0x200>,
|
||||
<0 0x08000000 0 0x04000000>,
|
||||
<0 0xee208000 0 0x100>;
|
||||
reg-names = "regs", "dirmap", "wbuf";
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata: sata@ee300000 {
|
||||
compatible = "renesas,sata-r8a77965",
|
||||
"renesas,rcar-gen3-sata";
|
||||
|
|
@ -2364,6 +2601,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -2419,6 +2660,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -2494,13 +2739,14 @@
|
|||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 721>;
|
||||
clock-names = "du.0", "du.1", "du.3";
|
||||
resets = <&cpg 724>, <&cpg 722>;
|
||||
reset-names = "du.0", "du.3";
|
||||
|
||||
renesas,cmms = <&cmm0>, <&cmm1>, <&cmm3>;
|
||||
vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
|
||||
renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -2510,8 +2756,6 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb: endpoint {
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
|
@ -2548,8 +2792,6 @@
|
|||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -2561,7 +2803,7 @@
|
|||
};
|
||||
|
||||
thermal-zones {
|
||||
sensor_thermal1: sensor-thermal1 {
|
||||
sensor1_thermal: sensor1-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 0>;
|
||||
|
|
@ -2576,7 +2818,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
sensor_thermal2: sensor-thermal2 {
|
||||
sensor2_thermal: sensor2-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 1>;
|
||||
|
|
@ -2591,7 +2833,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
sensor_thermal3: sensor-thermal3 {
|
||||
sensor3_thermal: sensor3-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 2>;
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the Eagle board
|
||||
* Device Tree Source for the Eagle board with R-Car V3M
|
||||
*
|
||||
* Copyright (C) 2016-2017 Renesas Electronics Corp.
|
||||
* Copyright (C) 2017 Cogent Embedded, Inc.
|
||||
|
|
@ -8,12 +8,18 @@
|
|||
|
||||
/dts-v1/;
|
||||
#include "r8a77970.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Renesas Eagle board based on r8a77970";
|
||||
compatible = "renesas,eagle", "renesas,r8a77970";
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
serial0 = &scif0;
|
||||
ethernet0 = &avb;
|
||||
};
|
||||
|
|
@ -73,6 +79,12 @@
|
|||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x38000000>;
|
||||
};
|
||||
|
||||
x1_clk: x1-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
};
|
||||
|
||||
&avb {
|
||||
|
|
@ -81,14 +93,18 @@
|
|||
|
||||
renesas,no-ether-link;
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
rx-internal-delay-ps = <1800>;
|
||||
tx-internal-delay-ps = <2000>;
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id0022.1622",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
rxc-skew-ps = <1500>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -102,7 +118,23 @@
|
|||
};
|
||||
};
|
||||
|
||||
&csi40 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
csi40_in: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
remote-endpoint = <&max9286_out0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
clocks = <&cpg CPG_MOD 724>, <&x1_clk>;
|
||||
clock-names = "du.0", "dclkin.0";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -137,8 +169,6 @@
|
|||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -161,6 +191,89 @@
|
|||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-0 = <&i2c3_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
gmsl0: gmsl-deserializer@48 {
|
||||
compatible = "maxim,max9286";
|
||||
reg = <0x48>;
|
||||
|
||||
maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
|
||||
enable-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
max9286_out0: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
remote-endpoint = <&csi40_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c-mux {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lvds0 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -189,12 +302,84 @@
|
|||
function = "i2c0";
|
||||
};
|
||||
|
||||
i2c3_pins: i2c3 {
|
||||
groups = "i2c3_a";
|
||||
function = "i2c3";
|
||||
};
|
||||
|
||||
qspi0_pins: qspi0 {
|
||||
groups = "qspi0_ctrl", "qspi0_data4";
|
||||
function = "qspi0";
|
||||
};
|
||||
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data";
|
||||
function = "scif0";
|
||||
};
|
||||
};
|
||||
|
||||
&rpc {
|
||||
pinctrl-0 = <&qspi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "spansion,s25fs512s", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
bootparam@0 {
|
||||
reg = <0x00000000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
cr7@40000 {
|
||||
reg = <0x00040000 0x080000>;
|
||||
read-only;
|
||||
};
|
||||
cert_header_sa3@c0000 {
|
||||
reg = <0x000c0000 0x080000>;
|
||||
read-only;
|
||||
};
|
||||
bl2@140000 {
|
||||
reg = <0x00140000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
cert_header_sa6@180000 {
|
||||
reg = <0x00180000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
bl31@1c0000 {
|
||||
reg = <0x001c0000 0x460000>;
|
||||
read-only;
|
||||
};
|
||||
uboot@640000 {
|
||||
reg = <0x00640000 0x0c0000>;
|
||||
read-only;
|
||||
};
|
||||
uboot-env@700000 {
|
||||
reg = <0x00700000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
dtb@740000 {
|
||||
reg = <0x00740000 0x080000>;
|
||||
};
|
||||
kernel@7c0000 {
|
||||
reg = <0x007c0000 0x1400000>;
|
||||
};
|
||||
user@1bc0000 {
|
||||
reg = <0x01bc0000 0x2440000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rwdt {
|
||||
timeout-sec = <60>;
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -16,14 +16,6 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
};
|
||||
|
||||
/* External CAN clock - to be overridden by boards that provide it */
|
||||
can_clk: can {
|
||||
compatible = "fixed-clock";
|
||||
|
|
@ -108,6 +100,7 @@
|
|||
compatible = "renesas,r8a77970-wdt",
|
||||
"renesas,rcar-gen3-wdt";
|
||||
reg = <0 0xe6020000 0 0x0c>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 402>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 402>;
|
||||
|
|
@ -204,7 +197,7 @@
|
|||
resets = <&cpg 907>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
pfc: pinctrl@e6060000 {
|
||||
compatible = "renesas,pfc-r8a77970";
|
||||
reg = <0 0xe6060000 0 0x504>;
|
||||
};
|
||||
|
|
@ -556,6 +549,7 @@
|
|||
reg = <0 0xe66c0000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch_int", "g_int";
|
||||
clocks = <&cpg CPG_MOD 914>,
|
||||
<&cpg CPG_CORE R8A77970_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
|
|
@ -612,9 +606,12 @@
|
|||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii";
|
||||
rx-internal-delay-ps = <0>;
|
||||
tx-internal-delay-ps = <0>;
|
||||
iommus = <&ipmmu_rt 3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -985,7 +982,7 @@
|
|||
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
|
||||
};
|
||||
|
||||
ipmmu_ds1: mmu@e7740000 {
|
||||
ipmmu_ds1: iommu@e7740000 {
|
||||
compatible = "renesas,ipmmu-r8a77970";
|
||||
reg = <0 0xe7740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 0>;
|
||||
|
|
@ -993,7 +990,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_ir: mmu@ff8b0000 {
|
||||
ipmmu_ir: iommu@ff8b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77970";
|
||||
reg = <0 0xff8b0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 3>;
|
||||
|
|
@ -1001,7 +998,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_mm: mmu@e67b0000 {
|
||||
ipmmu_mm: iommu@e67b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77970";
|
||||
reg = <0 0xe67b0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
@ -1010,7 +1007,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_rt: mmu@ffc80000 {
|
||||
ipmmu_rt: iommu@ffc80000 {
|
||||
compatible = "renesas,ipmmu-r8a77970";
|
||||
reg = <0 0xffc80000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 7>;
|
||||
|
|
@ -1018,7 +1015,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vi0: mmu@febd0000 {
|
||||
ipmmu_vi0: iommu@febd0000 {
|
||||
compatible = "renesas,ipmmu-r8a77970";
|
||||
reg = <0 0xfebd0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 9>;
|
||||
|
|
@ -1039,6 +1036,22 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
rpc: spi@ee200000 {
|
||||
compatible = "renesas,r8a77970-rpc-if",
|
||||
"renesas,rcar-gen3-rpc-if";
|
||||
reg = <0 0xee200000 0 0x200>,
|
||||
<0 0x08000000 0 0x4000000>,
|
||||
<0 0xee208000 0 0x100>;
|
||||
reg-names = "regs", "dirmap", "wbuf";
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
@ -1087,6 +1100,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -1121,7 +1138,9 @@
|
|||
clock-names = "du.0";
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 724>;
|
||||
vsps = <&vspd0 0>;
|
||||
reset-names = "du.0";
|
||||
renesas,vsps = <&vspd0 0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
|
|
@ -1130,8 +1149,6 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
|
|
@ -1164,8 +1181,6 @@
|
|||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the Condor board
|
||||
* Device Tree Source for the Condor board with R-Car V3H
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
* Copyright (C) 2018 Cogent Embedded, Inc.
|
||||
|
|
@ -8,279 +8,9 @@
|
|||
|
||||
/dts-v1/;
|
||||
#include "r8a77980.dtsi"
|
||||
#include "condor-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Renesas Condor board based on r8a77980";
|
||||
compatible = "renesas,condor", "renesas,r8a77980";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif0;
|
||||
ethernet0 = &gether;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
d1_8v: regulator-2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "D1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
d3_3v: regulator-0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "D3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds-decoder {
|
||||
compatible = "thine,thc63lvd1024";
|
||||
vcc-supply = <&d3_3v>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
thc63lvd1024_in: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
thc63lvd1024_out: endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0 0x48000000 0 0x78000000>;
|
||||
};
|
||||
|
||||
vddq_vin01: regulator-1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDDQ_VIN01";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
x1_clk: x1-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
};
|
||||
|
||||
&canfd {
|
||||
pinctrl-0 = <&canfd0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
channel0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&x1_clk>;
|
||||
clock-names = "du.0", "dclkin.0";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <16666666>;
|
||||
};
|
||||
|
||||
&extalr_clk {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
&gether {
|
||||
pinctrl-0 = <&gether_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <&phy0>;
|
||||
renesas,no-ether-link;
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
rxc-skew-ps = <1500>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
io_expander0: gpio@20 {
|
||||
compatible = "onnn,pca9654";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
io_expander1: gpio@21 {
|
||||
compatible = "onnn,pca9654";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
hdmi@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
|
||||
avdd-supply = <&d1_8v>;
|
||||
dvdd-supply = <&d1_8v>;
|
||||
pvdd-supply = <&d1_8v>;
|
||||
bgvdd-supply = <&d1_8v>;
|
||||
dvdd-3v-supply = <&d3_3v>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lvds0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
pinctrl-0 = <&mmc_pins>;
|
||||
pinctrl-1 = <&mmc_pins>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&d3_3v>;
|
||||
vqmmc-supply = <&vddq_vin01>;
|
||||
mmc-hs200-1_8v;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pciec {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_bus_clk {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pfc {
|
||||
canfd0_pins: canfd0 {
|
||||
groups = "canfd0_data_a";
|
||||
function = "canfd0";
|
||||
};
|
||||
|
||||
gether_pins: gether {
|
||||
groups = "gether_mdio_a", "gether_rgmii",
|
||||
"gether_txcrefclk", "gether_txcrefclk_mega";
|
||||
function = "gether";
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
groups = "i2c0";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
mmc_pins: mmc {
|
||||
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
|
||||
function = "mmc";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk_b";
|
||||
function = "scif_clk";
|
||||
};
|
||||
};
|
||||
|
||||
&rwdt {
|
||||
timeout-sec = <60>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -16,15 +16,6 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
i2c5 = &i2c5;
|
||||
};
|
||||
|
||||
/* External CAN clock - to be overridden by boards that provide it */
|
||||
can_clk: can {
|
||||
compatible = "fixed-clock";
|
||||
|
|
@ -138,6 +129,7 @@
|
|||
compatible = "renesas,r8a77980-wdt",
|
||||
"renesas,rcar-gen3-wdt";
|
||||
reg = <0 0xe6020000 0 0x0c>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 402>;
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 402>;
|
||||
|
|
@ -234,7 +226,7 @@
|
|||
resets = <&cpg 907>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
pfc: pinctrl@e6060000 {
|
||||
compatible = "renesas,pfc-r8a77980";
|
||||
reg = <0 0xe6060000 0 0x50c>;
|
||||
};
|
||||
|
|
@ -608,6 +600,7 @@
|
|||
reg = <0 0xe66c0000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch_int", "g_int";
|
||||
clocks = <&cpg CPG_MOD 914>,
|
||||
<&cpg CPG_CORE R8A77980_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
|
|
@ -664,9 +657,12 @@
|
|||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii";
|
||||
rx-internal-delay-ps = <0>;
|
||||
tx-internal-delay-ps = <2000>;
|
||||
iommus = <&ipmmu_ds1 33>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -990,8 +986,8 @@
|
|||
|
||||
reg = <1>;
|
||||
|
||||
vin4csi41: endpoint@2 {
|
||||
reg = <2>;
|
||||
vin4csi41: endpoint@3 {
|
||||
reg = <3>;
|
||||
remote-endpoint = <&csi41vin4>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1018,8 +1014,8 @@
|
|||
|
||||
reg = <1>;
|
||||
|
||||
vin5csi41: endpoint@2 {
|
||||
reg = <2>;
|
||||
vin5csi41: endpoint@3 {
|
||||
reg = <3>;
|
||||
remote-endpoint = <&csi41vin5>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1046,8 +1042,8 @@
|
|||
|
||||
reg = <1>;
|
||||
|
||||
vin6csi41: endpoint@2 {
|
||||
reg = <2>;
|
||||
vin6csi41: endpoint@3 {
|
||||
reg = <3>;
|
||||
remote-endpoint = <&csi41vin6>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1074,8 +1070,8 @@
|
|||
|
||||
reg = <1>;
|
||||
|
||||
vin7csi41: endpoint@2 {
|
||||
reg = <2>;
|
||||
vin7csi41: endpoint@3 {
|
||||
reg = <3>;
|
||||
remote-endpoint = <&csi41vin7>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1266,7 +1262,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_ds1: mmu@e7740000 {
|
||||
ipmmu_ds1: iommu@e7740000 {
|
||||
compatible = "renesas,ipmmu-r8a77980";
|
||||
reg = <0 0xe7740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 0>;
|
||||
|
|
@ -1274,7 +1270,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_ir: mmu@ff8b0000 {
|
||||
ipmmu_ir: iommu@ff8b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77980";
|
||||
reg = <0 0xff8b0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 3>;
|
||||
|
|
@ -1282,7 +1278,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_mm: mmu@e67b0000 {
|
||||
ipmmu_mm: iommu@e67b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77980";
|
||||
reg = <0 0xe67b0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
@ -1291,7 +1287,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_rt: mmu@ffc80000 {
|
||||
ipmmu_rt: iommu@ffc80000 {
|
||||
compatible = "renesas,ipmmu-r8a77980";
|
||||
reg = <0 0xffc80000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 10>;
|
||||
|
|
@ -1299,7 +1295,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vc0: mmu@fe990000 {
|
||||
ipmmu_vc0: iommu@fe990000 {
|
||||
compatible = "renesas,ipmmu-r8a77980";
|
||||
reg = <0 0xfe990000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 12>;
|
||||
|
|
@ -1307,7 +1303,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vi0: mmu@febd0000 {
|
||||
ipmmu_vi0: iommu@febd0000 {
|
||||
compatible = "renesas,ipmmu-r8a77980";
|
||||
reg = <0 0xfebd0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 14>;
|
||||
|
|
@ -1315,16 +1311,18 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vip0: mmu@e7b00000 {
|
||||
ipmmu_vip0: iommu@e7b00000 {
|
||||
compatible = "renesas,ipmmu-r8a77980";
|
||||
reg = <0 0xe7b00000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 4>;
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vip1: mmu@e7960000 {
|
||||
ipmmu_vip1: iommu@e7960000 {
|
||||
compatible = "renesas,ipmmu-r8a77980";
|
||||
reg = <0 0xe7960000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 11>;
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
|
@ -1334,7 +1332,8 @@
|
|||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77980_CLK_SD0H>;
|
||||
clock-names = "core", "clkh";
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
max-frequency = <200000000>;
|
||||
|
|
@ -1342,6 +1341,22 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
rpc: spi@ee200000 {
|
||||
compatible = "renesas,r8a77980-rpc-if",
|
||||
"renesas,rcar-gen3-rpc-if";
|
||||
reg = <0 0xee200000 0 0x200>,
|
||||
<0 0x08000000 0 0x4000000>,
|
||||
<0 0xee208000 0 0x100>;
|
||||
reg-names = "regs", "dirmap", "wbuf";
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
@ -1418,6 +1433,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -1457,6 +1476,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -1484,15 +1507,16 @@
|
|||
};
|
||||
|
||||
du: display@feb00000 {
|
||||
compatible = "renesas,du-r8a77980",
|
||||
"renesas,du-r8a77970";
|
||||
compatible = "renesas,du-r8a77980";
|
||||
reg = <0 0xfeb00000 0 0x80000>;
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>;
|
||||
clock-names = "du.0";
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 724>;
|
||||
vsps = <&vspd0 0>;
|
||||
reset-names = "du.0";
|
||||
renesas,vsps = <&vspd0 0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
|
|
@ -1501,8 +1525,6 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
|
|
@ -1536,8 +1558,6 @@
|
|||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1549,7 +1569,7 @@
|
|||
};
|
||||
|
||||
thermal-zones {
|
||||
thermal-sensor-1 {
|
||||
sensor1_thermal: sensor1-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 0>;
|
||||
|
|
@ -1568,7 +1588,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
thermal-sensor-2 {
|
||||
sensor2_thermal: sensor2-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 1>;
|
||||
|
|
|
|||
|
|
@ -1,754 +1,15 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the ebisu board
|
||||
* Device Tree Source for the Ebisu board with R-Car E3
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a77990.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "ebisu.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Renesas Ebisu board based on r8a77990";
|
||||
compatible = "renesas,ebisu", "renesas,r8a77990";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif2;
|
||||
ethernet0 = &avb;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
audio_clkout: audio-clkout {
|
||||
/*
|
||||
* This is same as <&rcar_sound 0>
|
||||
* but needed to avoid cs2000/rcar_sound probe dead-lock
|
||||
*/
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <11289600>;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm3 0 50000>;
|
||||
|
||||
brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
|
||||
default-brightness-level = <10>;
|
||||
|
||||
power-supply = <®_12p0v>;
|
||||
};
|
||||
|
||||
cvbs-in {
|
||||
compatible = "composite-video-connector";
|
||||
label = "CVBS IN";
|
||||
|
||||
port {
|
||||
cvbs_con: endpoint {
|
||||
remote-endpoint = <&adv7482_ain7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-in {
|
||||
compatible = "hdmi-connector";
|
||||
label = "HDMI IN";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_in_con: endpoint {
|
||||
remote-endpoint = <&adv7482_hdmi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_out: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds-decoder {
|
||||
compatible = "thine,thc63lvd1024";
|
||||
vcc-supply = <®_3p3v>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
thc63lvd1024_in: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
thc63lvd1024_out: endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x38000000>;
|
||||
};
|
||||
|
||||
reg_1p8v: regulator0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_12p0v: regulator2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "D12.0V";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
rsnd_ak4613: sound {
|
||||
compatible = "simple-audio-card";
|
||||
|
||||
simple-audio-card,name = "rsnd-ak4613";
|
||||
simple-audio-card,format = "left_j";
|
||||
simple-audio-card,bitclock-master = <&sndcpu>;
|
||||
simple-audio-card,frame-master = <&sndcpu>;
|
||||
|
||||
sndcodec: simple-audio-card,codec {
|
||||
sound-dai = <&ak4613>;
|
||||
};
|
||||
|
||||
sndcpu: simple-audio-card,cpu {
|
||||
sound-dai = <&rcar_sound>;
|
||||
};
|
||||
};
|
||||
|
||||
vbus0_usb2: regulator-vbus0-usb2 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "USB20_VBUS_CN";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
|
||||
gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI0 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI0 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1>, <1800000 0>;
|
||||
};
|
||||
|
||||
vcc_sdhi1: regulator-vcc-sdhi1 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI1 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi1: regulator-vccq-sdhi1 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI1 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1>, <1800000 0>;
|
||||
};
|
||||
|
||||
vga {
|
||||
compatible = "vga-connector";
|
||||
|
||||
port {
|
||||
vga_in: endpoint {
|
||||
remote-endpoint = <&adv7123_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vga-encoder {
|
||||
compatible = "adi,adv7123";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7123_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7123_out: endpoint {
|
||||
remote-endpoint = <&vga_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
x12_clk: x12 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24576000>;
|
||||
};
|
||||
|
||||
x13_clk: x13 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <74250000>;
|
||||
};
|
||||
};
|
||||
|
||||
&audio_clk_a {
|
||||
clock-frequency = <22579200>;
|
||||
};
|
||||
|
||||
&avb {
|
||||
pinctrl-0 = <&avb_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-handle = <&phy0>;
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
rxc-skew-ps = <1500>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
|
||||
/*
|
||||
* TX clock internal delay mode is required for reliable
|
||||
* 1Gbps communication using the KSZ9031RNX phy present on
|
||||
* the Ebisu board, however, TX clock internal delay mode
|
||||
* isn't supported on r8a77990. Thus, limit speed to
|
||||
* 100Mbps for reliable communication.
|
||||
*/
|
||||
max-speed = <100>;
|
||||
};
|
||||
};
|
||||
|
||||
&canfd {
|
||||
pinctrl-0 = <&canfd0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
channel0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&csi40 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
csi40_in: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
remote-endpoint = <&adv7482_txa>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&x13_clk>;
|
||||
clock-names = "du.0", "du.1", "dclkin.0";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7123_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
&hsusb {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
io_expander: gpio@20 {
|
||||
compatible = "onnn,pca9654";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
hdmi-encoder@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
video-receiver@70 {
|
||||
compatible = "adi,adv7482";
|
||||
reg = <0x70>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupt-names = "intrq1", "intrq2";
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_LOW>,
|
||||
<17 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
port@7 {
|
||||
reg = <7>;
|
||||
|
||||
adv7482_ain7: endpoint {
|
||||
remote-endpoint = <&cvbs_con>;
|
||||
};
|
||||
};
|
||||
|
||||
port@8 {
|
||||
reg = <8>;
|
||||
|
||||
adv7482_hdmi: endpoint {
|
||||
remote-endpoint = <&hdmi_in_con>;
|
||||
};
|
||||
};
|
||||
|
||||
port@a {
|
||||
reg = <10>;
|
||||
|
||||
adv7482_txa: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
remote-endpoint = <&csi40_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
|
||||
ak4613: codec@10 {
|
||||
compatible = "asahi-kasei,ak4613";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x10>;
|
||||
clocks = <&rcar_sound 3>;
|
||||
|
||||
asahi-kasei,in1-single-end;
|
||||
asahi-kasei,in2-single-end;
|
||||
asahi-kasei,out1-single-end;
|
||||
asahi-kasei,out2-single-end;
|
||||
asahi-kasei,out3-single-end;
|
||||
asahi-kasei,out4-single-end;
|
||||
asahi-kasei,out5-single-end;
|
||||
asahi-kasei,out6-single-end;
|
||||
};
|
||||
|
||||
cs2000: clk-multiplier@4f {
|
||||
#clock-cells = <0>;
|
||||
compatible = "cirrus,cs2000-cp";
|
||||
reg = <0x4f>;
|
||||
clocks = <&audio_clkout>, <&x12_clk>;
|
||||
clock-names = "clk_in", "ref_clk";
|
||||
|
||||
assigned-clocks = <&cs2000>;
|
||||
assigned-clock-rates = <24576000>; /* 1/1 divide */
|
||||
};
|
||||
};
|
||||
|
||||
&i2c_dvfs {
|
||||
status = "okay";
|
||||
|
||||
clock-frequency = <400000>;
|
||||
|
||||
pmic: pmic@30 {
|
||||
pinctrl-0 = <&irq0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
compatible = "rohm,bd9571mwv";
|
||||
reg = <0x30>;
|
||||
interrupt-parent = <&intc_ex>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
rohm,ddr-backup-power = <0x1>;
|
||||
rohm,rstbmode-level;
|
||||
};
|
||||
};
|
||||
|
||||
&lvds0 {
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 727>,
|
||||
<&x13_clk>,
|
||||
<&extal_clk>;
|
||||
clock-names = "fck", "dclkin.0", "extal";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lvds1 {
|
||||
/*
|
||||
* Even though the LVDS1 output is not connected, the encoder must be
|
||||
* enabled to supply a pixel clock to the DU for the DPAD output when
|
||||
* LVDS0 is in use.
|
||||
*/
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 727>,
|
||||
<&x13_clk>,
|
||||
<&extal_clk>;
|
||||
clock-names = "fck", "dclkin.0", "extal";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_bus_clk {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&pciec0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pfc {
|
||||
avb_pins: avb {
|
||||
mux {
|
||||
groups = "avb_link", "avb_mii";
|
||||
function = "avb";
|
||||
};
|
||||
};
|
||||
|
||||
canfd0_pins: canfd0 {
|
||||
groups = "canfd0_data";
|
||||
function = "canfd0";
|
||||
};
|
||||
|
||||
du_pins: du {
|
||||
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
|
||||
function = "du";
|
||||
};
|
||||
|
||||
irq0_pins: irq0 {
|
||||
groups = "intc_ex_irq0";
|
||||
function = "intc_ex";
|
||||
};
|
||||
|
||||
pwm3_pins: pwm3 {
|
||||
groups = "pwm3_b";
|
||||
function = "pwm3";
|
||||
};
|
||||
|
||||
pwm5_pins: pwm5 {
|
||||
groups = "pwm5_a";
|
||||
function = "pwm5";
|
||||
};
|
||||
|
||||
scif2_pins: scif2 {
|
||||
groups = "scif2_data_a";
|
||||
function = "scif2";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi0_pins_uhs: sd0_uhs {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi1_pins: sd1 {
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi1_pins_uhs: sd1_uhs {
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi3_pins: sd3 {
|
||||
groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
|
||||
function = "sdhi3";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sound_clk_pins: sound_clk {
|
||||
groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a",
|
||||
"audio_clkout_a", "audio_clkout1_a";
|
||||
function = "audio_clk";
|
||||
};
|
||||
|
||||
sound_pins: sound {
|
||||
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
|
||||
function = "ssi";
|
||||
};
|
||||
|
||||
usb0_pins: usb {
|
||||
groups = "usb0_b", "usb0_id";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
usb30_pins: usb30 {
|
||||
groups = "usb30";
|
||||
function = "usb30";
|
||||
};
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
pinctrl-0 = <&pwm3_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm5 {
|
||||
pinctrl-0 = <&pwm5_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_pins &sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* Single DAI */
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
/* audio_clkout0/1/2/3 */
|
||||
#clock-cells = <1>;
|
||||
clock-frequency = <12288000 11289600>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
/* update <audio_clk_b> to <cs2000> */
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
|
||||
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
|
||||
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
|
||||
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
|
||||
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
|
||||
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
|
||||
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
|
||||
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
|
||||
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
|
||||
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
|
||||
<&audio_clk_a>, <&cs2000>, <&audio_clk_c>,
|
||||
<&cpg CPG_CORE R8A77990_CLK_ZA2>;
|
||||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0 &src0 &dvc0>;
|
||||
capture = <&ssi1 &src1 &dvc1>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&rwdt {
|
||||
timeout-sec = <60>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
pinctrl-0 = <&scif2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-1 = <&sdhi0_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi1 {
|
||||
pinctrl-0 = <&sdhi1_pins>;
|
||||
pinctrl-1 = <&sdhi1_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi1>;
|
||||
vqmmc-supply = <&vccq_sdhi1>;
|
||||
cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi3 {
|
||||
/* used for on-board 8bit eMMC */
|
||||
pinctrl-0 = <&sdhi3_pins>;
|
||||
pinctrl-1 = <&sdhi3_pins>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_1p8v>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
shared-pin;
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vbus-supply = <&vbus0_usb2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_peri0 {
|
||||
companion = <&xhci0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xhci0 {
|
||||
pinctrl-0 = <&usb30_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -14,17 +14,6 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
i2c5 = &i2c5;
|
||||
i2c6 = &i2c6;
|
||||
i2c7 = &i2c7;
|
||||
};
|
||||
|
||||
/*
|
||||
* The external audio clocks are configured as 0 Hz fixed frequency
|
||||
* clocks by default.
|
||||
|
|
@ -55,7 +44,7 @@
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cluster1_opp: opp_table10 {
|
||||
cluster1_opp: opp-table-1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
opp-800000000 {
|
||||
|
|
@ -88,6 +77,7 @@
|
|||
power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
dynamic-power-coefficient = <277>;
|
||||
clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
|
|
@ -100,6 +90,7 @@
|
|||
power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
};
|
||||
|
|
@ -110,6 +101,19 @@
|
|||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
CPU_SLEEP_0: cpu-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <700>;
|
||||
exit-latency-us = <700>;
|
||||
min-residency-us = <5000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
extal_clk: extal {
|
||||
|
|
@ -156,6 +160,7 @@
|
|||
compatible = "renesas,r8a77990-wdt",
|
||||
"renesas,rcar-gen3-wdt";
|
||||
reg = <0 0xe6020000 0 0x0c>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 402>;
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 402>;
|
||||
|
|
@ -267,7 +272,7 @@
|
|||
resets = <&cpg 906>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
pfc: pinctrl@e6060000 {
|
||||
compatible = "renesas,pfc-r8a77990";
|
||||
reg = <0 0xe6060000 0 0x508>;
|
||||
};
|
||||
|
|
@ -275,8 +280,10 @@
|
|||
i2c_dvfs: i2c@e60b0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,iic-r8a77990";
|
||||
reg = <0 0xe60b0000 0 0x15>;
|
||||
compatible = "renesas,iic-r8a77990",
|
||||
"renesas,rcar-gen3-iic",
|
||||
"renesas,rmobile-iic";
|
||||
reg = <0 0xe60b0000 0 0x425>;
|
||||
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 926>;
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
|
|
@ -405,6 +412,71 @@
|
|||
resets = <&cpg 407>;
|
||||
};
|
||||
|
||||
tmu0: timer@e61e0000 {
|
||||
compatible = "renesas,tmu-r8a77990", "renesas,tmu";
|
||||
reg = <0 0xe61e0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 125>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 125>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu1: timer@e6fc0000 {
|
||||
compatible = "renesas,tmu-r8a77990", "renesas,tmu";
|
||||
reg = <0 0xe6fc0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 124>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 124>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu2: timer@e6fd0000 {
|
||||
compatible = "renesas,tmu-r8a77990", "renesas,tmu";
|
||||
reg = <0 0xe6fd0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 123>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 123>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu3: timer@e6fe0000 {
|
||||
compatible = "renesas,tmu-r8a77990", "renesas,tmu";
|
||||
reg = <0 0xe6fe0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 122>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 122>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu4: timer@ffc00000 {
|
||||
compatible = "renesas,tmu-r8a77990", "renesas,tmu";
|
||||
reg = <0 0xffc00000 0 0x30>;
|
||||
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 121>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 121>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -667,6 +739,15 @@
|
|||
dma-channels = <2>;
|
||||
};
|
||||
|
||||
arm_cc630p: crypto@e6601000 {
|
||||
compatible = "arm,cryptocell-630p-ree";
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x0 0xe6601000 0 0x1000>;
|
||||
clocks = <&cpg CPG_MOD 229>;
|
||||
resets = <&cpg 229>;
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
compatible = "renesas,dmac-r8a77990",
|
||||
"renesas,rcar-dmac";
|
||||
|
|
@ -793,7 +874,7 @@
|
|||
<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
|
||||
};
|
||||
|
||||
ipmmu_ds0: mmu@e6740000 {
|
||||
ipmmu_ds0: iommu@e6740000 {
|
||||
compatible = "renesas,ipmmu-r8a77990";
|
||||
reg = <0 0xe6740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 0>;
|
||||
|
|
@ -801,7 +882,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_ds1: mmu@e7740000 {
|
||||
ipmmu_ds1: iommu@e7740000 {
|
||||
compatible = "renesas,ipmmu-r8a77990";
|
||||
reg = <0 0xe7740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 1>;
|
||||
|
|
@ -809,7 +890,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_hc: mmu@e6570000 {
|
||||
ipmmu_hc: iommu@e6570000 {
|
||||
compatible = "renesas,ipmmu-r8a77990";
|
||||
reg = <0 0xe6570000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 2>;
|
||||
|
|
@ -817,7 +898,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_mm: mmu@e67b0000 {
|
||||
ipmmu_mm: iommu@e67b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77990";
|
||||
reg = <0 0xe67b0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
@ -826,7 +907,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_mp: mmu@ec670000 {
|
||||
ipmmu_mp: iommu@ec670000 {
|
||||
compatible = "renesas,ipmmu-r8a77990";
|
||||
reg = <0 0xec670000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 4>;
|
||||
|
|
@ -834,7 +915,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_pv0: mmu@fd800000 {
|
||||
ipmmu_pv0: iommu@fd800000 {
|
||||
compatible = "renesas,ipmmu-r8a77990";
|
||||
reg = <0 0xfd800000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 6>;
|
||||
|
|
@ -842,7 +923,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_rt: mmu@ffc80000 {
|
||||
ipmmu_rt: iommu@ffc80000 {
|
||||
compatible = "renesas,ipmmu-r8a77990";
|
||||
reg = <0 0xffc80000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 10>;
|
||||
|
|
@ -850,7 +931,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vc0: mmu@fe6b0000 {
|
||||
ipmmu_vc0: iommu@fe6b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77990";
|
||||
reg = <0 0xfe6b0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 12>;
|
||||
|
|
@ -858,7 +939,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vi0: mmu@febd0000 {
|
||||
ipmmu_vi0: iommu@febd0000 {
|
||||
compatible = "renesas,ipmmu-r8a77990";
|
||||
reg = <0 0xfebd0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 14>;
|
||||
|
|
@ -866,7 +947,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vp0: mmu@fe990000 {
|
||||
ipmmu_vp0: iommu@fe990000 {
|
||||
compatible = "renesas,ipmmu-r8a77990";
|
||||
reg = <0 0xfe990000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 16>;
|
||||
|
|
@ -911,9 +992,11 @@
|
|||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii";
|
||||
rx-internal-delay-ps = <0>;
|
||||
iommus = <&ipmmu_ds0 16>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -958,6 +1041,7 @@
|
|||
reg = <0 0xe66c0000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch_int", "g_int";
|
||||
clocks = <&cpg CPG_MOD 914>,
|
||||
<&cpg CPG_CORE R8A77990_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
|
|
@ -1168,9 +1252,8 @@
|
|||
reg = <0 0xe6ea0000 0 0x0064>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 210>;
|
||||
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
|
||||
<&dmac2 0x43>, <&dmac2 0x42>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
dmas = <&dmac0 0x43>, <&dmac0 0x42>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 210>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -1230,7 +1313,7 @@
|
|||
|
||||
vin4csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin4>;
|
||||
remote-endpoint = <&csi40vin4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1258,12 +1341,132 @@
|
|||
|
||||
vin5csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin5>;
|
||||
remote-endpoint = <&csi40vin5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
drif00: rif@e6f40000 {
|
||||
compatible = "renesas,r8a77990-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f40000 0 0x84>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 515>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x20>, <&dmac2 0x20>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 515>;
|
||||
renesas,bonding = <&drif01>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif01: rif@e6f50000 {
|
||||
compatible = "renesas,r8a77990-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f50000 0 0x84>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 514>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x22>, <&dmac2 0x22>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 514>;
|
||||
renesas,bonding = <&drif00>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif10: rif@e6f60000 {
|
||||
compatible = "renesas,r8a77990-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f60000 0 0x84>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 513>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x24>, <&dmac2 0x24>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 513>;
|
||||
renesas,bonding = <&drif11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif11: rif@e6f70000 {
|
||||
compatible = "renesas,r8a77990-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f70000 0 0x84>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 512>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac1 0x26>, <&dmac2 0x26>;
|
||||
dma-names = "rx", "rx";
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 512>;
|
||||
renesas,bonding = <&drif10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif20: rif@e6f80000 {
|
||||
compatible = "renesas,r8a77990-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f80000 0 0x84>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 511>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x28>;
|
||||
dma-names = "rx";
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 511>;
|
||||
renesas,bonding = <&drif21>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif21: rif@e6f90000 {
|
||||
compatible = "renesas,r8a77990-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6f90000 0 0x84>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 510>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x2a>;
|
||||
dma-names = "rx";
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 510>;
|
||||
renesas,bonding = <&drif20>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif30: rif@e6fa0000 {
|
||||
compatible = "renesas,r8a77990-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6fa0000 0 0x84>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 509>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x2c>;
|
||||
dma-names = "rx";
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 509>;
|
||||
renesas,bonding = <&drif31>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
drif31: rif@e6fb0000 {
|
||||
compatible = "renesas,r8a77990-drif",
|
||||
"renesas,rcar-gen3-drif";
|
||||
reg = <0 0xe6fb0000 0 0x84>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 508>;
|
||||
clock-names = "fck";
|
||||
dmas = <&dmac0 0x2e>;
|
||||
dma-names = "rx";
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 508>;
|
||||
renesas,bonding = <&drif30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rcar_sound: sound@ec500000 {
|
||||
/*
|
||||
* #sound-dai-cells is required
|
||||
|
|
@ -1277,12 +1480,12 @@
|
|||
* clkout : #clock-cells = <0>; <&rcar_sound>;
|
||||
* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
|
||||
*/
|
||||
compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3";
|
||||
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
||||
<0 0xec5a0000 0 0x100>, /* ADG */
|
||||
<0 0xec540000 0 0x1000>, /* SSIU */
|
||||
<0 0xec541000 0 0x280>, /* SSI */
|
||||
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
|
||||
compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3";
|
||||
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
||||
<0 0xec5a0000 0 0x100>, /* ADG */
|
||||
<0 0xec540000 0 0x1000>, /* SSIU */
|
||||
<0 0xec541000 0 0x280>, /* SSI */
|
||||
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
|
||||
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
|
||||
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
|
|
@ -1470,6 +1673,18 @@
|
|||
};
|
||||
};
|
||||
|
||||
mlp: mlp@ec520000 {
|
||||
compatible = "renesas,r8a77990-mlp",
|
||||
"renesas,rcar-gen3-mlp";
|
||||
reg = <0 0xec520000 0 0x800>;
|
||||
interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 802>;
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 802>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
audma0: dma-controller@ec700000 {
|
||||
compatible = "renesas,dmac-r8a77990",
|
||||
"renesas,rcar-dmac";
|
||||
|
|
@ -1571,12 +1786,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
sdhi0: mmc@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a77990",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee100000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77990_CLK_SD0H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
|
|
@ -1584,12 +1800,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi1: sd@ee120000 {
|
||||
sdhi1: mmc@ee120000 {
|
||||
compatible = "renesas,sdhi-r8a77990",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee120000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 313>;
|
||||
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77990_CLK_SD1H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 313>;
|
||||
|
|
@ -1597,12 +1814,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi3: sd@ee160000 {
|
||||
sdhi3: mmc@ee160000 {
|
||||
compatible = "renesas,sdhi-r8a77990",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee160000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 311>;
|
||||
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77990_CLK_SD3H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 311>;
|
||||
|
|
@ -1610,6 +1828,22 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
rpc: spi@ee200000 {
|
||||
compatible = "renesas,r8a77990-rpc-if",
|
||||
"renesas,rcar-gen3-rpc-if";
|
||||
reg = <0 0xee200000 0 0x200>,
|
||||
<0 0x08000000 0 0x04000000>,
|
||||
<0 0xee208000 0 0x100>;
|
||||
reg-names = "regs", "dirmap", "wbuf";
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
@ -1761,6 +1995,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -1784,14 +2022,13 @@
|
|||
reg = <0 0xfeb00000 0 0x40000>;
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>;
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
|
||||
clock-names = "du.0", "du.1";
|
||||
resets = <&cpg 724>;
|
||||
reset-names = "du.0";
|
||||
|
||||
renesas,cmms = <&cmm0>, <&cmm1>;
|
||||
vsps = <&vspd0 0>, <&vspd1 0>;
|
||||
renesas,vsps = <&vspd0 0>, <&vspd1 0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -1801,8 +2038,6 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
|
|
@ -1844,8 +2079,6 @@
|
|||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1871,8 +2104,6 @@
|
|||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds1_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1887,7 +2118,7 @@
|
|||
cpu-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&thermal 0>;
|
||||
thermal-sensors = <&thermal>;
|
||||
sustainable-power = <717>;
|
||||
|
||||
cooling-maps {
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the Draak board
|
||||
* Device Tree Source for the Draak board with R-Car D3
|
||||
*
|
||||
* Copyright (C) 2016-2018 Renesas Electronics Corp.
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
|
|
@ -8,521 +8,9 @@
|
|||
|
||||
/dts-v1/;
|
||||
#include "r8a77995.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "draak.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Renesas Draak board based on r8a77995";
|
||||
compatible = "renesas,draak", "renesas,r8a77995";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif2;
|
||||
ethernet0 = &avb;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 50000>;
|
||||
|
||||
brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
|
||||
default-brightness-level = <10>;
|
||||
|
||||
power-supply = <®_12p0v>;
|
||||
enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
composite-in {
|
||||
compatible = "composite-video-connector";
|
||||
|
||||
port {
|
||||
composite_con_in: endpoint {
|
||||
remote-endpoint = <&adv7180_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-in {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&adv7612_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_out: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds-decoder {
|
||||
compatible = "thine,thc63lvd1024";
|
||||
vcc-supply = <®_3p3v>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
thc63lvd1024_in: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
thc63lvd1024_out: endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x18000000>;
|
||||
};
|
||||
|
||||
reg_1p8v: regulator-1p8v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_12p0v: regulator-12p0v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "D12.0V";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vga {
|
||||
compatible = "vga-connector";
|
||||
|
||||
port {
|
||||
vga_in: endpoint {
|
||||
remote-endpoint = <&adv7123_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vga-encoder {
|
||||
compatible = "adi,adv7123";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7123_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7123_out: endpoint {
|
||||
remote-endpoint = <&vga_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
x12_clk: x12 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <74250000>;
|
||||
};
|
||||
};
|
||||
|
||||
&avb {
|
||||
pinctrl-0 = <&avb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
renesas,no-ether-link;
|
||||
phy-handle = <&phy0>;
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
rxc-skew-ps = <1500>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
|
||||
/*
|
||||
* TX clock internal delay mode is required for reliable
|
||||
* 1Gbps communication using the KSZ9031RNX phy present on
|
||||
* the Draak board, however, TX clock internal delay mode
|
||||
* isn't supported on r8a77995. Thus, limit speed to
|
||||
* 100Mbps for reliable communication.
|
||||
*/
|
||||
max-speed = <100>;
|
||||
};
|
||||
};
|
||||
|
||||
&can0 {
|
||||
pinctrl-0 = <&can0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can1 {
|
||||
pinctrl-0 = <&can1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&x12_clk>;
|
||||
clock-names = "du.0", "du.1", "dclkin.0";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7123_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
&hsusb {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
composite-in@20 {
|
||||
compatible = "adi,adv7180cp";
|
||||
reg = <0x20>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7180_in: endpoint {
|
||||
remote-endpoint = <&composite_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
|
||||
/*
|
||||
* The VIN4 video input path is shared between
|
||||
* CVBS and HDMI inputs through SW[49-53]
|
||||
* switches.
|
||||
*
|
||||
* CVBS is the default selection, link it to
|
||||
* VIN4 here.
|
||||
*/
|
||||
adv7180_out: endpoint {
|
||||
remote-endpoint = <&vin4_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
hdmi-encoder@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>, <0x3f>, <0x38>, <0x3c>;
|
||||
reg-names = "main", "edid", "packet", "cec";
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
/* Depends on LVDS */
|
||||
max-clock = <135000000>;
|
||||
min-vrefresh = <50>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-decoder@4c {
|
||||
compatible = "adi,adv7612";
|
||||
reg = <0x4c>;
|
||||
default-input = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
adv7612_in: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
/*
|
||||
* The VIN4 video input path is shared between
|
||||
* CVBS and HDMI inputs through SW[49-53]
|
||||
* switches.
|
||||
*
|
||||
* CVBS is the default selection, leave HDMI
|
||||
* not connected here.
|
||||
*/
|
||||
adv7612_out: endpoint {
|
||||
pclk-sample = <0>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "rohm,br24t01", "atmel,24c01";
|
||||
reg = <0x50>;
|
||||
pagesize = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lvds0 {
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 727>,
|
||||
<&x12_clk>,
|
||||
<&extal_clk>;
|
||||
clock-names = "fck", "dclkin.0", "extal";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lvds1 {
|
||||
/*
|
||||
* Even though the LVDS1 output is not connected, the encoder must be
|
||||
* enabled to supply a pixel clock to the DU for the DPAD output when
|
||||
* LVDS0 is in use.
|
||||
*/
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 727>,
|
||||
<&x12_clk>,
|
||||
<&extal_clk>;
|
||||
clock-names = "fck", "dclkin.0", "extal";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pfc {
|
||||
avb0_pins: avb {
|
||||
mux {
|
||||
groups = "avb0_link", "avb0_mdio", "avb0_mii";
|
||||
function = "avb0";
|
||||
};
|
||||
};
|
||||
|
||||
can0_pins: can0 {
|
||||
groups = "can0_data_a";
|
||||
function = "can0";
|
||||
};
|
||||
|
||||
can1_pins: can1 {
|
||||
groups = "can1_data_a";
|
||||
function = "can1";
|
||||
};
|
||||
|
||||
du_pins: du {
|
||||
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
|
||||
function = "du";
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
groups = "i2c0";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1 {
|
||||
groups = "i2c1";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
pwm0_pins: pwm0 {
|
||||
groups = "pwm0_c";
|
||||
function = "pwm0";
|
||||
};
|
||||
|
||||
pwm1_pins: pwm1 {
|
||||
groups = "pwm1_c";
|
||||
function = "pwm1";
|
||||
};
|
||||
|
||||
scif2_pins: scif2 {
|
||||
groups = "scif2_data";
|
||||
function = "scif2";
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
groups = "mmc_data8", "mmc_ctrl";
|
||||
function = "mmc";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi2_pins_uhs: sd2_uhs {
|
||||
groups = "mmc_data8", "mmc_ctrl";
|
||||
function = "mmc";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
||||
groups = "usb0";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
vin4_pins_cvbs: vin4 {
|
||||
groups = "vin4_data8", "vin4_sync", "vin4_clk";
|
||||
function = "vin4";
|
||||
};
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
pinctrl-0 = <&pwm0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-0 = <&pwm1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rwdt {
|
||||
timeout-sec = <60>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
pinctrl-0 = <&scif2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
/* used for on-board eMMC */
|
||||
pinctrl-0 = <&sdhi2_pins>;
|
||||
pinctrl-1 = <&sdhi2_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_1p8v>;
|
||||
bus-width = <8>;
|
||||
mmc-hs200-1_8v;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
renesas,no-otg-pins;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin4 {
|
||||
pinctrl-0 = <&vin4_pins_cvbs>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port {
|
||||
vin4_in: endpoint {
|
||||
remote-endpoint = <&adv7180_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -15,6 +15,23 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
/*
|
||||
* The external audio clocks are configured as 0 Hz fixed frequency
|
||||
* clocks by default.
|
||||
* Boards that provide audio clocks should override them.
|
||||
*/
|
||||
audio_clk_a: audio_clk_a {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
audio_clk_b: audio_clk_b {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
/* External CAN clock - to be overridden by boards that provide it */
|
||||
can_clk: can {
|
||||
compatible = "fixed-clock";
|
||||
|
|
@ -77,6 +94,7 @@
|
|||
compatible = "renesas,r8a77995-wdt",
|
||||
"renesas,rcar-gen3-wdt";
|
||||
reg = <0 0xe6020000 0 0x0c>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 402>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 402>;
|
||||
|
|
@ -188,11 +206,81 @@
|
|||
resets = <&cpg 906>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
pfc: pinctrl@e6060000 {
|
||||
compatible = "renesas,pfc-r8a77995";
|
||||
reg = <0 0xe6060000 0 0x508>;
|
||||
};
|
||||
|
||||
cmt0: timer@e60f0000 {
|
||||
compatible = "renesas,r8a77995-cmt0",
|
||||
"renesas,rcar-gen3-cmt0";
|
||||
reg = <0 0xe60f0000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 303>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 303>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cmt1: timer@e6130000 {
|
||||
compatible = "renesas,r8a77995-cmt1",
|
||||
"renesas,rcar-gen3-cmt1";
|
||||
reg = <0 0xe6130000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 302>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 302>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cmt2: timer@e6140000 {
|
||||
compatible = "renesas,r8a77995-cmt1",
|
||||
"renesas,rcar-gen3-cmt1";
|
||||
reg = <0 0xe6140000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 301>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 301>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cmt3: timer@e6148000 {
|
||||
compatible = "renesas,r8a77995-cmt1",
|
||||
"renesas,rcar-gen3-cmt1";
|
||||
reg = <0 0xe6148000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 300>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 300>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a77995-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
|
|
@ -242,6 +330,71 @@
|
|||
resets = <&cpg 407>;
|
||||
};
|
||||
|
||||
tmu0: timer@e61e0000 {
|
||||
compatible = "renesas,tmu-r8a77995", "renesas,tmu";
|
||||
reg = <0 0xe61e0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 125>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 125>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu1: timer@e6fc0000 {
|
||||
compatible = "renesas,tmu-r8a77995", "renesas,tmu";
|
||||
reg = <0 0xe6fc0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 124>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 124>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu2: timer@e6fd0000 {
|
||||
compatible = "renesas,tmu-r8a77995", "renesas,tmu";
|
||||
reg = <0 0xe6fd0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 123>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 123>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu3: timer@e6fe0000 {
|
||||
compatible = "renesas,tmu-r8a77995", "renesas,tmu";
|
||||
reg = <0 0xe6fe0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 122>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 122>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu4: timer@ffc00000 {
|
||||
compatible = "renesas,tmu-r8a77995", "renesas,tmu";
|
||||
reg = <0 0xffc00000 0 0x30>;
|
||||
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 121>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 121>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -389,12 +542,22 @@
|
|||
dma-channels = <2>;
|
||||
};
|
||||
|
||||
arm_cc630p: crypto@e6601000 {
|
||||
compatible = "arm,cryptocell-630p-ree";
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x0 0xe6601000 0 0x1000>;
|
||||
clocks = <&cpg CPG_MOD 229>;
|
||||
resets = <&cpg 229>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
canfd: can@e66c0000 {
|
||||
compatible = "renesas,r8a77995-canfd",
|
||||
"renesas,rcar-gen3-canfd";
|
||||
reg = <0 0xe66c0000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch_int", "g_int";
|
||||
clocks = <&cpg CPG_MOD 914>,
|
||||
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
|
|
@ -498,7 +661,7 @@
|
|||
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
|
||||
};
|
||||
|
||||
ipmmu_ds0: mmu@e6740000 {
|
||||
ipmmu_ds0: iommu@e6740000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xe6740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 0>;
|
||||
|
|
@ -506,7 +669,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_ds1: mmu@e7740000 {
|
||||
ipmmu_ds1: iommu@e7740000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xe7740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 1>;
|
||||
|
|
@ -514,7 +677,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_hc: mmu@e6570000 {
|
||||
ipmmu_hc: iommu@e6570000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xe6570000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 2>;
|
||||
|
|
@ -522,7 +685,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_mm: mmu@e67b0000 {
|
||||
ipmmu_mm: iommu@e67b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xe67b0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
@ -531,7 +694,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_mp: mmu@ec670000 {
|
||||
ipmmu_mp: iommu@ec670000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xec670000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 4>;
|
||||
|
|
@ -539,7 +702,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_pv0: mmu@fd800000 {
|
||||
ipmmu_pv0: iommu@fd800000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xfd800000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 6>;
|
||||
|
|
@ -547,7 +710,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_rt: mmu@ffc80000 {
|
||||
ipmmu_rt: iommu@ffc80000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xffc80000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 10>;
|
||||
|
|
@ -555,7 +718,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vc0: mmu@fe6b0000 {
|
||||
ipmmu_vc0: iommu@fe6b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xfe6b0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 12>;
|
||||
|
|
@ -563,7 +726,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vi0: mmu@febd0000 {
|
||||
ipmmu_vi0: iommu@febd0000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xfebd0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 14>;
|
||||
|
|
@ -571,7 +734,7 @@
|
|||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_vp0: mmu@fe990000 {
|
||||
ipmmu_vp0: iommu@fe990000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xfe990000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 16>;
|
||||
|
|
@ -616,9 +779,11 @@
|
|||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii";
|
||||
rx-internal-delay-ps = <1800>;
|
||||
iommus = <&ipmmu_ds0 16>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -870,6 +1035,159 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
rcar_sound: sound@ec500000 {
|
||||
/*
|
||||
* #sound-dai-cells is required
|
||||
*
|
||||
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
|
||||
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
|
||||
*/
|
||||
/*
|
||||
* #clock-cells is required for audio_clkout0/1/2/3
|
||||
*
|
||||
* clkout : #clock-cells = <0>; <&rcar_sound>;
|
||||
* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
|
||||
*/
|
||||
compatible = "renesas,rcar_sound-r8a77995", "renesas,rcar_sound-gen3";
|
||||
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
||||
<0 0xec5a0000 0 0x100>, /* ADG */
|
||||
<0 0xec540000 0 0x1000>, /* SSIU */
|
||||
<0 0xec541000 0 0x280>, /* SSI */
|
||||
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
|
||||
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
|
||||
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
<&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>,
|
||||
<&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
|
||||
<&audio_clk_a>, <&audio_clk_b>,
|
||||
<&cpg CPG_CORE R8A77995_CLK_ZA2>;
|
||||
clock-names = "ssi-all",
|
||||
"ssi.4", "ssi.3",
|
||||
"src.6", "src.5",
|
||||
"mix.1", "mix.0",
|
||||
"ctu.1", "ctu.0",
|
||||
"dvc.0", "dvc.1",
|
||||
"clk_a", "clk_b", "clk_i";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 1005>,
|
||||
<&cpg 1011>, <&cpg 1012>;
|
||||
reset-names = "ssi-all",
|
||||
"ssi.4", "ssi.3";
|
||||
status = "disabled";
|
||||
|
||||
rcar_sound,ctu {
|
||||
ctu00: ctu-0 { };
|
||||
ctu01: ctu-1 { };
|
||||
ctu02: ctu-2 { };
|
||||
ctu03: ctu-3 { };
|
||||
ctu10: ctu-4 { };
|
||||
ctu11: ctu-5 { };
|
||||
ctu12: ctu-6 { };
|
||||
ctu13: ctu-7 { };
|
||||
};
|
||||
|
||||
rcar_sound,dvc {
|
||||
dvc0: dvc-0 {
|
||||
dmas = <&audma0 0xbc>;
|
||||
dma-names = "tx";
|
||||
};
|
||||
dvc1: dvc-1 {
|
||||
dmas = <&audma0 0xbe>;
|
||||
dma-names = "tx";
|
||||
};
|
||||
};
|
||||
|
||||
rcar_sound,mix {
|
||||
mix0: mix-0 { };
|
||||
mix1: mix-1 { };
|
||||
};
|
||||
|
||||
rcar_sound,src {
|
||||
src5: src-5 {
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x8f>, <&audma0 0xb2>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src6: src-6 {
|
||||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x91>, <&audma0 0xb4>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
};
|
||||
|
||||
rcar_sound,ssi {
|
||||
ssi3: ssi-3 {
|
||||
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x07>, <&audma0 0x08>,
|
||||
<&audma0 0x6f>, <&audma0 0x70>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi4: ssi-4 {
|
||||
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x09>, <&audma0 0x0a>,
|
||||
<&audma0 0x71>, <&audma0 0x72>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mlp: mlp@ec520000 {
|
||||
compatible = "renesas,r8a77995-mlp",
|
||||
"renesas,rcar-gen3-mlp";
|
||||
reg = <0 0xec520000 0 0x800>;
|
||||
interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 802>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 802>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
audma0: dma-controller@ec700000 {
|
||||
compatible = "renesas,dmac-r8a77995",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xec700000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14", "ch15";
|
||||
clocks = <&cpg CPG_MOD 502>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 502>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
|
||||
<&ipmmu_mp 2>, <&ipmmu_mp 3>,
|
||||
<&ipmmu_mp 4>, <&ipmmu_mp 5>,
|
||||
<&ipmmu_mp 6>, <&ipmmu_mp 7>,
|
||||
<&ipmmu_mp 8>, <&ipmmu_mp 9>,
|
||||
<&ipmmu_mp 10>, <&ipmmu_mp 11>,
|
||||
<&ipmmu_mp 12>, <&ipmmu_mp 13>,
|
||||
<&ipmmu_mp 14>, <&ipmmu_mp 15>;
|
||||
};
|
||||
|
||||
ohci0: usb@ee080000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0xee080000 0 0x100>;
|
||||
|
|
@ -907,12 +1225,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi2: sd@ee140000 {
|
||||
sdhi2: mmc@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a77995",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77995_CLK_SD0H>;
|
||||
clock-names = "core", "clkh";
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 312>;
|
||||
|
|
@ -920,6 +1239,22 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
rpc: spi@ee200000 {
|
||||
compatible = "renesas,r8a77995-rpc-if",
|
||||
"renesas,rcar-gen3-rpc-if";
|
||||
reg = <0 0xee200000 0 0x200>,
|
||||
<0 0x08000000 0 0x04000000>,
|
||||
<0 0xee208000 0 0x100>;
|
||||
reg-names = "regs", "dirmap", "wbuf";
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
@ -1017,14 +1352,13 @@
|
|||
reg = <0 0xfeb00000 0 0x40000>;
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>;
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
|
||||
clock-names = "du.0", "du.1";
|
||||
resets = <&cpg 724>;
|
||||
reset-names = "du.0";
|
||||
|
||||
renesas,cmms = <&cmm0>, <&cmm1>;
|
||||
vsps = <&vspd0 0>, <&vspd1 0>;
|
||||
renesas,vsps = <&vspd0 0>, <&vspd1 0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -1034,8 +1368,6 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
|
|
@ -1077,8 +1409,6 @@
|
|||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1104,8 +1434,6 @@
|
|||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds1_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -6,12 +6,84 @@
|
|||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
#include "r8a779a0.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Renesas Falcon CPU board";
|
||||
compatible = "renesas,falcon-cpu", "renesas,r8a779a0";
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
i2c5 = &i2c5;
|
||||
i2c6 = &i2c6;
|
||||
serial0 = &scif0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&keys_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
key-1 {
|
||||
gpios = <&gpio6 18 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_1>;
|
||||
label = "SW47";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
|
||||
key-2 {
|
||||
gpios = <&gpio6 19 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_2>;
|
||||
label = "SW48";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
|
||||
key-3 {
|
||||
gpios = <&gpio6 20 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_3>;
|
||||
label = "SW49";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-1 {
|
||||
gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <1>;
|
||||
};
|
||||
led-2 {
|
||||
gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <2>;
|
||||
};
|
||||
led-3 {
|
||||
gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
|
|
@ -33,6 +105,27 @@
|
|||
reg = <0x7 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
mini-dp-con {
|
||||
compatible = "dp-connector";
|
||||
label = "CN5";
|
||||
type = "mini";
|
||||
|
||||
port {
|
||||
mini_dp_con_in: endpoint {
|
||||
remote-endpoint = <&sn65dsi86_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
reg_1p2v: regulator-1p2v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.2V";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_1p8v: regulator-1p8v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.8V";
|
||||
|
|
@ -50,24 +143,31 @@
|
|||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sn65dsi86_refclk: clk-x6 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <38400000>;
|
||||
};
|
||||
};
|
||||
|
||||
&avb0 {
|
||||
pinctrl-0 = <&avb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-handle = <&phy0>;
|
||||
tx-internal-delay-ps = <2000>;
|
||||
&dsi0 {
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
rxc-skew-ps = <1500>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
|
||||
ports {
|
||||
port@1 {
|
||||
dsi0_out: endpoint {
|
||||
remote-endpoint = <&sn65dsi86_in>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <16666666>;
|
||||
};
|
||||
|
|
@ -82,6 +182,13 @@
|
|||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "rohm,br24g01", "atmel,24c01";
|
||||
label = "cpu-board";
|
||||
reg = <0x50>;
|
||||
pagesize = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
|
|
@ -90,6 +197,44 @@
|
|||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
bridge@2c {
|
||||
pinctrl-0 = <&irq0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
compatible = "ti,sn65dsi86";
|
||||
reg = <0x2c>;
|
||||
|
||||
clocks = <&sn65dsi86_refclk>;
|
||||
clock-names = "refclk";
|
||||
|
||||
interrupt-parent = <&intc_ex>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
vccio-supply = <®_1p8v>;
|
||||
vpll-supply = <®_1p8v>;
|
||||
vcca-supply = <®_1p2v>;
|
||||
vcc-supply = <®_1p2v>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
sn65dsi86_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
sn65dsi86_out: endpoint {
|
||||
remote-endpoint = <&mini_dp_con_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
|
|
@ -121,24 +266,6 @@
|
|||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
avb0_pins: avb0 {
|
||||
mux {
|
||||
groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
|
||||
function = "avb0";
|
||||
};
|
||||
|
||||
pins_mdio {
|
||||
groups = "avb0_mdio";
|
||||
drive-strength = <21>;
|
||||
};
|
||||
|
||||
pins_mii {
|
||||
groups = "avb0_rgmii";
|
||||
drive-strength = <21>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
groups = "i2c0";
|
||||
function = "i2c0";
|
||||
|
|
@ -154,12 +281,27 @@
|
|||
function = "i2c6";
|
||||
};
|
||||
|
||||
irq0_pins: irq0 {
|
||||
groups = "intc_ex_irq0";
|
||||
function = "intc_ex";
|
||||
};
|
||||
|
||||
keys_pins: keys {
|
||||
pins = "GP_6_18", "GP_6_19", "GP_6_20";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mmc_pins: mmc {
|
||||
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
|
||||
function = "mmc";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
qspi0_pins: qspi0 {
|
||||
groups = "qspi0_ctrl", "qspi0_data4";
|
||||
function = "qspi0";
|
||||
};
|
||||
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data", "scif0_ctrl";
|
||||
function = "scif0";
|
||||
|
|
@ -171,6 +313,39 @@
|
|||
};
|
||||
};
|
||||
|
||||
&rpc {
|
||||
pinctrl-0 = <&qspi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "spansion,s25fs512s", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
boot@0 {
|
||||
reg = <0x0 0xcc0000>;
|
||||
read-only;
|
||||
};
|
||||
user@cc0000 {
|
||||
reg = <0xcc0000 0x3340000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rwdt {
|
||||
timeout-sec = <60>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
|
|
|||
265
arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi
Normal file
265
arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi
Normal file
|
|
@ -0,0 +1,265 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the Falcon CSI/DSI sub-board
|
||||
*
|
||||
* Copyright (C) 2021 Glider bv
|
||||
*/
|
||||
|
||||
&csi40 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
csi40_in: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
remote-endpoint = <&max96712_out0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&csi42 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
csi42_in: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
remote-endpoint = <&max96712_out1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&csi43 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
csi43_in: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
remote-endpoint = <&max96712_out2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pca9654_a: gpio@21 {
|
||||
compatible = "onnn,pca9654";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
pca9654_b: gpio@22 {
|
||||
compatible = "onnn,pca9654";
|
||||
reg = <0x22>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
pca9654_c: gpio@23 {
|
||||
compatible = "onnn,pca9654";
|
||||
reg = <0x23>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
eeprom@52 {
|
||||
compatible = "rohm,br24g01", "atmel,24c01";
|
||||
label = "csi-dsi-sub-board-id";
|
||||
reg = <0x52>;
|
||||
pagesize = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
gmsl0: gmsl-deserializer@49 {
|
||||
compatible = "maxim,max96712";
|
||||
reg = <0x49>;
|
||||
enable-gpios = <&pca9654_a 0 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
max96712_out0: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
remote-endpoint = <&csi40_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gmsl1: gmsl-deserializer@4b {
|
||||
compatible = "maxim,max96712";
|
||||
reg = <0x4b>;
|
||||
enable-gpios = <&pca9654_b 0 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
max96712_out1: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
lane-polarities = <0 0 0 0 1>;
|
||||
remote-endpoint = <&csi42_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gmsl2: gmsl-deserializer@6b {
|
||||
compatible = "maxim,max96712";
|
||||
reg = <0x6b>;
|
||||
enable-gpios = <&pca9654_c 0 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
max96712_out2: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
lane-polarities = <0 0 0 0 1>;
|
||||
remote-endpoint = <&csi43_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&isp0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&isp2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&isp3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin00 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin01 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin02 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin03 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin04 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin05 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin06 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin07 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin16 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin17 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin18 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin19 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin20 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin21 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin22 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin23 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin24 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin25 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin26 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin27 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin28 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin29 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin30 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin31 {
|
||||
status = "okay";
|
||||
};
|
||||
15
arch/arm/dts/r8a779a0-falcon-ethernet.dtsi
Normal file
15
arch/arm/dts/r8a779a0-falcon-ethernet.dtsi
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the Falcon Ethernet sub-board
|
||||
*
|
||||
* Copyright (C) 2021 Glider bv
|
||||
*/
|
||||
|
||||
&i2c0 {
|
||||
eeprom@53 {
|
||||
compatible = "rohm,br24g01", "atmel,24c01";
|
||||
label = "ethernet-sub-board-id";
|
||||
reg = <0x53>;
|
||||
pagesize = <8>;
|
||||
};
|
||||
};
|
||||
|
|
@ -21,7 +21,7 @@
|
|||
spi-max-frequency = <50000000>;
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
reg = <0>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
|
|
|
|||
|
|
@ -1,12 +1,14 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the Falcon CPU and BreakOut boards
|
||||
* Device Tree Source for the Falcon CPU and BreakOut boards with R-Car V3U
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a779a0-falcon-cpu.dtsi"
|
||||
#include "r8a779a0-falcon-csi-dsi.dtsi"
|
||||
#include "r8a779a0-falcon-ethernet.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Renesas Falcon CPU and Breakout boards based on r8a779a0";
|
||||
|
|
@ -14,15 +16,77 @@
|
|||
|
||||
aliases {
|
||||
ethernet0 = &avb0;
|
||||
serial0 = &scif0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&rwdt {
|
||||
timeout-sec = <60>;
|
||||
&avb0 {
|
||||
pinctrl-0 = <&avb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-handle = <&phy0>;
|
||||
tx-internal-delay-ps = <2000>;
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id0022.1622",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
rxc-skew-ps = <1500>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&canfd {
|
||||
pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
channel0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
channel1 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
eeprom@51 {
|
||||
compatible = "rohm,br24g01", "atmel,24c01";
|
||||
label = "breakout-board";
|
||||
reg = <0x51>;
|
||||
pagesize = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
&pfc {
|
||||
avb0_pins: avb0 {
|
||||
mux {
|
||||
groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
|
||||
"avb0_txcrefclk";
|
||||
function = "avb0";
|
||||
};
|
||||
|
||||
pins_mdio {
|
||||
groups = "avb0_mdio";
|
||||
drive-strength = <21>;
|
||||
};
|
||||
|
||||
pins_mii {
|
||||
groups = "avb0_rgmii";
|
||||
drive-strength = <21>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
canfd0_pins: canfd0 {
|
||||
groups = "canfd0_data";
|
||||
function = "canfd0";
|
||||
};
|
||||
|
||||
canfd1_pins: canfd1 {
|
||||
groups = "canfd1_data";
|
||||
function = "canfd1";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -21,8 +21,18 @@
|
|||
model = "Renesas R-Car Gen3 ULCB board";
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
i2c5 = &i2c5;
|
||||
i2c6 = &i2c6;
|
||||
i2c7 = &i2c_dvfs;
|
||||
serial0 = &scif2;
|
||||
ethernet0 = &avb;
|
||||
mmc0 = &sdhi2;
|
||||
mmc1 = &sdhi0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
|
@ -46,6 +56,7 @@
|
|||
|
||||
port {
|
||||
hdmi0_con: endpoint {
|
||||
remote-endpoint = <&rcar_dw_hdmi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -73,7 +84,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
reg_1p8v: regulator0 {
|
||||
reg_1p8v: regulator-1p8v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
|
|
@ -82,7 +93,7 @@
|
|||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator1 {
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
|
|
@ -92,11 +103,11 @@
|
|||
};
|
||||
|
||||
sound_card: sound {
|
||||
compatible = "audio-graph-card";
|
||||
compatible = "audio-graph-card2";
|
||||
label = "rcar-sound";
|
||||
|
||||
dais = <&rsnd_port0 /* ak4613 */
|
||||
&rsnd_port1 /* HDMI0 */
|
||||
links = <&rsnd_port0 /* ak4613 */
|
||||
&rsnd_port1 /* HDMI0 */
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -136,6 +147,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&a57_0 {
|
||||
cpu-supply = <&dvfs>;
|
||||
};
|
||||
|
||||
&audio_clk_a {
|
||||
clock-frequency = <22579200>;
|
||||
};
|
||||
|
|
@ -144,10 +159,12 @@
|
|||
pinctrl-0 = <&avb_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-txid";
|
||||
tx-internal-delay-ps = <2000>;
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id0022.1622",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
rxc-skew-ps = <1500>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
|
|
@ -191,10 +208,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&hdmi0_con {
|
||||
remote-endpoint = <&rcar_dw_hdmi0_out>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -365,7 +378,7 @@
|
|||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_pins &sound_clk_pins>;
|
||||
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* Single DAI */
|
||||
|
|
@ -403,30 +416,73 @@
|
|||
reg = <0>;
|
||||
rsnd_for_ak4613: endpoint {
|
||||
remote-endpoint = <&ak4613_endpoint>;
|
||||
|
||||
dai-format = "left_j";
|
||||
bitclock-master = <&rsnd_for_ak4613>;
|
||||
frame-master = <&rsnd_for_ak4613>;
|
||||
|
||||
playback = <&ssi0 &src0 &dvc0>;
|
||||
capture = <&ssi1 &src1 &dvc1>;
|
||||
bitclock-master;
|
||||
frame-master;
|
||||
playback = <&ssi0>, <&src0>, <&dvc0>;
|
||||
capture = <&ssi1>, <&src1>, <&dvc1>;
|
||||
};
|
||||
};
|
||||
rsnd_port1: port@1 {
|
||||
reg = <1>;
|
||||
rsnd_for_hdmi: endpoint {
|
||||
remote-endpoint = <&dw_hdmi0_snd_in>;
|
||||
|
||||
dai-format = "i2s";
|
||||
bitclock-master = <&rsnd_for_hdmi>;
|
||||
frame-master = <&rsnd_for_hdmi>;
|
||||
|
||||
bitclock-master;
|
||||
frame-master;
|
||||
playback = <&ssi2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rpc {
|
||||
/* Left disabled. To be enabled by firmware when unlocked. */
|
||||
|
||||
flash@0 {
|
||||
compatible = "cypress,hyperflash", "cfi-flash";
|
||||
reg = <0>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
bootparam@0 {
|
||||
reg = <0x00000000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
bl2@40000 {
|
||||
reg = <0x00040000 0x140000>;
|
||||
read-only;
|
||||
};
|
||||
cert_header_sa6@180000 {
|
||||
reg = <0x00180000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
bl31@1c0000 {
|
||||
reg = <0x001c0000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
tee@200000 {
|
||||
reg = <0x00200000 0x440000>;
|
||||
read-only;
|
||||
};
|
||||
uboot@640000 {
|
||||
reg = <0x00640000 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
dtb@740000 {
|
||||
reg = <0x00740000 0x080000>;
|
||||
};
|
||||
kernel@7c0000 {
|
||||
reg = <0x007c0000 0x1400000>;
|
||||
};
|
||||
user@1bc0000 {
|
||||
reg = <0x01bc0000 0x2440000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rwdt {
|
||||
timeout-sec = <60>;
|
||||
status = "okay";
|
||||
|
|
@ -468,7 +524,10 @@
|
|||
bus-width = <8>;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
non-removable;
|
||||
full-pwr-cycle-in-suspend;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -30,13 +30,15 @@ config R8A7795
|
|||
bool "Renesas SoC R8A7795"
|
||||
select GICV2
|
||||
imply CLK_R8A7795
|
||||
imply PINCTRL_PFC_R8A7795
|
||||
imply PINCTRL_PFC_R8A77951
|
||||
|
||||
config R8A7796
|
||||
bool "Renesas SoC R8A7796"
|
||||
select GICV2
|
||||
imply CLK_R8A7796
|
||||
imply PINCTRL_PFC_R8A7796
|
||||
imply CLK_R8A77960
|
||||
imply CLK_R8A77961
|
||||
imply PINCTRL_PFC_R8A77960
|
||||
imply PINCTRL_PFC_R8A77961
|
||||
|
||||
config R8A77965
|
||||
bool "Renesas SoC R8A77965"
|
||||
|
|
@ -199,4 +201,7 @@ config MULTI_DTB_FIT_USER_DEF_ADDR
|
|||
config SYS_MALLOC_F_LEN
|
||||
default 0x8000 if RCAR_GEN3
|
||||
|
||||
config DM_RESET
|
||||
default y if RCAR_GEN3
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-ex
|
|||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SYS_MMC_ENV_DEV=2
|
||||
CONFIG_SYS_MMC_ENV_DEV=0
|
||||
CONFIG_SYS_MMC_ENV_PART=2
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_REGMAP=y
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ CONFIG_DFU_RAM=y
|
|||
CONFIG_DFU_SF=y
|
||||
CONFIG_RCAR_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_RCAR_IIC=y
|
||||
CONFIG_SYS_I2C_RCAR_I2C=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-ex
|
|||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SYS_MMC_ENV_DEV=1
|
||||
CONFIG_SYS_MMC_ENV_DEV=0
|
||||
CONFIG_SYS_MMC_ENV_PART=2
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_REGMAP=y
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/math64.h>
|
||||
|
||||
#include <dt-bindings/clk/versaclock.h>
|
||||
#include <dt-bindings/clock/versaclock.h>
|
||||
|
||||
/* VersaClock5 registers */
|
||||
#define VC5_OTP_CONTROL 0x00
|
||||
|
|
|
|||
|
|
@ -4,6 +4,9 @@ config CLK_RENESAS
|
|||
help
|
||||
Enable support for clock present on Renesas RCar SoCs.
|
||||
|
||||
config CLK_RCAR_CPG_LIB
|
||||
bool "CPG/MSSR library functions"
|
||||
|
||||
config CLK_RCAR_GEN2
|
||||
bool "Renesas RCar Gen2 clock driver"
|
||||
def_bool y if RCAR_32
|
||||
|
|
@ -45,6 +48,7 @@ config CLK_RCAR_GEN3
|
|||
bool "Renesas RCar Gen3 clock driver"
|
||||
def_bool y if RCAR_GEN3
|
||||
depends on CLK_RENESAS
|
||||
select CLK_RCAR_CPG_LIB
|
||||
help
|
||||
Enable this to support the clocks on Renesas RCar Gen3 SoC.
|
||||
|
||||
|
|
@ -79,11 +83,17 @@ config CLK_R8A7795
|
|||
help
|
||||
Enable this to support the clocks on Renesas R8A7795 SoC.
|
||||
|
||||
config CLK_R8A7796
|
||||
bool "Renesas R8A7796 clock driver"
|
||||
config CLK_R8A77960
|
||||
bool "Renesas R8A77960 clock driver"
|
||||
depends on CLK_RCAR_GEN3
|
||||
help
|
||||
Enable this to support the clocks on Renesas R8A7796 SoC.
|
||||
Enable this to support the clocks on Renesas R8A77960 SoC.
|
||||
|
||||
config CLK_R8A77961
|
||||
bool "Renesas R8A77961 clock driver"
|
||||
depends on CLK_RCAR_GEN3
|
||||
help
|
||||
Enable this to support the clocks on Renesas R8A77961 SoC.
|
||||
|
||||
config CLK_R8A77965
|
||||
bool "Renesas R8A77965 clock driver"
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
obj-$(CONFIG_CLK_RENESAS) += renesas-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o
|
||||
obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o
|
||||
obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o
|
||||
|
|
@ -11,7 +12,8 @@ obj-$(CONFIG_CLK_R8A7793) += r8a7791-cpg-mssr.o
|
|||
obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o
|
||||
obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77960) += r8a7796-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77961) += r8a7796-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
#include <log.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
|
|
@ -26,11 +27,6 @@
|
|||
#define CPG_PLL0CR 0x00d8
|
||||
#define CPG_SDCKCR 0x0074
|
||||
|
||||
struct clk_div_table {
|
||||
u8 val;
|
||||
u8 div;
|
||||
};
|
||||
|
||||
/* SDHI divisors */
|
||||
static const struct clk_div_table cpg_sdh_div_table[] = {
|
||||
{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
|
||||
|
|
|
|||
|
|
@ -13,77 +13,42 @@
|
|||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
#include <dm/device-internal.h>
|
||||
#include <dm/lists.h>
|
||||
#include <errno.h>
|
||||
#include <log.h>
|
||||
#include <wait_bit.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <reset-uclass.h>
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
#include "rcar-cpg-lib.h"
|
||||
|
||||
#define CPG_PLL0CR 0x00d8
|
||||
#define CPG_PLL2CR 0x002c
|
||||
#define CPG_PLL4CR 0x01f4
|
||||
|
||||
#define CPG_RPC_PREDIV_MASK 0x3
|
||||
#define CPG_RPC_PREDIV_OFFSET 3
|
||||
#define CPG_RPC_POSTDIV_MASK 0x7
|
||||
#define CPG_RPC_POSTDIV_OFFSET 0
|
||||
|
||||
/*
|
||||
* SDn Clock
|
||||
*/
|
||||
#define CPG_SD_STP_HCK BIT(9)
|
||||
#define CPG_SD_STP_CK BIT(8)
|
||||
|
||||
#define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
|
||||
#define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
|
||||
|
||||
#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
|
||||
{ \
|
||||
.val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
|
||||
((stp_ck) ? CPG_SD_STP_CK : 0) | \
|
||||
((sd_srcfc) << 2) | \
|
||||
((sd_fc) << 0), \
|
||||
.div = (sd_div), \
|
||||
}
|
||||
|
||||
struct sd_div_table {
|
||||
u32 val;
|
||||
unsigned int div;
|
||||
static const struct clk_div_table cpg_rpcsrc_div_table[] = {
|
||||
{ 2, 5 }, { 3, 6 }, { 0, 0 },
|
||||
};
|
||||
|
||||
/* SDn divider
|
||||
* sd_srcfc sd_fc div
|
||||
* stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
|
||||
*-------------------------------------------------------------------
|
||||
* 0 0 0 (1) 1 (4) 4
|
||||
* 0 0 1 (2) 1 (4) 8
|
||||
* 1 0 2 (4) 1 (4) 16
|
||||
* 1 0 3 (8) 1 (4) 32
|
||||
* 1 0 4 (16) 1 (4) 64
|
||||
* 0 0 0 (1) 0 (2) 2
|
||||
* 0 0 1 (2) 0 (2) 4
|
||||
* 1 0 2 (4) 0 (2) 8
|
||||
* 1 0 3 (8) 0 (2) 16
|
||||
* 1 0 4 (16) 0 (2) 32
|
||||
*/
|
||||
static const struct sd_div_table cpg_sd_div_table[] = {
|
||||
/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
|
||||
CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
|
||||
CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
|
||||
CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
|
||||
CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
|
||||
static const struct clk_div_table r8a77970_cpg_sd0h_div_table[] = {
|
||||
{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
|
||||
{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
|
||||
{ 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_div_table r8a77970_cpg_sd0_div_table[] = {
|
||||
{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
|
||||
{ 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
|
||||
|
|
@ -108,37 +73,6 @@ static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
|
|||
return renesas_clk_get_parent(clk, info, parent);
|
||||
}
|
||||
|
||||
static int gen3_clk_setup_sdif_div(struct clk *clk, ulong rate)
|
||||
{
|
||||
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
struct cpg_mssr_info *info = priv->info;
|
||||
const struct cpg_core_clk *core;
|
||||
struct clk parent;
|
||||
int ret;
|
||||
|
||||
ret = gen3_clk_get_parent(priv, clk, info, &parent);
|
||||
if (ret) {
|
||||
printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (renesas_clk_is_mod(&parent))
|
||||
return 0;
|
||||
|
||||
ret = renesas_clk_get_core(&parent, info, &core);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (core->type != CLK_TYPE_GEN3_SD)
|
||||
return 0;
|
||||
|
||||
debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset);
|
||||
|
||||
writel((rate == 400000000) ? 0x4 : 0x1, priv->base + core->offset);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gen3_clk_enable(struct clk *clk)
|
||||
{
|
||||
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
|
|
@ -155,9 +89,71 @@ static int gen3_clk_disable(struct clk *clk)
|
|||
|
||||
static u64 gen3_clk_get_rate64(struct clk *clk);
|
||||
|
||||
static int gen3_clk_setup_sdif_div(struct clk *clk, ulong rate)
|
||||
{
|
||||
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
struct cpg_mssr_info *info = priv->info;
|
||||
const struct cpg_core_clk *core;
|
||||
struct clk parent, grandparent;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* The clk may be either CPG_MOD or core clock, in case this is MOD
|
||||
* clock, use core clock one level up, otherwise use the clock as-is.
|
||||
* Note that parent clock here always represents core clock. Also note
|
||||
* that grandparent clock are the parent clock of the core clock here.
|
||||
*/
|
||||
if (renesas_clk_is_mod(clk)) {
|
||||
ret = gen3_clk_get_parent(priv, clk, info, &parent);
|
||||
if (ret) {
|
||||
printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
|
||||
return ret;
|
||||
}
|
||||
} else {
|
||||
parent = *clk;
|
||||
}
|
||||
|
||||
if (renesas_clk_is_mod(&parent))
|
||||
return 0;
|
||||
|
||||
ret = renesas_clk_get_core(&parent, info, &core);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = renesas_clk_get_parent(&parent, info, &grandparent);
|
||||
if (ret) {
|
||||
printf("%s[%i] grandparent fail, ret=%i\n", __func__, __LINE__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
switch (core->type) {
|
||||
case CLK_TYPE_GEN3_SDH:
|
||||
fallthrough;
|
||||
case CLK_TYPE_GEN4_SDH:
|
||||
return rcar_clk_set_rate64_sdh(core->parent,
|
||||
gen3_clk_get_rate64(&grandparent),
|
||||
rate, priv->base + core->offset);
|
||||
|
||||
case CLK_TYPE_GEN3_SD:
|
||||
fallthrough;
|
||||
case CLK_TYPE_GEN4_SD:
|
||||
return rcar_clk_set_rate64_sd(core->parent,
|
||||
gen3_clk_get_rate64(&grandparent),
|
||||
rate, priv->base + core->offset);
|
||||
|
||||
case CLK_TYPE_R8A77970_SD0:
|
||||
return rcar_clk_set_rate64_div_table(core->parent,
|
||||
gen3_clk_get_rate64(&grandparent),
|
||||
rate, priv->base + core->offset,
|
||||
CPG_SDCKCR_SD0FC_MASK,
|
||||
r8a77970_cpg_sd0_div_table, "SD");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u64 gen3_clk_get_rate64_pll_mul_reg(struct gen3_clk_priv *priv,
|
||||
struct clk *parent,
|
||||
const struct cpg_core_clk *core,
|
||||
u32 mul_reg, u32 mult, u32 div,
|
||||
char *name)
|
||||
{
|
||||
|
|
@ -172,8 +168,8 @@ static u64 gen3_clk_get_rate64_pll_mul_reg(struct gen3_clk_priv *priv,
|
|||
|
||||
rate = (gen3_clk_get_rate64(parent) * mult) / div;
|
||||
|
||||
debug("%s[%i] %s clk: parent=%i mult=%u div=%u => rate=%llu\n",
|
||||
__func__, __LINE__, name, core->parent, mult, div, rate);
|
||||
debug("%s[%i] %s clk: mult=%u div=%u => rate=%llu\n",
|
||||
__func__, __LINE__, name, mult, div, rate);
|
||||
return rate;
|
||||
}
|
||||
|
||||
|
|
@ -185,9 +181,9 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
|
|||
const struct cpg_core_clk *core;
|
||||
const struct rcar_gen3_cpg_pll_config *pll_config =
|
||||
priv->cpg_pll_config;
|
||||
u32 value, div, prediv, postdiv;
|
||||
u32 value, div;
|
||||
u64 rate = 0;
|
||||
int i, ret;
|
||||
int ret;
|
||||
|
||||
debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
|
||||
|
||||
|
|
@ -227,56 +223,56 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
|
|||
return -EINVAL;
|
||||
|
||||
case CLK_TYPE_GEN3_MAIN:
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
|
||||
0, 1, pll_config->extal_div,
|
||||
"MAIN");
|
||||
|
||||
case CLK_TYPE_GEN3_PLL0:
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
|
||||
CPG_PLL0CR, 0, 0, "PLL0");
|
||||
|
||||
case CLK_TYPE_GEN3_PLL1:
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
|
||||
0, pll_config->pll1_mult,
|
||||
pll_config->pll1_div, "PLL1");
|
||||
|
||||
case CLK_TYPE_GEN3_PLL2:
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
|
||||
CPG_PLL2CR, 0, 0, "PLL2");
|
||||
|
||||
case CLK_TYPE_GEN3_PLL3:
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
|
||||
0, pll_config->pll3_mult,
|
||||
pll_config->pll3_div, "PLL3");
|
||||
|
||||
case CLK_TYPE_GEN3_PLL4:
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
|
||||
CPG_PLL4CR, 0, 0, "PLL4");
|
||||
|
||||
case CLK_TYPE_R8A779A0_MAIN:
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
|
||||
case CLK_TYPE_GEN4_MAIN:
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
|
||||
0, 1, pll_config->extal_div,
|
||||
"V3U_MAIN");
|
||||
|
||||
case CLK_TYPE_R8A779A0_PLL1:
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
|
||||
case CLK_TYPE_GEN4_PLL1:
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
|
||||
0, pll_config->pll1_mult,
|
||||
pll_config->pll1_div,
|
||||
"V3U_PLL1");
|
||||
|
||||
case CLK_TYPE_R8A779A0_PLL2X_3X:
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
|
||||
case CLK_TYPE_GEN4_PLL2X_3X:
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
|
||||
core->offset, 0, 0,
|
||||
"V3U_PLL2X_3X");
|
||||
|
||||
case CLK_TYPE_R8A779A0_PLL5:
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
|
||||
case CLK_TYPE_GEN4_PLL5:
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
|
||||
0, pll_config->pll5_mult,
|
||||
pll_config->pll5_div,
|
||||
"V3U_PLL5");
|
||||
|
||||
case CLK_TYPE_FF:
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
|
||||
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
|
||||
0, core->mult, core->div,
|
||||
"FIXED");
|
||||
|
||||
|
|
@ -289,59 +285,82 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
|
|||
div, rate);
|
||||
return rate;
|
||||
|
||||
case CLK_TYPE_GEN3_SD: /* FIXME */
|
||||
case CLK_TYPE_GEN3_SDH: /* Fixed factor 1:1 */
|
||||
fallthrough;
|
||||
case CLK_TYPE_R8A779A0_SD:
|
||||
value = readl(priv->base + core->offset);
|
||||
value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;
|
||||
case CLK_TYPE_GEN4_SDH: /* Fixed factor 1:1 */
|
||||
return rcar_clk_get_rate64_sdh(core->parent,
|
||||
gen3_clk_get_rate64(&parent),
|
||||
priv->base + core->offset);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cpg_sd_div_table); i++) {
|
||||
if (cpg_sd_div_table[i].val != value)
|
||||
continue;
|
||||
case CLK_TYPE_R8A77970_SD0H:
|
||||
return rcar_clk_get_rate64_div_table(core->parent,
|
||||
gen3_clk_get_rate64(&parent),
|
||||
priv->base + core->offset,
|
||||
CPG_SDCKCR_SDHFC_MASK,
|
||||
r8a77970_cpg_sd0h_div_table, "SDH");
|
||||
|
||||
rate = gen3_clk_get_rate64(&parent) /
|
||||
cpg_sd_div_table[i].div;
|
||||
debug("%s[%i] SD clk: parent=%i div=%i => rate=%llu\n",
|
||||
__func__, __LINE__,
|
||||
core->parent, cpg_sd_div_table[i].div, rate);
|
||||
case CLK_TYPE_GEN3_SD:
|
||||
fallthrough;
|
||||
case CLK_TYPE_GEN4_SD:
|
||||
return rcar_clk_get_rate64_sd(core->parent,
|
||||
gen3_clk_get_rate64(&parent),
|
||||
priv->base + core->offset);
|
||||
|
||||
return rate;
|
||||
case CLK_TYPE_R8A77970_SD0:
|
||||
return rcar_clk_get_rate64_div_table(core->parent,
|
||||
gen3_clk_get_rate64(&parent),
|
||||
priv->base + core->offset,
|
||||
CPG_SDCKCR_SD0FC_MASK,
|
||||
r8a77970_cpg_sd0_div_table, "SD");
|
||||
|
||||
case CLK_TYPE_GEN3_RPCSRC:
|
||||
return rcar_clk_get_rate64_div_table(core->parent,
|
||||
gen3_clk_get_rate64(&parent),
|
||||
priv->base + CPG_RPCCKCR,
|
||||
CPG_RPCCKCR_DIV_POST_MASK,
|
||||
cpg_rpcsrc_div_table, "RPCSRC");
|
||||
|
||||
case CLK_TYPE_GEN3_D3_RPCSRC:
|
||||
case CLK_TYPE_GEN3_E3_RPCSRC:
|
||||
/*
|
||||
* Register RPCSRC as fixed factor clock based on the
|
||||
* MD[4:1] pins and CPG_RPCCKCR[4:3] register value for
|
||||
* which has been set prior to booting the kernel.
|
||||
*/
|
||||
value = (readl(priv->base + CPG_RPCCKCR) & GENMASK(4, 3)) >> 3;
|
||||
|
||||
switch (value) {
|
||||
case 0:
|
||||
div = 5;
|
||||
break;
|
||||
case 1:
|
||||
div = 3;
|
||||
break;
|
||||
case 2:
|
||||
div = core->div;
|
||||
break;
|
||||
case 3:
|
||||
default:
|
||||
div = 2;
|
||||
break;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
rate = gen3_clk_get_rate64(&parent) / div;
|
||||
debug("%s[%i] E3/D3 RPCSRC clk: parent=%i div=%u => rate=%llu\n",
|
||||
__func__, __LINE__, (core->parent >> 16) & 0xffff, div, rate);
|
||||
|
||||
return rate;
|
||||
|
||||
case CLK_TYPE_GEN3_RPC:
|
||||
case CLK_TYPE_GEN4_RPC:
|
||||
return rcar_clk_get_rate64_rpc(core->parent,
|
||||
gen3_clk_get_rate64(&parent),
|
||||
priv->base + CPG_RPCCKCR);
|
||||
|
||||
case CLK_TYPE_GEN3_RPCD2:
|
||||
rate = gen3_clk_get_rate64(&parent);
|
||||
|
||||
value = readl(priv->base + core->offset);
|
||||
|
||||
prediv = (value >> CPG_RPC_PREDIV_OFFSET) &
|
||||
CPG_RPC_PREDIV_MASK;
|
||||
if (prediv == 2)
|
||||
rate /= 5;
|
||||
else if (prediv == 3)
|
||||
rate /= 6;
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) &
|
||||
CPG_RPC_POSTDIV_MASK;
|
||||
|
||||
if (postdiv % 2 != 0) {
|
||||
rate /= postdiv + 1;
|
||||
|
||||
if (core->type == CLK_TYPE_GEN3_RPCD2)
|
||||
rate /= 2;
|
||||
|
||||
debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%llu\n",
|
||||
__func__, __LINE__,
|
||||
core->parent, prediv, postdiv, rate);
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
case CLK_TYPE_GEN4_RPCD2:
|
||||
return rcar_clk_get_rate64_rpcd2(core->parent,
|
||||
gen3_clk_get_rate64(&parent));
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -382,7 +401,7 @@ const struct clk_ops gen3_clk_ops = {
|
|||
.of_xlate = gen3_clk_of_xlate,
|
||||
};
|
||||
|
||||
int gen3_clk_probe(struct udevice *dev)
|
||||
static int gen3_clk_probe(struct udevice *dev)
|
||||
{
|
||||
struct gen3_clk_priv *priv = dev_get_priv(dev);
|
||||
struct cpg_mssr_info *info =
|
||||
|
|
@ -440,9 +459,84 @@ int gen3_clk_probe(struct udevice *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int gen3_clk_remove(struct udevice *dev)
|
||||
static int gen3_clk_remove(struct udevice *dev)
|
||||
{
|
||||
struct gen3_clk_priv *priv = dev_get_priv(dev);
|
||||
|
||||
return renesas_clk_remove(priv->base, priv->info);
|
||||
}
|
||||
|
||||
U_BOOT_DRIVER(clk_gen3) = {
|
||||
.name = "clk_gen3",
|
||||
.id = UCLASS_CLK,
|
||||
.priv_auto = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
};
|
||||
|
||||
static int gen3_reset_assert(struct reset_ctl *reset_ctl)
|
||||
{
|
||||
struct udevice *cdev = (struct udevice *)dev_get_driver_data(reset_ctl->dev);
|
||||
struct gen3_clk_priv *priv = dev_get_priv(cdev);
|
||||
unsigned int reg = reset_ctl->id / 32;
|
||||
unsigned int bit = reset_ctl->id % 32;
|
||||
u32 bitmask = BIT(bit);
|
||||
|
||||
writel(bitmask, priv->base + priv->info->reset_regs[reg]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gen3_reset_deassert(struct reset_ctl *reset_ctl)
|
||||
{
|
||||
struct udevice *cdev = (struct udevice *)dev_get_driver_data(reset_ctl->dev);
|
||||
struct gen3_clk_priv *priv = dev_get_priv(cdev);
|
||||
unsigned int reg = reset_ctl->id / 32;
|
||||
unsigned int bit = reset_ctl->id % 32;
|
||||
u32 bitmask = BIT(bit);
|
||||
|
||||
writel(bitmask, priv->base + priv->info->reset_clear_regs[reg]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct reset_ops rst_gen3_ops = {
|
||||
.rst_assert = gen3_reset_assert,
|
||||
.rst_deassert = gen3_reset_deassert,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rst_gen3) = {
|
||||
.name = "rst_gen3",
|
||||
.id = UCLASS_RESET,
|
||||
.ops = &rst_gen3_ops,
|
||||
};
|
||||
|
||||
int gen3_cpg_bind(struct udevice *parent)
|
||||
{
|
||||
struct cpg_mssr_info *info =
|
||||
(struct cpg_mssr_info *)dev_get_driver_data(parent);
|
||||
struct udevice *cdev, *rdev;
|
||||
struct driver *drv;
|
||||
int ret;
|
||||
|
||||
drv = lists_driver_lookup_name("clk_gen3");
|
||||
if (!drv)
|
||||
return -ENOENT;
|
||||
|
||||
ret = device_bind_with_driver_data(parent, drv, "clk_gen3", (ulong)info,
|
||||
dev_ofnode(parent), &cdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
drv = lists_driver_lookup_name("rst_gen3");
|
||||
if (!drv)
|
||||
return -ENOENT;
|
||||
|
||||
ret = device_bind_with_driver_data(parent, drv, "rst_gen3", (ulong)cdev,
|
||||
dev_ofnode(parent), &rdev);
|
||||
if (ret)
|
||||
device_unbind(cdev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,11 +1,10 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Renesas R8A774A1 CPG MSSR driver
|
||||
* r8a774a1 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2017-2019 Marek Vasut <marek.vasut@gmail.com>
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on the following driver from Linux kernel:
|
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
|
||||
* Based on r8a7796-cpg-mssr.c
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*/
|
||||
|
|
@ -68,12 +67,8 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = {
|
|||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
|
||||
|
||||
DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC,
|
||||
CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
|
||||
R8A774A1_CLK_RPC),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
|
|
@ -100,10 +95,17 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = {
|
|||
DEF_FIXED("s3d2", R8A774A1_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A774A1_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c),
|
||||
DEF_GEN3_SDH("sd0h", R8A774A1_CLK_SD0H, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SDH("sd1h", R8A774A1_CLK_SD1H, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SDH("sd2h", R8A774A1_CLK_SD2H, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SDH("sd3h", R8A774A1_CLK_SD3H, CLK_SDSRC, 0x26c),
|
||||
DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, R8A774A1_CLK_SD0H, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, R8A774A1_CLK_SD1H, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, R8A774A1_CLK_SD2H, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, R8A774A1_CLK_SD3H, 0x26c),
|
||||
|
||||
DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774A1_CLK_RPC),
|
||||
|
||||
DEF_FIXED("cl", R8A774A1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A774A1_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
|
|
@ -210,7 +212,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] = {
|
|||
DEF_MOD("rpc-if", 917, R8A774A1_CLK_RPCD2),
|
||||
DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6),
|
||||
DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A774A1_CLK_CP),
|
||||
DEF_MOD("iic-pmic", 926, R8A774A1_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A774A1_CLK_S0D6),
|
||||
DEF_MOD("i2c3", 928, R8A774A1_CLK_S0D6),
|
||||
DEF_MOD("i2c2", 929, R8A774A1_CLK_S3D2),
|
||||
|
|
@ -329,7 +331,7 @@ static const struct cpg_mssr_info r8a774a1_cpg_mssr_info = {
|
|||
.get_pll_config = r8a774a1_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a774a1_clk_ids[] = {
|
||||
static const struct udevice_id r8a774a1_cpg_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a774a1-cpg-mssr",
|
||||
.data = (ulong)&r8a774a1_cpg_mssr_info,
|
||||
|
|
@ -337,12 +339,9 @@ static const struct udevice_id r8a774a1_clk_ids[] = {
|
|||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a774a1) = {
|
||||
.name = "clk_r8a774a1",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a774a1_clk_ids,
|
||||
.priv_auto = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
U_BOOT_DRIVER(cpg_r8a774a1) = {
|
||||
.name = "cpg_r8a774a1",
|
||||
.id = UCLASS_NOP,
|
||||
.of_match = r8a774a1_cpg_ids,
|
||||
.bind = gen3_cpg_bind,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* r8a774b1 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
* Copyright (C) 2019 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on r8a7796-cpg-mssr.c
|
||||
*
|
||||
|
|
@ -65,12 +65,8 @@ static const struct cpg_core_clk r8a774b1_core_clks[] = {
|
|||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
|
||||
|
||||
DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC,
|
||||
CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
|
||||
R8A774B1_CLK_RPC),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
|
|
@ -96,10 +92,17 @@ static const struct cpg_core_clk r8a774b1_core_clks[] = {
|
|||
DEF_FIXED("s3d2", R8A774B1_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A774B1_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, CLK_SDSRC, 0x26c),
|
||||
DEF_GEN3_SDH("sd0h", R8A774B1_CLK_SD0H, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SDH("sd1h", R8A774B1_CLK_SD1H, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SDH("sd2h", R8A774B1_CLK_SD2H, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SDH("sd3h", R8A774B1_CLK_SD3H, CLK_SDSRC, 0x26c),
|
||||
DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, R8A774B1_CLK_SD0H, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, R8A774B1_CLK_SD1H, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, R8A774B1_CLK_SD2H, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, R8A774B1_CLK_SD3H, 0x26c),
|
||||
|
||||
DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774B1_CLK_RPC),
|
||||
|
||||
DEF_FIXED("cl", R8A774B1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A774B1_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
|
|
@ -205,7 +208,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] = {
|
|||
DEF_MOD("rpc-if", 917, R8A774B1_CLK_RPCD2),
|
||||
DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6),
|
||||
DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A774B1_CLK_CP),
|
||||
DEF_MOD("iic-pmic", 926, R8A774B1_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A774B1_CLK_S0D6),
|
||||
DEF_MOD("i2c3", 928, R8A774B1_CLK_S0D6),
|
||||
DEF_MOD("i2c2", 929, R8A774B1_CLK_S3D2),
|
||||
|
|
@ -326,7 +329,7 @@ static const struct cpg_mssr_info r8a774b1_cpg_mssr_info = {
|
|||
.get_pll_config = r8a774b1_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a774b1_clk_ids[] = {
|
||||
static const struct udevice_id r8a774b1_cpg_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a774b1-cpg-mssr",
|
||||
.data = (ulong)&r8a774b1_cpg_mssr_info,
|
||||
|
|
@ -334,12 +337,9 @@ static const struct udevice_id r8a774b1_clk_ids[] = {
|
|||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a774b1) = {
|
||||
.name = "clk_r8a774b1",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a774b1_clk_ids,
|
||||
.priv_auto = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
U_BOOT_DRIVER(cpg_r8a774b1) = {
|
||||
.name = "cpg_r8a774b1",
|
||||
.id = UCLASS_NOP,
|
||||
.of_match = r8a774b1_cpg_ids,
|
||||
.bind = gen3_cpg_bind,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,12 +2,12 @@
|
|||
/*
|
||||
* r8a774c0 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on r8a77990-cpg-mssr.c
|
||||
*
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
|
@ -77,11 +77,6 @@ static const struct cpg_core_clk r8a774c0_core_clks[] = {
|
|||
|
||||
DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
|
||||
|
||||
DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC,
|
||||
CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
|
||||
R8A774C0_CLK_RPC),
|
||||
|
||||
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
|
||||
|
||||
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
|
||||
|
|
@ -108,9 +103,15 @@ static const struct cpg_core_clk r8a774c0_core_clks[] = {
|
|||
DEF_FIXED("s3d2", R8A774C0_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A774C0_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A774C0_CLK_SD0, CLK_SDSRC, 0x0074),
|
||||
DEF_GEN3_SD("sd1", R8A774C0_CLK_SD1, CLK_SDSRC, 0x0078),
|
||||
DEF_GEN3_SD("sd3", R8A774C0_CLK_SD3, CLK_SDSRC, 0x026c),
|
||||
DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774C0_CLK_RPC),
|
||||
|
||||
DEF_GEN3_SDH("sd0h", R8A774C0_CLK_SD0H, CLK_SDSRC, 0x0074),
|
||||
DEF_GEN3_SDH("sd1h", R8A774C0_CLK_SD1H, CLK_SDSRC, 0x0078),
|
||||
DEF_GEN3_SDH("sd3h", R8A774C0_CLK_SD3H, CLK_SDSRC, 0x026c),
|
||||
DEF_GEN3_SD("sd0", R8A774C0_CLK_SD0, R8A774C0_CLK_SD0H, 0x0074),
|
||||
DEF_GEN3_SD("sd1", R8A774C0_CLK_SD1, R8A774C0_CLK_SD1H, 0x0078),
|
||||
DEF_GEN3_SD("sd3", R8A774C0_CLK_SD3, R8A774C0_CLK_SD3H, 0x026c),
|
||||
|
||||
DEF_FIXED("cl", R8A774C0_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cp", R8A774C0_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
|
|
@ -210,7 +211,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] = {
|
|||
DEF_MOD("rpc-if", 917, R8A774C0_CLK_RPCD2),
|
||||
DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2),
|
||||
DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A774C0_CLK_CP),
|
||||
DEF_MOD("iic-pmic", 926, R8A774C0_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A774C0_CLK_S3D2),
|
||||
DEF_MOD("i2c3", 928, R8A774C0_CLK_S3D2),
|
||||
DEF_MOD("i2c2", 929, R8A774C0_CLK_S3D2),
|
||||
|
|
@ -299,7 +300,7 @@ const struct cpg_mssr_info r8a774c0_cpg_mssr_info = {
|
|||
.get_pll_config = r8a774c0_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a774c0_clk_ids[] = {
|
||||
static const struct udevice_id r8a774c0_cpg_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a774c0-cpg-mssr",
|
||||
.data = (ulong)&r8a774c0_cpg_mssr_info
|
||||
|
|
@ -307,12 +308,9 @@ static const struct udevice_id r8a774c0_clk_ids[] = {
|
|||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a774c0) = {
|
||||
.name = "clk_r8a774c0",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a774c0_clk_ids,
|
||||
.priv_auto = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
U_BOOT_DRIVER(cpg_r8a774c0) = {
|
||||
.name = "cpg_r8a774c0",
|
||||
.id = UCLASS_NOP,
|
||||
.of_match = r8a774c0_cpg_ids,
|
||||
.bind = gen3_cpg_bind,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -68,12 +68,8 @@ static const struct cpg_core_clk r8a774e1_core_clks[] = {
|
|||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
|
||||
|
||||
DEF_BASE("rpc", R8A774E1_CLK_RPC, CLK_TYPE_GEN3_RPC,
|
||||
CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A774E1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
|
||||
R8A774E1_CLK_RPC),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
|
|
@ -100,10 +96,17 @@ static const struct cpg_core_clk r8a774e1_core_clks[] = {
|
|||
DEF_FIXED("s3d2", R8A774E1_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A774E1_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, CLK_SDSRC, 0x26c),
|
||||
DEF_GEN3_SDH("sd0h", R8A774E1_CLK_SD0H, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SDH("sd1h", R8A774E1_CLK_SD1H, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SDH("sd2h", R8A774E1_CLK_SD2H, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SDH("sd3h", R8A774E1_CLK_SD3H, CLK_SDSRC, 0x26c),
|
||||
DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, R8A774E1_CLK_SD0H, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, R8A774E1_CLK_SD1H, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, R8A774E1_CLK_SD2H, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, R8A774E1_CLK_SD3H, 0x26c),
|
||||
|
||||
DEF_BASE("rpc", R8A774E1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A774E1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774E1_CLK_RPC),
|
||||
|
||||
DEF_FIXED("cl", R8A774E1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cr", R8A774E1_CLK_CR, CLK_PLL1_DIV4, 2, 1),
|
||||
|
|
@ -219,7 +222,7 @@ static const struct mssr_mod_clk r8a774e1_mod_clks[] = {
|
|||
DEF_MOD("i2c6", 918, R8A774E1_CLK_S0D6),
|
||||
DEF_MOD("i2c5", 919, R8A774E1_CLK_S0D6),
|
||||
DEF_MOD("adg", 922, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A774E1_CLK_CP),
|
||||
DEF_MOD("iic-pmic", 926, R8A774E1_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A774E1_CLK_S0D6),
|
||||
DEF_MOD("i2c3", 928, R8A774E1_CLK_S0D6),
|
||||
DEF_MOD("i2c2", 929, R8A774E1_CLK_S3D2),
|
||||
|
|
@ -340,7 +343,7 @@ static const struct cpg_mssr_info r8a774e1_cpg_mssr_info = {
|
|||
.get_pll_config = r8a774e1_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a774e1_clk_ids[] = {
|
||||
static const struct udevice_id r8a774e1_cpg_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a774e1-cpg-mssr",
|
||||
.data = (ulong)&r8a774e1_cpg_mssr_info
|
||||
|
|
@ -348,12 +351,9 @@ static const struct udevice_id r8a774e1_clk_ids[] = {
|
|||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a774e1) = {
|
||||
.name = "clk_r8a774e1",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a774e1_clk_ids,
|
||||
.priv_auto = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
U_BOOT_DRIVER(cpg_r8a774e1) = {
|
||||
.name = "cpg_r8a774e1",
|
||||
.id = UCLASS_NOP,
|
||||
.of_match = r8a774e1_cpg_ids,
|
||||
.bind = gen3_cpg_bind,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
* r8a7795 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
* Copyright (C) 2018-2019 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on clk-rcar-gen3.c
|
||||
*
|
||||
|
|
@ -69,12 +70,8 @@ static const struct cpg_core_clk r8a7795_core_clks[] = {
|
|||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
|
||||
|
||||
DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC,
|
||||
CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
|
||||
R8A7795_CLK_RPC),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
|
|
@ -102,10 +99,17 @@ static const struct cpg_core_clk r8a7795_core_clks[] = {
|
|||
DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
|
||||
DEF_GEN3_SDH("sd0h", R8A7795_CLK_SD0H, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SDH("sd1h", R8A7795_CLK_SD1H, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SDH("sd2h", R8A7795_CLK_SD2H, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SDH("sd3h", R8A7795_CLK_SD3H, CLK_SDSRC, 0x26c),
|
||||
DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, R8A7795_CLK_SD0H, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, R8A7795_CLK_SD1H, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, R8A7795_CLK_SD2H, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, R8A7795_CLK_SD3H, 0x26c),
|
||||
|
||||
DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A7795_CLK_RPC),
|
||||
|
||||
DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1),
|
||||
|
|
@ -126,6 +130,11 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
|
|||
DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("tmu4", 121, R8A7795_CLK_S0D6),
|
||||
DEF_MOD("tmu3", 122, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("tmu2", 123, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("tmu1", 124, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("tmu0", 125, R8A7795_CLK_CP),
|
||||
DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
|
||||
|
|
@ -222,6 +231,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
|
|||
DEF_MOD("lvds", 727, R8A7795_CLK_S0D4),
|
||||
DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
|
||||
DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
|
||||
DEF_MOD("mlp", 802, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("vin7", 804, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vin6", 805, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vin5", 806, R8A7795_CLK_S0D2),
|
||||
|
|
@ -370,7 +380,7 @@ static const struct cpg_mssr_info r8a7795_cpg_mssr_info = {
|
|||
.get_pll_config = r8a7795_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a7795_clk_ids[] = {
|
||||
static const struct udevice_id r8a7795_cpg_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a7795-cpg-mssr",
|
||||
.data = (ulong)&r8a7795_cpg_mssr_info
|
||||
|
|
@ -378,12 +388,9 @@ static const struct udevice_id r8a7795_clk_ids[] = {
|
|||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a7795) = {
|
||||
.name = "clk_r8a7795",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a7795_clk_ids,
|
||||
.priv_auto = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
U_BOOT_DRIVER(cpg_r8a7795) = {
|
||||
.name = "cpg_r8a7795",
|
||||
.id = UCLASS_NOP,
|
||||
.of_match = r8a7795_cpg_ids,
|
||||
.bind = gen3_cpg_bind,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,13 +1,10 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Renesas R8A7796 CPG MSSR driver
|
||||
* r8a7796 (R-Car M3-W/W+) Clock Pulse Generator / Module Standby and Software
|
||||
* Reset
|
||||
*
|
||||
* Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* Based on the following driver from Linux kernel:
|
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
* Copyright (C) 2016-2019 Glider bvba
|
||||
* Copyright (C) 2018-2019 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on r8a7795-cpg-mssr.c
|
||||
*
|
||||
|
|
@ -75,12 +72,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] = {
|
|||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
|
||||
|
||||
DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC,
|
||||
CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
|
||||
R8A7796_CLK_RPC),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
|
|
@ -108,10 +101,17 @@ static const struct cpg_core_clk r8a7796_core_clks[] = {
|
|||
DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
|
||||
DEF_GEN3_SDH("sd0h", R8A7796_CLK_SD0H, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SDH("sd1h", R8A7796_CLK_SD1H, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SDH("sd2h", R8A7796_CLK_SD2H, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SDH("sd3h", R8A7796_CLK_SD3H, CLK_SDSRC, 0x26c),
|
||||
DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, R8A7796_CLK_SD0H, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, R8A7796_CLK_SD1H, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, R8A7796_CLK_SD2H, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, R8A7796_CLK_SD3H, 0x26c),
|
||||
|
||||
DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A7796_CLK_RPC),
|
||||
|
||||
DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cr", R8A7796_CLK_CR, CLK_PLL1_DIV4, 2, 1),
|
||||
|
|
@ -209,6 +209,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
|
|||
DEF_MOD("du0", 724, R8A7796_CLK_S2D1),
|
||||
DEF_MOD("lvds", 727, R8A7796_CLK_S2D1),
|
||||
DEF_MOD("hdmi0", 729, R8A7796_CLK_HDMI),
|
||||
DEF_MOD("mlp", 802, R8A7796_CLK_S2D1),
|
||||
DEF_MOD("vin7", 804, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin6", 805, R8A7796_CLK_S0D2),
|
||||
DEF_MOD("vin5", 806, R8A7796_CLK_S0D2),
|
||||
|
|
@ -354,20 +355,36 @@ static const struct cpg_mssr_info r8a7796_cpg_mssr_info = {
|
|||
.get_pll_config = r8a7796_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a7796_clk_ids[] = {
|
||||
static const struct cpg_mssr_info r8a77961_cpg_mssr_info = {
|
||||
.core_clk = r8a7796_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a7796_core_clks),
|
||||
.mod_clk = r8a7796_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks),
|
||||
.mstp_table = r8a7796_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a7796_mstp_table),
|
||||
.reset_node = "renesas,r8a77961-rst",
|
||||
.extalr_node = "extalr",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extalr_id = CLK_EXTALR,
|
||||
.get_pll_config = r8a7796_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a7796_cpg_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a7796-cpg-mssr",
|
||||
.data = (ulong)&r8a7796_cpg_mssr_info,
|
||||
},
|
||||
{
|
||||
.compatible = "renesas,r8a77961-cpg-mssr",
|
||||
.data = (ulong)&r8a77961_cpg_mssr_info,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a7796) = {
|
||||
.name = "clk_r8a7796",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a7796_clk_ids,
|
||||
.priv_auto = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
U_BOOT_DRIVER(cpg_r8a7796) = {
|
||||
.name = "cpg_r8a7796",
|
||||
.id = UCLASS_NOP,
|
||||
.of_match = r8a7796_cpg_ids,
|
||||
.bind = gen3_cpg_bind,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
* r8a77965 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
|
||||
* Copyright (C) 2019 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on r8a7795-cpg-mssr.c
|
||||
*
|
||||
|
|
@ -68,12 +69,8 @@ static const struct cpg_core_clk r8a77965_core_clks[] = {
|
|||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
|
||||
|
||||
DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC,
|
||||
CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
|
||||
R8A77965_CLK_RPC),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
|
|
@ -100,10 +97,17 @@ static const struct cpg_core_clk r8a77965_core_clks[] = {
|
|||
DEF_FIXED("s3d2", R8A77965_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A77965_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c),
|
||||
DEF_GEN3_SDH("sd0h", R8A77965_CLK_SD0H, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SDH("sd1h", R8A77965_CLK_SD1H, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SDH("sd2h", R8A77965_CLK_SD2H, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SDH("sd3h", R8A77965_CLK_SD3H, CLK_SDSRC, 0x26c),
|
||||
DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, R8A77965_CLK_SD0H, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, R8A77965_CLK_SD1H, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, R8A77965_CLK_SD2H, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, R8A77965_CLK_SD3H, 0x26c),
|
||||
|
||||
DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77965_CLK_RPC),
|
||||
|
||||
DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cr", R8A77965_CLK_CR, CLK_PLL1_DIV4, 2, 1),
|
||||
|
|
@ -204,6 +208,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = {
|
|||
DEF_MOD("lvds", 727, R8A77965_CLK_S2D1),
|
||||
DEF_MOD("hdmi0", 729, R8A77965_CLK_HDMI),
|
||||
|
||||
DEF_MOD("mlp", 802, R8A77965_CLK_S2D1),
|
||||
DEF_MOD("vin7", 804, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vin6", 805, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vin5", 806, R8A77965_CLK_S0D2),
|
||||
|
|
@ -249,6 +254,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = {
|
|||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("dab", 1016, R8A77965_CLK_S0D6),
|
||||
DEF_MOD("scu-all", 1017, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
|
|
@ -352,7 +358,7 @@ static const struct cpg_mssr_info r8a77965_cpg_mssr_info = {
|
|||
.get_pll_config = r8a77965_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a77965_clk_ids[] = {
|
||||
static const struct udevice_id r8a77965_cpg_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a77965-cpg-mssr",
|
||||
.data = (ulong)&r8a77965_cpg_mssr_info,
|
||||
|
|
@ -360,12 +366,9 @@ static const struct udevice_id r8a77965_clk_ids[] = {
|
|||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a77965) = {
|
||||
.name = "clk_r8a77965",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a77965_clk_ids,
|
||||
.priv_auto = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
U_BOOT_DRIVER(cpg_r8a77965) = {
|
||||
.name = "cpg_r8a77965",
|
||||
.id = UCLASS_NOP,
|
||||
.of_match = r8a77965_cpg_ids,
|
||||
.bind = gen3_cpg_bind,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -22,11 +22,6 @@
|
|||
|
||||
#define CPG_SD0CKCR 0x0074
|
||||
|
||||
enum r8a77970_clk_types {
|
||||
CLK_TYPE_R8A77970_SD0H = CLK_TYPE_GEN3_SOC_BASE,
|
||||
CLK_TYPE_R8A77970_SD0,
|
||||
};
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
|
||||
|
|
@ -219,7 +214,7 @@ static const struct cpg_mssr_info r8a77970_cpg_mssr_info = {
|
|||
.get_pll_config = r8a77970_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a77970_clk_ids[] = {
|
||||
static const struct udevice_id r8a77970_cpg_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a77970-cpg-mssr",
|
||||
.data = (ulong)&r8a77970_cpg_mssr_info
|
||||
|
|
@ -227,12 +222,9 @@ static const struct udevice_id r8a77970_clk_ids[] = {
|
|||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a77970) = {
|
||||
.name = "clk_r8a77970",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a77970_clk_ids,
|
||||
.priv_auto = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
U_BOOT_DRIVER(cpg_r8a77970) = {
|
||||
.name = "cpg_r8a77970",
|
||||
.id = UCLASS_NOP,
|
||||
.of_match = r8a77970_cpg_ids,
|
||||
.bind = gen3_cpg_bind,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -65,13 +65,10 @@ static const struct cpg_core_clk r8a77980_core_clks[] = {
|
|||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
|
||||
DEF_RATE(".oco", CLK_OCO, 32768),
|
||||
|
||||
DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC,
|
||||
CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
|
||||
R8A77980_CLK_RPC),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
|
||||
|
||||
DEF_RATE(".oco", CLK_OCO, 32768),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
|
|
@ -95,7 +92,11 @@ static const struct cpg_core_clk r8a77980_core_clks[] = {
|
|||
DEF_FIXED("s3d2", R8A77980_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A77980_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, CLK_SDSRC, 0x0074),
|
||||
DEF_GEN3_SDH("sd0h", R8A77980_CLK_SD0H, CLK_SDSRC, 0x0074),
|
||||
DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, R8A77980_CLK_SD0H, 0x0074),
|
||||
|
||||
DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77980_CLK_RPC),
|
||||
|
||||
DEF_FIXED("cl", R8A77980_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A77980_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
|
|
@ -238,7 +239,7 @@ static const struct cpg_mssr_info r8a77980_cpg_mssr_info = {
|
|||
.get_pll_config = r8a77980_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a77980_clk_ids[] = {
|
||||
static const struct udevice_id r8a77980_cpg_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a77980-cpg-mssr",
|
||||
.data = (ulong)&r8a77980_cpg_mssr_info
|
||||
|
|
@ -246,12 +247,9 @@ static const struct udevice_id r8a77980_clk_ids[] = {
|
|||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a77980) = {
|
||||
.name = "clk_r8a77980",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a77980_clk_ids,
|
||||
.priv_auto = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
U_BOOT_DRIVER(cpg_r8a77980) = {
|
||||
.name = "cpg_r8a77980",
|
||||
.id = UCLASS_NOP,
|
||||
.of_match = r8a77980_cpg_ids,
|
||||
.bind = gen3_cpg_bind,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* r8a77990 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
* Copyright (C) 2018-2019 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on r8a7795-cpg-mssr.c
|
||||
*
|
||||
|
|
@ -77,11 +77,6 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
|
|||
|
||||
DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
|
||||
|
||||
DEF_BASE("rpc", R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC,
|
||||
CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
|
||||
R8A77990_CLK_RPC),
|
||||
|
||||
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
|
||||
|
||||
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
|
||||
|
|
@ -108,9 +103,15 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
|
|||
DEF_FIXED("s3d2", R8A77990_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A77990_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A77990_CLK_SD0, CLK_SDSRC, 0x0074),
|
||||
DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, CLK_SDSRC, 0x0078),
|
||||
DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, CLK_SDSRC, 0x026c),
|
||||
DEF_GEN3_SDH("sd0h", R8A77990_CLK_SD0H, CLK_SDSRC, 0x0074),
|
||||
DEF_GEN3_SDH("sd1h", R8A77990_CLK_SD1H, CLK_SDSRC, 0x0078),
|
||||
DEF_GEN3_SDH("sd3h", R8A77990_CLK_SD3H, CLK_SDSRC, 0x026c),
|
||||
DEF_GEN3_SD("sd0", R8A77990_CLK_SD0, R8A77990_CLK_SD0H, 0x0074),
|
||||
DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, R8A77990_CLK_SD1H, 0x0078),
|
||||
DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, R8A77990_CLK_SD3H, 0x026c),
|
||||
|
||||
DEF_BASE("rpc", R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77990_CLK_RPC),
|
||||
|
||||
DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cr", R8A77990_CLK_CR, CLK_PLL1D2, 2, 1),
|
||||
|
|
@ -205,6 +206,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
|
|||
DEF_MOD("du0", 724, R8A77990_CLK_S1D1),
|
||||
DEF_MOD("lvds", 727, R8A77990_CLK_S2D1),
|
||||
|
||||
DEF_MOD("mlp", 802, R8A77990_CLK_S2D1),
|
||||
DEF_MOD("vin5", 806, R8A77990_CLK_S1D2),
|
||||
DEF_MOD("vin4", 807, R8A77990_CLK_S1D2),
|
||||
DEF_MOD("etheravb", 812, R8A77990_CLK_S3D2),
|
||||
|
|
@ -219,7 +221,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
|
|||
DEF_MOD("can-fd", 914, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("rpc", 917, R8A77990_CLK_RPC),
|
||||
DEF_MOD("rpc-if", 917, R8A77990_CLK_RPCD2),
|
||||
DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP),
|
||||
|
|
@ -241,6 +243,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
|
|||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("dab", 1016, R8A77990_CLK_S3D1),
|
||||
DEF_MOD("scu-all", 1017, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
|
|
@ -311,7 +314,7 @@ static const struct cpg_mssr_info r8a77990_cpg_mssr_info = {
|
|||
.get_pll_config = r8a77990_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a77990_clk_ids[] = {
|
||||
static const struct udevice_id r8a77990_cpg_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a77990-cpg-mssr",
|
||||
.data = (ulong)&r8a77990_cpg_mssr_info
|
||||
|
|
@ -319,12 +322,9 @@ static const struct udevice_id r8a77990_clk_ids[] = {
|
|||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a77990) = {
|
||||
.name = "clk_r8a77990",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a77990_clk_ids,
|
||||
.priv_auto = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
U_BOOT_DRIVER(cpg_r8a77990) = {
|
||||
.name = "cpg_r8a77990",
|
||||
.id = UCLASS_NOP,
|
||||
.of_match = r8a77990_cpg_ids,
|
||||
.bind = gen3_cpg_bind,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -71,18 +71,14 @@ static const struct cpg_core_clk r8a77995_core_clks[] = {
|
|||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
|
||||
|
||||
DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC,
|
||||
CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
|
||||
R8A77995_CLK_RPC),
|
||||
DEF_FIXED_RPCSRC_D3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
|
||||
|
||||
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
|
||||
|
||||
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3, 2, 1),
|
||||
DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
|
||||
DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),
|
||||
|
|
@ -110,7 +106,11 @@ static const struct cpg_core_clk r8a77995_core_clks[] = {
|
|||
DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
|
||||
DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SDH("sd0h", R8A77995_CLK_SD0H, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, R8A77995_CLK_SD0H, 0x268),
|
||||
|
||||
DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77995_CLK_RPC),
|
||||
|
||||
DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244),
|
||||
DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014),
|
||||
|
|
@ -166,6 +166,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
|
|||
DEF_MOD("du1", 723, R8A77995_CLK_S1D1),
|
||||
DEF_MOD("du0", 724, R8A77995_CLK_S1D1),
|
||||
DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
|
||||
DEF_MOD("mlp", 802, R8A77995_CLK_S2D1),
|
||||
DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
|
||||
|
|
@ -179,7 +180,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
|
|||
DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("rpc", 917, R8A77995_CLK_RPC),
|
||||
DEF_MOD("rpc-if", 917, R8A77995_CLK_RPCD2),
|
||||
DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
|
||||
|
|
@ -249,7 +250,7 @@ static const struct cpg_mssr_info r8a77995_cpg_mssr_info = {
|
|||
.get_pll_config = r8a77995_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a77995_clk_ids[] = {
|
||||
static const struct udevice_id r8a77995_cpg_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a77995-cpg-mssr",
|
||||
.data = (ulong)&r8a77995_cpg_mssr_info
|
||||
|
|
@ -257,12 +258,9 @@ static const struct udevice_id r8a77995_clk_ids[] = {
|
|||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a77995) = {
|
||||
.name = "clk_r8a77995",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a77995_clk_ids,
|
||||
.priv_auto = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
U_BOOT_DRIVER(cpg_r8a77995) = {
|
||||
.name = "cpg_r8a77995",
|
||||
.id = UCLASS_NOP,
|
||||
.of_match = r8a77995_cpg_ids,
|
||||
.bind = gen3_cpg_bind,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -53,29 +53,18 @@ enum clk_ids {
|
|||
};
|
||||
|
||||
#define DEF_PLL(_name, _id, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \
|
||||
.offset = _offset)
|
||||
|
||||
#define DEF_SD(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SD, _parent, .offset = _offset)
|
||||
|
||||
#define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL, \
|
||||
(_parent0) << 16 | (_parent1), \
|
||||
.div = (_div0) << 16 | (_div1), .offset = _md)
|
||||
|
||||
#define DEF_OSC(_name, _id, _parent, _div) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div)
|
||||
|
||||
static const struct cpg_core_clk r8a779a0_core_clks[] = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("extalr", CLK_EXTALR),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN),
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
|
||||
DEF_PLL(".pll20", CLK_PLL20, 0x0834),
|
||||
DEF_PLL(".pll21", CLK_PLL21, 0x0838),
|
||||
DEF_PLL(".pll30", CLK_PLL30, 0x083c),
|
||||
|
|
@ -91,9 +80,14 @@ static const struct cpg_core_clk r8a779a0_core_clks[] = {
|
|||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV4, 1, 1),
|
||||
|
||||
DEF_RATE(".oco", CLK_OCO, 32768),
|
||||
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_GEN4_Z("z0", R8A779A0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL20, 2, 0),
|
||||
DEF_GEN4_Z("z1", R8A779A0_CLK_Z1, CLK_TYPE_GEN4_Z, CLK_PLL21, 2, 8),
|
||||
DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1),
|
||||
DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1),
|
||||
DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1),
|
||||
|
|
@ -107,7 +101,6 @@ static const struct cpg_core_clk r8a779a0_core_clks[] = {
|
|||
DEF_FIXED("zt", R8A779A0_CLK_ZT, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED("ztr", R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED("zr", R8A779A0_CLK_ZR, CLK_PLL1_DIV2, 1, 1),
|
||||
DEF_FIXED("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 1, 1),
|
||||
DEF_FIXED("cnndsp", R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4, 1, 1),
|
||||
DEF_FIXED("vip", R8A779A0_CLK_VIP, CLK_PLL5, 5, 1),
|
||||
DEF_FIXED("adgh", R8A779A0_CLK_ADGH, CLK_PLL5_DIV4, 1, 1),
|
||||
|
|
@ -116,15 +109,22 @@ static const struct cpg_core_clk r8a779a0_core_clks[] = {
|
|||
DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1),
|
||||
DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cl16mck", R8A779A0_CLK_CL16MCK, CLK_PLL1_DIV2, 64, 1),
|
||||
|
||||
DEF_SD("sd0", R8A779A0_CLK_SD0, CLK_SDSRC, 0x870),
|
||||
DEF_GEN4_SDH("sd0h", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870),
|
||||
DEF_GEN4_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, 0x870),
|
||||
|
||||
DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2,
|
||||
R8A779A0_CLK_RPC),
|
||||
|
||||
DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
|
||||
DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
|
||||
DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
|
||||
DEF_DIV6P1("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 0x884),
|
||||
|
||||
DEF_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8),
|
||||
DEF_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
|
||||
DEF_GEN4_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8),
|
||||
DEF_GEN4_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
|
||||
|
|
@ -134,10 +134,14 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
|
|||
DEF_MOD("avb3", 214, R8A779A0_CLK_S3D2),
|
||||
DEF_MOD("avb4", 215, R8A779A0_CLK_S3D2),
|
||||
DEF_MOD("avb5", 216, R8A779A0_CLK_S3D2),
|
||||
DEF_MOD("canfd0", 328, R8A779A0_CLK_CANFD),
|
||||
DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0),
|
||||
DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0),
|
||||
DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0),
|
||||
DEF_MOD("csi43", 402, R8A779A0_CLK_CSI0),
|
||||
DEF_MOD("du", 411, R8A779A0_CLK_S3D1),
|
||||
DEF_MOD("dsi0", 415, R8A779A0_CLK_DSI),
|
||||
DEF_MOD("dsi1", 416, R8A779A0_CLK_DSI),
|
||||
DEF_MOD("fcpvd0", 508, R8A779A0_CLK_S3D1),
|
||||
DEF_MOD("fcpvd1", 509, R8A779A0_CLK_S3D1),
|
||||
DEF_MOD("hscif0", 514, R8A779A0_CLK_S1D2),
|
||||
|
|
@ -151,12 +155,17 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
|
|||
DEF_MOD("i2c4", 522, R8A779A0_CLK_S1D4),
|
||||
DEF_MOD("i2c5", 523, R8A779A0_CLK_S1D4),
|
||||
DEF_MOD("i2c6", 524, R8A779A0_CLK_S1D4),
|
||||
DEF_MOD("ispcs0", 612, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("ispcs1", 613, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("ispcs2", 614, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("ispcs3", 615, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("msi0", 618, R8A779A0_CLK_MSO),
|
||||
DEF_MOD("msi1", 619, R8A779A0_CLK_MSO),
|
||||
DEF_MOD("msi2", 620, R8A779A0_CLK_MSO),
|
||||
DEF_MOD("msi3", 621, R8A779A0_CLK_MSO),
|
||||
DEF_MOD("msi4", 622, R8A779A0_CLK_MSO),
|
||||
DEF_MOD("msi5", 623, R8A779A0_CLK_MSO),
|
||||
DEF_MOD("rpc-if", 629, R8A779A0_CLK_RPCD2),
|
||||
DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8),
|
||||
DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8),
|
||||
DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8),
|
||||
|
|
@ -164,6 +173,12 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
|
|||
DEF_MOD("sdhi0", 706, R8A779A0_CLK_SD0),
|
||||
DEF_MOD("sydm1", 709, R8A779A0_CLK_S1D2),
|
||||
DEF_MOD("sydm2", 710, R8A779A0_CLK_S1D2),
|
||||
DEF_MOD("tmu0", 713, R8A779A0_CLK_CL16MCK),
|
||||
DEF_MOD("tmu1", 714, R8A779A0_CLK_S1D4),
|
||||
DEF_MOD("tmu2", 715, R8A779A0_CLK_S1D4),
|
||||
DEF_MOD("tmu3", 716, R8A779A0_CLK_S1D4),
|
||||
DEF_MOD("tmu4", 717, R8A779A0_CLK_S1D4),
|
||||
DEF_MOD("tpu0", 718, R8A779A0_CLK_S1D8),
|
||||
DEF_MOD("vin00", 730, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin01", 731, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vin02", 800, R8A779A0_CLK_S1D1),
|
||||
|
|
@ -199,10 +214,15 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
|
|||
DEF_MOD("vspd0", 830, R8A779A0_CLK_S3D1),
|
||||
DEF_MOD("vspd1", 831, R8A779A0_CLK_S3D1),
|
||||
DEF_MOD("rwdt", 907, R8A779A0_CLK_R),
|
||||
DEF_MOD("cmt0", 910, R8A779A0_CLK_R),
|
||||
DEF_MOD("cmt1", 911, R8A779A0_CLK_R),
|
||||
DEF_MOD("cmt2", 912, R8A779A0_CLK_R),
|
||||
DEF_MOD("cmt3", 913, R8A779A0_CLK_R),
|
||||
DEF_MOD("pfc0", 915, R8A779A0_CLK_CP),
|
||||
DEF_MOD("pfc1", 916, R8A779A0_CLK_CP),
|
||||
DEF_MOD("pfc2", 917, R8A779A0_CLK_CP),
|
||||
DEF_MOD("pfc3", 918, R8A779A0_CLK_CP),
|
||||
DEF_MOD("tsc", 919, R8A779A0_CLK_CL16MCK),
|
||||
DEF_MOD("vspx0", 1028, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vspx1", 1029, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vspx2", 1030, R8A779A0_CLK_S1D1),
|
||||
|
|
@ -281,7 +301,7 @@ static const struct cpg_mssr_info r8a779a0_cpg_mssr_info = {
|
|||
.reg_layout = CLK_REG_LAYOUT_RCAR_V3U,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a779a0_clk_ids[] = {
|
||||
static const struct udevice_id r8a779a0_cpg_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a779a0-cpg-mssr",
|
||||
.data = (ulong)&r8a779a0_cpg_mssr_info
|
||||
|
|
@ -289,12 +309,9 @@ static const struct udevice_id r8a779a0_clk_ids[] = {
|
|||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a779a0) = {
|
||||
.name = "clk_r8a779a0",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a779a0_clk_ids,
|
||||
.priv_auto = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
U_BOOT_DRIVER(cpg_r8a779a0) = {
|
||||
.name = "cpg_r8a779a0",
|
||||
.id = UCLASS_NOP,
|
||||
.of_match = r8a779a0_cpg_ids,
|
||||
.bind = gen3_cpg_bind,
|
||||
};
|
||||
|
|
|
|||
169
drivers/clk/renesas/rcar-cpg-lib.c
Normal file
169
drivers/clk/renesas/rcar-cpg-lib.c
Normal file
|
|
@ -0,0 +1,169 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Renesas RCar Gen3 CPG MSSR driver
|
||||
*
|
||||
* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
|
||||
*
|
||||
* Based on the following driver from Linux kernel:
|
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
#include <errno.h>
|
||||
#include <log.h>
|
||||
#include <wait_bit.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
#include "rcar-cpg-lib.h"
|
||||
|
||||
#define SDnSRCFC_SHIFT 2
|
||||
#define STPnHCK_TABLE (CPG_SDCKCR_STPnHCK >> SDnSRCFC_SHIFT)
|
||||
|
||||
/* Non-constant mask variant of FIELD_GET/FIELD_PREP */
|
||||
#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
|
||||
#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
|
||||
|
||||
static const struct clk_div_table cpg_sdh_div_table[] = {
|
||||
{ 0, 1 }, { 1, 2 }, { STPnHCK_TABLE | 2, 4 }, { STPnHCK_TABLE | 3, 8 },
|
||||
{ STPnHCK_TABLE | 4, 16 }, { 0, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_div_table cpg_sd_div_table[] = {
|
||||
{ 0, 2 }, { 1, 4 }, { 0, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_div_table cpg_rpc_div_table[] = {
|
||||
{ 1, 2 }, { 3, 4 }, { 5, 6 }, { 7, 8 }, { 0, 0 },
|
||||
};
|
||||
|
||||
static unsigned int rcar_clk_get_table_div(const struct clk_div_table *table,
|
||||
const u32 value)
|
||||
{
|
||||
const struct clk_div_table *clkt;
|
||||
|
||||
for (clkt = table; clkt->div; clkt++)
|
||||
if (clkt->val == value)
|
||||
return clkt->div;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rcar_clk_get_table_val(const struct clk_div_table *table,
|
||||
unsigned int div)
|
||||
{
|
||||
const struct clk_div_table *clkt;
|
||||
|
||||
for (clkt = table; clkt->div; clkt++)
|
||||
if (clkt->div == div)
|
||||
return clkt->val;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
s64 rcar_clk_get_rate64_div_table(unsigned int parent, u64 parent_rate,
|
||||
void __iomem *reg, const u32 mask,
|
||||
const struct clk_div_table *table, char *name)
|
||||
{
|
||||
u32 value, div;
|
||||
u64 rate;
|
||||
|
||||
value = field_get(mask, readl(reg));
|
||||
div = rcar_clk_get_table_div(table, value);
|
||||
if (!div)
|
||||
return -EINVAL;
|
||||
|
||||
rate = parent_rate / div;
|
||||
debug("%s[%i] %s clk: parent=%i div=%u => rate=%llu\n",
|
||||
__func__, __LINE__, name, parent, div, rate);
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
int rcar_clk_set_rate64_div_table(unsigned int parent, u64 parent_rate, ulong rate,
|
||||
void __iomem *reg, const u32 mask,
|
||||
const struct clk_div_table *table, char *name)
|
||||
{
|
||||
u32 value = 0, div = 0;
|
||||
|
||||
div = DIV_ROUND_CLOSEST(parent_rate, rate);
|
||||
value = rcar_clk_get_table_val(table, div);
|
||||
if (value < 0)
|
||||
return value;
|
||||
|
||||
clrsetbits_le32(reg, mask, field_prep(mask, value));
|
||||
|
||||
debug("%s[%i] %s clk: parent=%i div=%u rate=%lu => val=%u\n",
|
||||
__func__, __LINE__, name, parent, div, rate, value);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
s64 rcar_clk_get_rate64_rpc(unsigned int parent, u64 parent_rate, void __iomem *reg)
|
||||
{
|
||||
return rcar_clk_get_rate64_div_table(parent, parent_rate, reg,
|
||||
CPG_RPCCKCR_DIV_PRE_MASK,
|
||||
cpg_rpc_div_table, "RPC");
|
||||
}
|
||||
|
||||
u64 rcar_clk_get_rate64_rpcd2(unsigned int parent, u64 parent_rate)
|
||||
{
|
||||
u64 rate = 0;
|
||||
|
||||
rate = parent_rate / 2;
|
||||
debug("%s[%i] RPCD2 clk: parent=%i => rate=%llu\n",
|
||||
__func__, __LINE__, parent, rate);
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
s64 rcar_clk_get_rate64_sdh(unsigned int parent, u64 parent_rate, void __iomem *reg)
|
||||
{
|
||||
/*
|
||||
* This takes STPnHCK and STPnCK bits into consideration
|
||||
* in the table look up too, hence the inobvious GENMASK
|
||||
* below. Bits [7:5] always read zero, so this is OKish.
|
||||
*/
|
||||
return rcar_clk_get_rate64_div_table(parent, parent_rate, reg,
|
||||
CPG_SDCKCR_SRCFC_MASK |
|
||||
GENMASK(9, 5),
|
||||
cpg_sdh_div_table, "SDH");
|
||||
}
|
||||
|
||||
s64 rcar_clk_get_rate64_sd(unsigned int parent, u64 parent_rate, void __iomem *reg)
|
||||
{
|
||||
return rcar_clk_get_rate64_div_table(parent, parent_rate, reg,
|
||||
CPG_SDCKCR_FC_MASK,
|
||||
cpg_sd_div_table, "SD");
|
||||
}
|
||||
|
||||
int rcar_clk_set_rate64_sdh(unsigned int parent, u64 parent_rate, ulong rate,
|
||||
void __iomem *reg)
|
||||
{
|
||||
/*
|
||||
* This takes STPnHCK and STPnCK bits into consideration
|
||||
* in the table look up too, hence the inobvious GENMASK
|
||||
* below. Bits [7:5] always read zero, so this is OKish.
|
||||
*/
|
||||
return rcar_clk_set_rate64_div_table(parent, parent_rate, rate, reg,
|
||||
CPG_SDCKCR_SRCFC_MASK |
|
||||
GENMASK(9, 5),
|
||||
cpg_sdh_div_table, "SDH");
|
||||
}
|
||||
|
||||
int rcar_clk_set_rate64_sd(unsigned int parent, u64 parent_rate, ulong rate,
|
||||
void __iomem *reg)
|
||||
{
|
||||
return rcar_clk_set_rate64_div_table(parent, parent_rate, rate, reg,
|
||||
CPG_SDCKCR_FC_MASK,
|
||||
cpg_sd_div_table, "SD");
|
||||
}
|
||||
33
drivers/clk/renesas/rcar-cpg-lib.h
Normal file
33
drivers/clk/renesas/rcar-cpg-lib.h
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* R-Car Gen3 Clock Pulse Generator Library
|
||||
*
|
||||
* Copyright (C) 2015-2018 Glider bvba
|
||||
* Copyright (C) 2019 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on clk-rcar-gen3.c
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#ifndef __CLK_RENESAS_RCAR_CPG_LIB_H__
|
||||
#define __CLK_RENESAS_RCAR_CPG_LIB_H__
|
||||
|
||||
s64 rcar_clk_get_rate64_div_table(unsigned int parent, u64 parent_rate,
|
||||
void __iomem *reg, const u32 mask,
|
||||
const struct clk_div_table *table, char *name);
|
||||
|
||||
int rcar_clk_set_rate64_div_table(unsigned int parent, u64 parent_rate, ulong rate,
|
||||
void __iomem *reg, const u32 mask,
|
||||
const struct clk_div_table *table, char *name);
|
||||
|
||||
s64 rcar_clk_get_rate64_sdh(unsigned int parent, u64 parent_rate, void __iomem *reg);
|
||||
s64 rcar_clk_get_rate64_sd(unsigned int parent, u64 parent_rate, void __iomem *reg);
|
||||
s64 rcar_clk_get_rate64_rpc(unsigned int parent, u64 parent_rate, void __iomem *reg);
|
||||
u64 rcar_clk_get_rate64_rpcd2(unsigned int parent, u64 parent_rate);
|
||||
int rcar_clk_set_rate64_sdh(unsigned int parent, u64 parent_rate, ulong rate,
|
||||
void __iomem *reg);
|
||||
int rcar_clk_set_rate64_sd(unsigned int parent, u64 parent_rate, ulong rate,
|
||||
void __iomem *reg);
|
||||
|
||||
#endif
|
||||
|
|
@ -17,35 +17,44 @@ enum rcar_gen3_clk_types {
|
|||
CLK_TYPE_GEN3_PLL2,
|
||||
CLK_TYPE_GEN3_PLL3,
|
||||
CLK_TYPE_GEN3_PLL4,
|
||||
CLK_TYPE_GEN3_SDH,
|
||||
CLK_TYPE_R8A77970_SD0H,
|
||||
CLK_TYPE_GEN3_SD,
|
||||
CLK_TYPE_R8A77970_SD0,
|
||||
CLK_TYPE_GEN3_R,
|
||||
CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
|
||||
CLK_TYPE_GEN3_Z,
|
||||
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
|
||||
CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
|
||||
CLK_TYPE_GEN3_RPCSRC,
|
||||
CLK_TYPE_GEN3_D3_RPCSRC,
|
||||
CLK_TYPE_GEN3_E3_RPCSRC,
|
||||
CLK_TYPE_GEN3_RPC,
|
||||
CLK_TYPE_GEN3_RPCD2,
|
||||
|
||||
CLK_TYPE_R8A779A0_MAIN,
|
||||
CLK_TYPE_R8A779A0_PLL1,
|
||||
CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */
|
||||
CLK_TYPE_R8A779A0_PLL5,
|
||||
CLK_TYPE_R8A779A0_SD,
|
||||
CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */
|
||||
CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */
|
||||
CLK_TYPE_GEN4_MAIN,
|
||||
CLK_TYPE_GEN4_PLL1,
|
||||
CLK_TYPE_GEN4_PLL2X_3X, /* PLL[23][01] */
|
||||
CLK_TYPE_GEN4_PLL5,
|
||||
CLK_TYPE_GEN4_SDH,
|
||||
CLK_TYPE_GEN4_SD,
|
||||
CLK_TYPE_GEN4_MDSEL, /* Select parent/divider using mode pin */
|
||||
CLK_TYPE_GEN4_Z,
|
||||
CLK_TYPE_GEN4_OSC, /* OSC EXTAL predivider and fixed divider */
|
||||
CLK_TYPE_GEN4_RPCSRC,
|
||||
CLK_TYPE_GEN4_RPC,
|
||||
CLK_TYPE_GEN4_RPCD2,
|
||||
|
||||
/* SoC specific definitions start here */
|
||||
CLK_TYPE_GEN3_SOC_BASE,
|
||||
};
|
||||
|
||||
#define DEF_GEN3_SDH(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset)
|
||||
|
||||
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
|
||||
|
||||
#define DEF_GEN3_RPCD2(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPCD2, _parent, .offset = _offset)
|
||||
|
||||
#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
|
||||
(_parent0) << 16 | (_parent1), \
|
||||
|
|
@ -66,10 +75,31 @@ enum rcar_gen3_clk_types {
|
|||
#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \
|
||||
DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
|
||||
|
||||
#define DEF_FIXED_RPCSRC_D3(_name, _id, _parent0, _parent1) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_D3_RPCSRC, \
|
||||
(_parent0) << 16 | (_parent1), .div = 5)
|
||||
|
||||
#define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \
|
||||
(_parent0) << 16 | (_parent1), .div = 8)
|
||||
|
||||
#define DEF_GEN4_SDH(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
|
||||
|
||||
#define DEF_GEN4_SD(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
|
||||
|
||||
#define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \
|
||||
(_parent0) << 16 | (_parent1), \
|
||||
.div = (_div0) << 16 | (_div1), .offset = _md)
|
||||
|
||||
#define DEF_GEN4_OSC(_name, _id, _parent, _div) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
|
||||
|
||||
#define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \
|
||||
DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
|
||||
|
||||
struct rcar_gen3_cpg_pll_config {
|
||||
u8 extal_div;
|
||||
u8 pll1_mult;
|
||||
|
|
@ -83,7 +113,18 @@ struct rcar_gen3_cpg_pll_config {
|
|||
|
||||
#define CPG_RST_MODEMR 0x060
|
||||
|
||||
#define CPG_SDCKCR_STPnHCK BIT(9)
|
||||
#define CPG_SDCKCR_STPnCK BIT(8)
|
||||
#define CPG_SDCKCR_SRCFC_MASK GENMASK(4, 2)
|
||||
#define CPG_SDCKCR_FC_MASK GENMASK(1, 0)
|
||||
/* V3M specifics */
|
||||
#define CPG_SDCKCR_SDHFC_MASK GENMASK(11, 8)
|
||||
#define CPG_SDCKCR_SD0FC_MASK GENMASK(7, 4)
|
||||
|
||||
#define CPG_RPCCKCR 0x238
|
||||
#define CPG_RPCCKCR_DIV_POST_MASK GENMASK(4, 3)
|
||||
#define CPG_RPCCKCR_DIV_PRE_MASK GENMASK(2, 0)
|
||||
|
||||
#define CPG_RCKCR 0x240
|
||||
|
||||
struct gen3_clk_priv {
|
||||
|
|
@ -95,8 +136,7 @@ struct gen3_clk_priv {
|
|||
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
|
||||
};
|
||||
|
||||
int gen3_clk_probe(struct udevice *dev);
|
||||
int gen3_clk_remove(struct udevice *dev);
|
||||
int gen3_cpg_bind(struct udevice *parent);
|
||||
|
||||
extern const struct clk_ops gen3_clk_ops;
|
||||
|
||||
|
|
|
|||
|
|
@ -125,7 +125,7 @@ static void config_reg_helper(struct pinmux_info *gpioc,
|
|||
*maskp = (1 << crp->var_field_width[in_pos]) - 1;
|
||||
*posp = crp->reg_width;
|
||||
for (k = 0; k <= in_pos; k++)
|
||||
*posp -= crp->var_field_width[k];
|
||||
*posp -= abs(crp->var_field_width[k]);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -71,39 +71,25 @@
|
|||
|
||||
#define CALIB_TABLE_MAX (RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK + 1)
|
||||
|
||||
static const u8 r8a7795_calib_table[2][CALIB_TABLE_MAX] = {
|
||||
{ 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 5, 5, 6, 6, 7, 11,
|
||||
15, 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 21 },
|
||||
{ 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 12, 15,
|
||||
16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 22 }
|
||||
};
|
||||
|
||||
static const u8 r8a7796_rev1_calib_table[2][CALIB_TABLE_MAX] = {
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 9,
|
||||
15, 15, 15, 16, 16, 16, 16, 16, 17, 18, 19, 20, 21, 21, 22, 22 },
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
2, 9, 16, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 23, 24}
|
||||
};
|
||||
|
||||
static const u8 r8a7796_rev3_calib_table[2][CALIB_TABLE_MAX] = {
|
||||
{ 0, 0, 0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 9, 10,
|
||||
11, 12, 13, 15, 16, 17, 17, 18, 19, 19, 20, 21, 21, 22, 23, 23 },
|
||||
{ 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12,
|
||||
13, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22, 22, 23, 24, 24 }
|
||||
static const u8 r8a7796_rev13_calib_table[2][CALIB_TABLE_MAX] = {
|
||||
{ 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15,
|
||||
16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 },
|
||||
{ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11,
|
||||
12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 }
|
||||
};
|
||||
|
||||
static const u8 r8a77965_calib_table[2][CALIB_TABLE_MAX] = {
|
||||
{ 0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15,
|
||||
16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 29 },
|
||||
{ 0, 1, 2, 2, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 15,
|
||||
16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 31 }
|
||||
{ 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16,
|
||||
17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 },
|
||||
{ 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17,
|
||||
17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 }
|
||||
};
|
||||
|
||||
static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ 0, 0, 1, 2, 3, 4, 4, 4, 4, 5, 5, 6, 7, 8, 10, 11,
|
||||
12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 }
|
||||
{ 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10,
|
||||
11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 }
|
||||
};
|
||||
|
||||
static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv)
|
||||
|
|
@ -372,13 +358,21 @@ static int renesas_sdhi_hs400(struct udevice *dev)
|
|||
struct mmc *mmc = mmc_get_mmc_dev(dev);
|
||||
bool hs400 = (mmc->selected_mode == MMC_HS_400);
|
||||
int ret, taps = hs400 ? priv->nrtaps : 8;
|
||||
const u32 sdn_rate = 200000000;
|
||||
u32 sdnh_rate = 800000000;
|
||||
unsigned long new_tap;
|
||||
u32 reg;
|
||||
|
||||
if (taps == 4) /* HS400 on 4tap SoC needs different clock */
|
||||
ret = clk_set_rate(&priv->clk, 400000000);
|
||||
else
|
||||
ret = clk_set_rate(&priv->clk, 200000000);
|
||||
if (clk_valid(&priv->clkh) && !priv->needs_clkh_fallback) {
|
||||
/* HS400 on 4tap SoC => SDnH=400 MHz, SDn=200 MHz */
|
||||
if (taps == 4)
|
||||
sdnh_rate /= 2;
|
||||
ret = clk_set_rate(&priv->clkh, sdnh_rate);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_set_rate(&priv->clk, sdn_rate);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
|
|
@ -843,6 +837,7 @@ static const struct udevice_id renesas_sdhi_match[] = {
|
|||
{ .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
|
||||
{ .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
|
||||
{ .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
|
||||
{ .compatible = "renesas,sdhi-r8a77961", .data = RENESAS_GEN3_QUIRKS },
|
||||
{ .compatible = "renesas,rcar-gen3-sdhi", .data = RENESAS_GEN3_QUIRKS },
|
||||
{ .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
|
||||
{ .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
|
||||
|
|
@ -871,12 +866,16 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
|
|||
CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
|
||||
struct tmio_sd_plat *plat = dev_get_plat(dev);
|
||||
|
||||
/* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
|
||||
/* HS400 is not supported on H3 ES1.x, M3W ES1.[012], V3M, V3H ES1.x, D3 */
|
||||
if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
|
||||
(rmobile_get_cpu_rev_integer() <= 1)) ||
|
||||
((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
|
||||
(rmobile_get_cpu_rev_integer() == 1) &&
|
||||
(rmobile_get_cpu_rev_fraction() < 2)))
|
||||
(rmobile_get_cpu_rev_fraction() <= 2)) ||
|
||||
(rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77970) ||
|
||||
((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77980) &&
|
||||
(rmobile_get_cpu_rev_integer() <= 1)) ||
|
||||
(rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995))
|
||||
plat->cfg.host_caps &= ~MMC_MODE_HS400;
|
||||
|
||||
/* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */
|
||||
|
|
@ -888,36 +887,22 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
|
|||
(rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965))
|
||||
priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7);
|
||||
|
||||
/* H3 ES3.0 can use HS400 with manual adjustment */
|
||||
if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
|
||||
(rmobile_get_cpu_rev_integer() >= 3)) {
|
||||
priv->adjust_hs400_enable = true;
|
||||
priv->adjust_hs400_offset = 0;
|
||||
priv->adjust_hs400_calib_table =
|
||||
r8a7795_calib_table[!rmobile_is_gen3_mmc0(priv)];
|
||||
}
|
||||
|
||||
/* M3W ES1.2 can use HS400 with manual adjustment */
|
||||
if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
|
||||
(rmobile_get_cpu_rev_integer() == 1) &&
|
||||
(rmobile_get_cpu_rev_fraction() == 2)) {
|
||||
priv->adjust_hs400_enable = true;
|
||||
priv->adjust_hs400_offset = 3;
|
||||
priv->adjust_hs400_calib_table =
|
||||
r8a7796_rev1_calib_table[!rmobile_is_gen3_mmc0(priv)];
|
||||
}
|
||||
|
||||
/* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */
|
||||
if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
|
||||
(rmobile_get_cpu_rev_integer() == 1) &&
|
||||
(rmobile_get_cpu_rev_fraction() > 2)) {
|
||||
priv->adjust_hs400_enable = true;
|
||||
priv->adjust_hs400_offset = 0;
|
||||
priv->adjust_hs400_offset = 3;
|
||||
priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
|
||||
priv->adjust_hs400_calib_table =
|
||||
r8a7796_rev3_calib_table[!rmobile_is_gen3_mmc0(priv)];
|
||||
r8a7796_rev13_calib_table[!rmobile_is_gen3_mmc0(priv)];
|
||||
}
|
||||
|
||||
/* M3W+ bad taps */
|
||||
if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
|
||||
(rmobile_get_cpu_rev_integer() == 3))
|
||||
priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
|
||||
|
||||
/* M3N can use HS400 with manual adjustment */
|
||||
if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
|
||||
priv->adjust_hs400_enable = true;
|
||||
|
|
@ -934,12 +919,12 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
|
|||
r8a77990_calib_table[!rmobile_is_gen3_mmc0(priv)];
|
||||
}
|
||||
|
||||
/* H3 ES1.x, ES2.0 and M3W ES1.0, ES1.1, ES1.2 uses 4 tuning taps */
|
||||
/* H3 ES1.x, ES2.0 and M3W ES1.[0123] uses 4 tuning taps */
|
||||
if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
|
||||
(rmobile_get_cpu_rev_integer() <= 2)) ||
|
||||
((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
|
||||
(rmobile_get_cpu_rev_integer() == 1) &&
|
||||
(rmobile_get_cpu_rev_fraction() <= 2)))
|
||||
(rmobile_get_cpu_rev_fraction() <= 3)))
|
||||
priv->nrtaps = 4;
|
||||
else
|
||||
priv->nrtaps = 8;
|
||||
|
|
@ -953,6 +938,12 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
|
|||
priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
|
||||
else
|
||||
priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
|
||||
|
||||
/* V3M handles SD0H differently than other Gen3 SoCs */
|
||||
if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77970)
|
||||
priv->needs_clkh_fallback = true;
|
||||
else
|
||||
priv->needs_clkh_fallback = false;
|
||||
}
|
||||
|
||||
static int renesas_sdhi_probe(struct udevice *dev)
|
||||
|
|
@ -984,6 +975,11 @@ static int renesas_sdhi_probe(struct udevice *dev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
/* optional SDnH clock */
|
||||
ret = clk_get_by_name(dev, "clkh", &priv->clkh);
|
||||
if (ret < 0)
|
||||
dev_dbg(dev, "failed to get clkh\n");
|
||||
|
||||
/* set to max rate */
|
||||
ret = clk_set_rate(&priv->clk, 200000000);
|
||||
if (ret < 0) {
|
||||
|
|
|
|||
|
|
@ -138,6 +138,7 @@ struct tmio_sd_priv {
|
|||
#endif
|
||||
#if CONFIG_IS_ENABLED(CLK)
|
||||
struct clk clk;
|
||||
struct clk clkh;
|
||||
#endif
|
||||
#if CONFIG_IS_ENABLED(RENESAS_SDHI)
|
||||
unsigned int smpcmp;
|
||||
|
|
@ -151,6 +152,7 @@ struct tmio_sd_priv {
|
|||
u8 hs400_bad_tap;
|
||||
const u8 *adjust_hs400_calib_table;
|
||||
u32 quirks;
|
||||
bool needs_clkh_fallback;
|
||||
#endif
|
||||
ulong (*clk_get_rate)(struct tmio_sd_priv *);
|
||||
};
|
||||
|
|
|
|||
|
|
@ -693,12 +693,6 @@ int ravb_of_to_plat(struct udevice *dev)
|
|||
}
|
||||
|
||||
static const struct udevice_id ravb_ids[] = {
|
||||
{ .compatible = "renesas,etheravb-r8a7795" },
|
||||
{ .compatible = "renesas,etheravb-r8a7796" },
|
||||
{ .compatible = "renesas,etheravb-r8a77965" },
|
||||
{ .compatible = "renesas,etheravb-r8a77970" },
|
||||
{ .compatible = "renesas,etheravb-r8a77990" },
|
||||
{ .compatible = "renesas,etheravb-r8a77995" },
|
||||
{ .compatible = "renesas,etheravb-rcar-gen3" },
|
||||
{ }
|
||||
};
|
||||
|
|
|
|||
|
|
@ -65,17 +65,23 @@ config PINCTRL_PFC_R8A774E1
|
|||
help
|
||||
Support pin multiplexing control on Renesas RZ/G2H R8A774E1 SoCs.
|
||||
|
||||
config PINCTRL_PFC_R8A7795
|
||||
config PINCTRL_PFC_R8A77951
|
||||
bool "Renesas RCar Gen3 R8A7795 pin control driver"
|
||||
depends on PINCTRL_PFC
|
||||
help
|
||||
Support pin multiplexing control on Renesas RCar Gen3 R8A7795 SoCs.
|
||||
|
||||
config PINCTRL_PFC_R8A7796
|
||||
bool "Renesas RCar Gen3 R8A7796 pin control driver"
|
||||
config PINCTRL_PFC_R8A77960
|
||||
bool "Renesas RCar Gen3 R8A77960 pin control driver"
|
||||
depends on PINCTRL_PFC
|
||||
help
|
||||
Support pin multiplexing control on Renesas RCar Gen3 R8A7796 SoCs.
|
||||
Support pin multiplexing control on Renesas RCar Gen3 R8A77960 SoCs.
|
||||
|
||||
config PINCTRL_PFC_R8A77961
|
||||
bool "Renesas RCar Gen3 R8A77961 pin control driver"
|
||||
depends on PINCTRL_PFC
|
||||
help
|
||||
Support pin multiplexing control on Renesas RCar Gen3 R8A77961 SoCs.
|
||||
|
||||
config PINCTRL_PFC_R8A77965
|
||||
bool "Renesas RCar Gen3 R8A77965 pin control driver"
|
||||
|
|
|
|||
|
|
@ -8,8 +8,9 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
|
|||
obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77951) += pfc-r8a7795.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77960) += pfc-r8a7796.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77961) += pfc-r8a7796.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -16,15 +16,66 @@
|
|||
#include "sh_pfc.h"
|
||||
|
||||
#define CPU_ALL_GP(fn, sfx) \
|
||||
PORT_GP_32(0, fn, sfx), \
|
||||
PORT_GP_26(1, fn, sfx), \
|
||||
PORT_GP_32(2, fn, sfx), \
|
||||
PORT_GP_32(3, fn, sfx), \
|
||||
PORT_GP_32(4, fn, sfx), \
|
||||
PORT_GP_28(5, fn, sfx), \
|
||||
PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_1(6, 24, fn, sfx), \
|
||||
PORT_GP_1(6, 25, fn, sfx)
|
||||
PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_26(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_7(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_1(5, 7, fn, sfx), \
|
||||
PORT_GP_1(5, 8, fn, sfx), \
|
||||
PORT_GP_1(5, 9, fn, sfx), \
|
||||
PORT_GP_CFG_1(5, 10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(5, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(5, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(5, 13, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(5, 14, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(5, 15, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(5, 16, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(5, 17, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(5, 18, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(5, 19, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(5, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(5, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(5, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(5, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_1(5, 24, fn, sfx), \
|
||||
PORT_GP_1(5, 25, fn, sfx), \
|
||||
PORT_GP_1(5, 26, fn, sfx), \
|
||||
PORT_GP_1(5, 27, fn, sfx), \
|
||||
PORT_GP_CFG_1(6, 0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_CFG_1(6, 1, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 11, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 12, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_CFG_1(6, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 23, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
|
||||
|
||||
#define CPU_ALL_NOGP(fn) \
|
||||
PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
|
||||
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
|
||||
|
||||
enum {
|
||||
PINMUX_RESERVED = 0,
|
||||
|
|
@ -1437,8 +1488,17 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
|
||||
};
|
||||
|
||||
/*
|
||||
* Pins not associated with a GPIO port.
|
||||
*/
|
||||
enum {
|
||||
GP_ASSIGN_LAST(),
|
||||
NOGP_ALL(),
|
||||
};
|
||||
|
||||
static const struct sh_pfc_pin pinmux_pins[] = {
|
||||
PINMUX_GPIO_GP_ALL(),
|
||||
PINMUX_NOGP_ALL(),
|
||||
};
|
||||
|
||||
/* - Audio Clock ------------------------------------------------------------ */
|
||||
|
|
@ -2329,29 +2389,14 @@ static const unsigned int intc_irq9_mux[] = {
|
|||
IRQ9_MARK,
|
||||
};
|
||||
/* - MMCIF ------------------------------------------------------------------ */
|
||||
static const unsigned int mmc_data1_pins[] = {
|
||||
/* D[0] */
|
||||
RCAR_GP_PIN(6, 18),
|
||||
};
|
||||
static const unsigned int mmc_data1_mux[] = {
|
||||
MMC_D0_MARK,
|
||||
};
|
||||
static const unsigned int mmc_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
|
||||
RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
|
||||
};
|
||||
static const unsigned int mmc_data4_mux[] = {
|
||||
MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
|
||||
};
|
||||
static const unsigned int mmc_data8_pins[] = {
|
||||
static const unsigned int mmc_data_pins[] = {
|
||||
/* D[0:7] */
|
||||
RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
|
||||
RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
|
||||
RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
|
||||
RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
|
||||
};
|
||||
static const unsigned int mmc_data8_mux[] = {
|
||||
static const unsigned int mmc_data_mux[] = {
|
||||
MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
|
||||
MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
|
||||
};
|
||||
|
|
@ -2686,19 +2731,12 @@ static const unsigned int qspi_ctrl_pins[] = {
|
|||
static const unsigned int qspi_ctrl_mux[] = {
|
||||
SPCLK_MARK, SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi_data2_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1 */
|
||||
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
|
||||
};
|
||||
static const unsigned int qspi_data2_mux[] = {
|
||||
MOSI_IO0_MARK, MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi_data4_pins[] = {
|
||||
static const unsigned int qspi_data_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
|
||||
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(1, 8),
|
||||
};
|
||||
static const unsigned int qspi_data4_mux[] = {
|
||||
static const unsigned int qspi_data_mux[] = {
|
||||
MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
|
||||
};
|
||||
/* - SCIF0 ------------------------------------------------------------------ */
|
||||
|
|
@ -3173,19 +3211,12 @@ static const unsigned int scif_clk_b_mux[] = {
|
|||
SCIF_CLK_B_MARK,
|
||||
};
|
||||
/* - SDHI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi0_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(6, 2),
|
||||
};
|
||||
static const unsigned int sdhi0_data1_mux[] = {
|
||||
SD0_DATA0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi0_data4_pins[] = {
|
||||
static const unsigned int sdhi0_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
|
||||
RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
|
||||
};
|
||||
static const unsigned int sdhi0_data4_mux[] = {
|
||||
static const unsigned int sdhi0_data_mux[] = {
|
||||
SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi0_ctrl_pins[] = {
|
||||
|
|
@ -3210,19 +3241,12 @@ static const unsigned int sdhi0_wp_mux[] = {
|
|||
SD0_WP_MARK,
|
||||
};
|
||||
/* - SDHI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi1_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(6, 10),
|
||||
};
|
||||
static const unsigned int sdhi1_data1_mux[] = {
|
||||
SD1_DATA0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi1_data4_pins[] = {
|
||||
static const unsigned int sdhi1_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
|
||||
RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
|
||||
};
|
||||
static const unsigned int sdhi1_data4_mux[] = {
|
||||
static const unsigned int sdhi1_data_mux[] = {
|
||||
SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi1_ctrl_pins[] = {
|
||||
|
|
@ -3247,19 +3271,12 @@ static const unsigned int sdhi1_wp_mux[] = {
|
|||
SD1_WP_MARK,
|
||||
};
|
||||
/* - SDHI2 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi2_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(6, 18),
|
||||
};
|
||||
static const unsigned int sdhi2_data1_mux[] = {
|
||||
SD2_DATA0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_data4_pins[] = {
|
||||
static const unsigned int sdhi2_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
|
||||
RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
|
||||
};
|
||||
static const unsigned int sdhi2_data4_mux[] = {
|
||||
static const unsigned int sdhi2_data_mux[] = {
|
||||
SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_ctrl_pins[] = {
|
||||
|
|
@ -3614,43 +3631,39 @@ static const unsigned int usb1_mux[] = {
|
|||
USB1_OVC_MARK,
|
||||
};
|
||||
/* - VIN0 ------------------------------------------------------------------- */
|
||||
static const union vin_data vin0_data_pins = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
|
||||
RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
|
||||
RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
|
||||
RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
|
||||
/* G */
|
||||
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
|
||||
RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
|
||||
RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
|
||||
RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
|
||||
/* R */
|
||||
RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
|
||||
RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
|
||||
RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
|
||||
RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
|
||||
},
|
||||
static const unsigned int vin0_data_pins[] = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
|
||||
RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
|
||||
RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
|
||||
RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
|
||||
/* G */
|
||||
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
|
||||
RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
|
||||
RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
|
||||
RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
|
||||
/* R */
|
||||
RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
|
||||
RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
|
||||
RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
|
||||
RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
|
||||
};
|
||||
static const union vin_data vin0_data_mux = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
|
||||
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
|
||||
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
|
||||
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
|
||||
/* G */
|
||||
VI0_G0_MARK, VI0_G1_MARK,
|
||||
VI0_G2_MARK, VI0_G3_MARK,
|
||||
VI0_G4_MARK, VI0_G5_MARK,
|
||||
VI0_G6_MARK, VI0_G7_MARK,
|
||||
/* R */
|
||||
VI0_R0_MARK, VI0_R1_MARK,
|
||||
VI0_R2_MARK, VI0_R3_MARK,
|
||||
VI0_R4_MARK, VI0_R5_MARK,
|
||||
VI0_R6_MARK, VI0_R7_MARK,
|
||||
},
|
||||
static const unsigned int vin0_data_mux[] = {
|
||||
/* B */
|
||||
VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
|
||||
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
|
||||
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
|
||||
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
|
||||
/* G */
|
||||
VI0_G0_MARK, VI0_G1_MARK,
|
||||
VI0_G2_MARK, VI0_G3_MARK,
|
||||
VI0_G4_MARK, VI0_G5_MARK,
|
||||
VI0_G6_MARK, VI0_G7_MARK,
|
||||
/* R */
|
||||
VI0_R0_MARK, VI0_R1_MARK,
|
||||
VI0_R2_MARK, VI0_R3_MARK,
|
||||
VI0_R4_MARK, VI0_R5_MARK,
|
||||
VI0_R6_MARK, VI0_R7_MARK,
|
||||
};
|
||||
static const unsigned int vin0_data18_pins[] = {
|
||||
/* B */
|
||||
|
|
@ -3707,25 +3720,21 @@ static const unsigned int vin0_clk_mux[] = {
|
|||
VI0_CLK_MARK,
|
||||
};
|
||||
/* - VIN1 ------------------------------------------------------------------- */
|
||||
static const union vin_data12 vin1_data_pins = {
|
||||
.data12 = {
|
||||
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
|
||||
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
|
||||
RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
|
||||
RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
|
||||
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
},
|
||||
static const unsigned int vin1_data_pins[] = {
|
||||
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
|
||||
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
|
||||
RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
|
||||
RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
|
||||
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
};
|
||||
static const union vin_data12 vin1_data_mux = {
|
||||
.data12 = {
|
||||
VI1_DATA0_MARK, VI1_DATA1_MARK,
|
||||
VI1_DATA2_MARK, VI1_DATA3_MARK,
|
||||
VI1_DATA4_MARK, VI1_DATA5_MARK,
|
||||
VI1_DATA6_MARK, VI1_DATA7_MARK,
|
||||
VI1_DATA8_MARK, VI1_DATA9_MARK,
|
||||
VI1_DATA10_MARK, VI1_DATA11_MARK,
|
||||
},
|
||||
static const unsigned int vin1_data_mux[] = {
|
||||
VI1_DATA0_MARK, VI1_DATA1_MARK,
|
||||
VI1_DATA2_MARK, VI1_DATA3_MARK,
|
||||
VI1_DATA4_MARK, VI1_DATA5_MARK,
|
||||
VI1_DATA6_MARK, VI1_DATA7_MARK,
|
||||
VI1_DATA8_MARK, VI1_DATA9_MARK,
|
||||
VI1_DATA10_MARK, VI1_DATA11_MARK,
|
||||
};
|
||||
static const unsigned int vin1_sync_pins[] = {
|
||||
RCAR_GP_PIN(5, 22), /* HSYNC */
|
||||
|
|
@ -3864,9 +3873,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(intc_irq7),
|
||||
SH_PFC_PIN_GROUP(intc_irq8),
|
||||
SH_PFC_PIN_GROUP(intc_irq9),
|
||||
SH_PFC_PIN_GROUP(mmc_data1),
|
||||
SH_PFC_PIN_GROUP(mmc_data4),
|
||||
SH_PFC_PIN_GROUP(mmc_data8),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 1),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 4),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 8),
|
||||
SH_PFC_PIN_GROUP(mmc_ctrl),
|
||||
SH_PFC_PIN_GROUP(msiof0_clk),
|
||||
SH_PFC_PIN_GROUP(msiof0_sync),
|
||||
|
|
@ -3916,8 +3925,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(pwm6),
|
||||
SH_PFC_PIN_GROUP(pwm6_b),
|
||||
SH_PFC_PIN_GROUP(qspi_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi_data2),
|
||||
SH_PFC_PIN_GROUP(qspi_data4),
|
||||
BUS_DATA_PIN_GROUP(qspi_data, 2),
|
||||
BUS_DATA_PIN_GROUP(qspi_data, 4),
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
SH_PFC_PIN_GROUP(scif0_data_b),
|
||||
SH_PFC_PIN_GROUP(scif0_data_c),
|
||||
|
|
@ -3983,18 +3992,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(scifb2_ctrl),
|
||||
SH_PFC_PIN_GROUP(scif_clk),
|
||||
SH_PFC_PIN_GROUP(scif_clk_b),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi0_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi0_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi1_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi1_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi2_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi2_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi2_wp),
|
||||
|
|
@ -4046,20 +4055,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(tpu_to3_c),
|
||||
SH_PFC_PIN_GROUP(usb0),
|
||||
SH_PFC_PIN_GROUP(usb1),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 24),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 20),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 24),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 20),
|
||||
SH_PFC_PIN_GROUP(vin0_data18),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 16),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 16),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 8),
|
||||
SH_PFC_PIN_GROUP(vin0_sync),
|
||||
SH_PFC_PIN_GROUP(vin0_field),
|
||||
SH_PFC_PIN_GROUP(vin0_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin0_clk),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 8),
|
||||
SH_PFC_PIN_GROUP(vin1_sync),
|
||||
SH_PFC_PIN_GROUP(vin1_field),
|
||||
SH_PFC_PIN_GROUP(vin1_clkenb),
|
||||
|
|
@ -4859,7 +4868,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
},
|
||||
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
|
||||
GROUP(2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
1, 1, 1, 1, 2, -7, 1),
|
||||
GROUP(
|
||||
/* IP0_31_30 [2] */
|
||||
FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
|
||||
|
|
@ -4895,25 +4904,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
FN_MMC_CLK, FN_SD2_CLK,
|
||||
/* IP0_9_8 [2] */
|
||||
FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
|
||||
/* IP0_7 [1] */
|
||||
0, 0,
|
||||
/* IP0_6 [1] */
|
||||
0, 0,
|
||||
/* IP0_5 [1] */
|
||||
0, 0,
|
||||
/* IP0_4 [1] */
|
||||
0, 0,
|
||||
/* IP0_3 [1] */
|
||||
0, 0,
|
||||
/* IP0_2 [1] */
|
||||
0, 0,
|
||||
/* IP0_1 [1] */
|
||||
0, 0,
|
||||
/* IP0_7_1 [7] RESERVED */
|
||||
/* IP0_0 [1] */
|
||||
FN_SD1_CD, FN_CAN0_RX, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
|
||||
GROUP(2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2,
|
||||
GROUP(2, 2, 1, 1, -1, 1, 2, 2, 2, 3, 2, 2,
|
||||
3, 2, 2, 2, 2),
|
||||
GROUP(
|
||||
/* IP1_31_30 [2] */
|
||||
|
|
@ -4924,8 +4920,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
FN_A4, FN_SCIFB0_TXD,
|
||||
/* IP1_26 [1] */
|
||||
FN_A3, FN_SCIFB0_SCK,
|
||||
/* IP1_25 [1] */
|
||||
0, 0,
|
||||
/* IP1_25 [1] RESERVED */
|
||||
/* IP1_24 [1] */
|
||||
FN_A1, FN_SCIFB1_TXD,
|
||||
/* IP1_23_22 [2] */
|
||||
|
|
@ -5152,12 +5147,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
|
||||
GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
|
||||
GROUP(1, -1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
|
||||
GROUP(
|
||||
/* IP7_31 [1] */
|
||||
FN_DREQ0_N, FN_SCIFB1_RXD,
|
||||
/* IP7_30 [1] */
|
||||
0, 0,
|
||||
/* IP7_30 [1] RESERVED */
|
||||
/* IP7_29_27 [3] */
|
||||
FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
|
||||
FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
|
||||
|
|
@ -5226,10 +5220,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
|
||||
GROUP(1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3),
|
||||
GROUP(-1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3),
|
||||
GROUP(
|
||||
/* IP9_31 [1] */
|
||||
0, 0,
|
||||
/* IP9_31 [1] RESERVED */
|
||||
/* IP9_30_28 [3] */
|
||||
FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5,
|
||||
FN_SSI_SDATA1_B, 0, 0, 0,
|
||||
|
|
@ -5299,10 +5292,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
0, 0, 0, 0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
|
||||
GROUP(2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3),
|
||||
GROUP(-2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3),
|
||||
GROUP(
|
||||
/* IP11_31_30 [2] */
|
||||
0, 0, 0, 0,
|
||||
/* IP11_31_30 [2] RESERVED */
|
||||
/* IP11_29_27 [3] */
|
||||
FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
|
||||
0, 0, 0, 0,
|
||||
|
|
@ -5335,10 +5327,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
0, 0, 0, 0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
|
||||
GROUP(2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3),
|
||||
GROUP(-2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3),
|
||||
GROUP(
|
||||
/* IP12_31_30 [2] */
|
||||
0, 0, 0, 0,
|
||||
/* IP12_31_30 [2] RESERVED */
|
||||
/* IP12_29_27 [3] */
|
||||
FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, 0,
|
||||
FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0,
|
||||
|
|
@ -5371,18 +5362,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
0, FN_DREQ1_N_B, 0, 0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
|
||||
GROUP(1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3),
|
||||
GROUP(-5, 3, 3, 3, 3, 3, 3, 3, 3, 3),
|
||||
GROUP(
|
||||
/* IP13_31 [1] */
|
||||
0, 0,
|
||||
/* IP13_30 [1] */
|
||||
0, 0,
|
||||
/* IP13_29 [1] */
|
||||
0, 0,
|
||||
/* IP13_28 [1] */
|
||||
0, 0,
|
||||
/* IP13_27 [1] */
|
||||
0, 0,
|
||||
/* IP13_31_27 [5] RESERVED */
|
||||
/* IP13_26_24 [3] */
|
||||
FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
|
||||
FN_TS_SPSYNC_C, 0, FN_FMIN_E, 0,
|
||||
|
|
@ -5412,23 +5394,21 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
0, FN_ATACS00_N, FN_ETH_LINK_B, 0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
|
||||
GROUP(2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, 2, 1),
|
||||
GROUP(2, -1, 2, 3, -4, 1, -1,
|
||||
3, 3, 3, 3, 3, 2, -1),
|
||||
GROUP(
|
||||
/* SEL_ADG [2] */
|
||||
FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
|
||||
/* RESERVED [1] */
|
||||
0, 0,
|
||||
/* SEL_CAN [2] */
|
||||
FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
|
||||
/* SEL_DARC [3] */
|
||||
FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
|
||||
FN_SEL_DARC_4, 0, 0, 0,
|
||||
/* RESERVED [4] */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* SEL_ETH [1] */
|
||||
FN_SEL_ETH_0, FN_SEL_ETH_1,
|
||||
/* RESERVED [1] */
|
||||
0, 0,
|
||||
/* SEL_IC200 [3] */
|
||||
FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
|
||||
FN_SEL_I2C00_4, 0, 0, 0,
|
||||
|
|
@ -5446,12 +5426,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
FN_SEL_I2C04_4, 0, 0, 0,
|
||||
/* SEL_I2C05 [2] */
|
||||
FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
|
||||
/* RESERVED [1] */
|
||||
0, 0, ))
|
||||
/* RESERVED [1] */ ))
|
||||
},
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
|
||||
GROUP(2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1,
|
||||
2, 2, 1, 1, 2, 2, 2, 1, 1, 2),
|
||||
2, 2, -1, 1, 2, 2, 2, 1, 1, -2),
|
||||
GROUP(
|
||||
/* SEL_IEB [2] */
|
||||
FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
|
||||
|
|
@ -5485,7 +5464,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
|
||||
FN_SEL_SCIFA5_3,
|
||||
/* RESERVED [1] */
|
||||
0, 0,
|
||||
/* SEL_TMU [1] */
|
||||
FN_SEL_TMU_0, FN_SEL_TMU_1,
|
||||
/* SEL_TSIF0 [2] */
|
||||
|
|
@ -5498,12 +5476,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
|
||||
/* SEL_HSCIF1 [1] */
|
||||
FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
|
||||
/* RESERVED [2] */
|
||||
0, 0, 0, 0, ))
|
||||
/* RESERVED [2] */ ))
|
||||
},
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
|
||||
GROUP(2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
1, 1, -12),
|
||||
GROUP(
|
||||
/* SEL_SCIF0 [2] */
|
||||
FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
|
||||
|
|
@ -5534,36 +5511,16 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
FN_SEL_SSI8_0, FN_SEL_SSI8_1,
|
||||
/* SEL_SSI9 [1] */
|
||||
FN_SEL_SSI9_0, FN_SEL_SSI9_1,
|
||||
/* RESERVED [1] */
|
||||
0, 0,
|
||||
/* RESERVED [1] */
|
||||
0, 0,
|
||||
/* RESERVED [1] */
|
||||
0, 0,
|
||||
/* RESERVED [1] */
|
||||
0, 0,
|
||||
/* RESERVED [1] */
|
||||
0, 0,
|
||||
/* RESERVED [1] */
|
||||
0, 0,
|
||||
/* RESERVED [1] */
|
||||
0, 0,
|
||||
/* RESERVED [1] */
|
||||
0, 0,
|
||||
/* RESERVED [1] */
|
||||
0, 0,
|
||||
/* RESERVED [1] */
|
||||
0, 0,
|
||||
/* RESERVED [1] */
|
||||
0, 0,
|
||||
/* RESERVED [1] */
|
||||
0, 0, ))
|
||||
/* RESERVED [12] */ ))
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
|
||||
static int r8a7794_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
|
||||
return -EINVAL;
|
||||
|
||||
*pocctrl = 0xe606006c;
|
||||
|
||||
switch (pin & 0x1f) {
|
||||
|
|
@ -5581,6 +5538,284 @@ static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
{ PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(0, 0), /* D0 */
|
||||
[ 1] = RCAR_GP_PIN(0, 1), /* D1 */
|
||||
[ 2] = RCAR_GP_PIN(0, 2), /* D2 */
|
||||
[ 3] = RCAR_GP_PIN(0, 3), /* D3 */
|
||||
[ 4] = RCAR_GP_PIN(0, 4), /* D4 */
|
||||
[ 5] = RCAR_GP_PIN(0, 5), /* D5 */
|
||||
[ 6] = RCAR_GP_PIN(0, 6), /* D6 */
|
||||
[ 7] = RCAR_GP_PIN(0, 7), /* D7 */
|
||||
[ 8] = RCAR_GP_PIN(0, 8), /* D8 */
|
||||
[ 9] = RCAR_GP_PIN(0, 9), /* D9 */
|
||||
[10] = RCAR_GP_PIN(0, 10), /* D10 */
|
||||
[11] = RCAR_GP_PIN(0, 11), /* D11 */
|
||||
[12] = RCAR_GP_PIN(0, 12), /* D12 */
|
||||
[13] = RCAR_GP_PIN(0, 13), /* D13 */
|
||||
[14] = RCAR_GP_PIN(0, 14), /* D14 */
|
||||
[15] = RCAR_GP_PIN(0, 15), /* D15 */
|
||||
[16] = RCAR_GP_PIN(0, 16), /* A0 */
|
||||
[17] = RCAR_GP_PIN(0, 17), /* A1 */
|
||||
[18] = RCAR_GP_PIN(0, 18), /* A2 */
|
||||
[19] = RCAR_GP_PIN(0, 19), /* A3 */
|
||||
[20] = RCAR_GP_PIN(0, 20), /* A4 */
|
||||
[21] = RCAR_GP_PIN(0, 21), /* A5 */
|
||||
[22] = RCAR_GP_PIN(0, 22), /* A6 */
|
||||
[23] = RCAR_GP_PIN(0, 23), /* A7 */
|
||||
[24] = RCAR_GP_PIN(0, 24), /* A8 */
|
||||
[25] = RCAR_GP_PIN(0, 25), /* A9 */
|
||||
[26] = RCAR_GP_PIN(0, 26), /* A10 */
|
||||
[27] = RCAR_GP_PIN(0, 27), /* A11 */
|
||||
[28] = RCAR_GP_PIN(0, 28), /* A12 */
|
||||
[29] = RCAR_GP_PIN(0, 29), /* A13 */
|
||||
[30] = RCAR_GP_PIN(0, 30), /* A14 */
|
||||
[31] = RCAR_GP_PIN(0, 31), /* A15 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
|
||||
/* PUPR1 pull-up pins */
|
||||
[ 0] = RCAR_GP_PIN(1, 0), /* A16 */
|
||||
[ 1] = RCAR_GP_PIN(1, 1), /* A17 */
|
||||
[ 2] = RCAR_GP_PIN(1, 2), /* A18 */
|
||||
[ 3] = RCAR_GP_PIN(1, 3), /* A19 */
|
||||
[ 4] = RCAR_GP_PIN(1, 4), /* A20 */
|
||||
[ 5] = RCAR_GP_PIN(1, 5), /* A21 */
|
||||
[ 6] = RCAR_GP_PIN(1, 6), /* A22 */
|
||||
[ 7] = RCAR_GP_PIN(1, 7), /* A23 */
|
||||
[ 8] = RCAR_GP_PIN(1, 8), /* A24 */
|
||||
[ 9] = RCAR_GP_PIN(1, 9), /* A25 */
|
||||
[10] = RCAR_GP_PIN(1, 10), /* CS0# */
|
||||
[11] = RCAR_GP_PIN(1, 12), /* EX_CS0# */
|
||||
[12] = RCAR_GP_PIN(1, 14), /* EX_CS2# */
|
||||
[13] = RCAR_GP_PIN(1, 16), /* EX_CS4# */
|
||||
[14] = RCAR_GP_PIN(1, 18), /* BS# */
|
||||
[15] = RCAR_GP_PIN(1, 19), /* RD# */
|
||||
[16] = RCAR_GP_PIN(1, 20), /* RD/WR# */
|
||||
[17] = RCAR_GP_PIN(1, 21), /* WE0# */
|
||||
[18] = RCAR_GP_PIN(1, 22), /* WE1# */
|
||||
[19] = RCAR_GP_PIN(1, 23), /* EX_WAIT0 */
|
||||
[20] = RCAR_GP_PIN(1, 24), /* DREQ0# */
|
||||
[21] = RCAR_GP_PIN(1, 25), /* DACK0 */
|
||||
[22] = PIN_TRST_N, /* TRST# */
|
||||
[23] = PIN_TCK, /* TCK */
|
||||
[24] = PIN_TMS, /* TMS */
|
||||
[25] = PIN_TDI, /* TDI */
|
||||
[26] = RCAR_GP_PIN(1, 11), /* CS1#/A26 */
|
||||
[27] = RCAR_GP_PIN(1, 13), /* EX_CS1# */
|
||||
[28] = RCAR_GP_PIN(1, 15), /* EX_CS3# */
|
||||
[29] = RCAR_GP_PIN(1, 17), /* EX_CS5# */
|
||||
[30] = SH_PFC_PIN_NONE,
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("N/A", 0, "PUPR1", 0xe6060104) {
|
||||
/* PUPR1 pull-down pins */
|
||||
[ 0] = SH_PFC_PIN_NONE,
|
||||
[ 1] = SH_PFC_PIN_NONE,
|
||||
[ 2] = SH_PFC_PIN_NONE,
|
||||
[ 3] = SH_PFC_PIN_NONE,
|
||||
[ 4] = SH_PFC_PIN_NONE,
|
||||
[ 5] = SH_PFC_PIN_NONE,
|
||||
[ 6] = SH_PFC_PIN_NONE,
|
||||
[ 7] = SH_PFC_PIN_NONE,
|
||||
[ 8] = SH_PFC_PIN_NONE,
|
||||
[ 9] = SH_PFC_PIN_NONE,
|
||||
[10] = SH_PFC_PIN_NONE,
|
||||
[11] = SH_PFC_PIN_NONE,
|
||||
[12] = SH_PFC_PIN_NONE,
|
||||
[13] = SH_PFC_PIN_NONE,
|
||||
[14] = SH_PFC_PIN_NONE,
|
||||
[15] = SH_PFC_PIN_NONE,
|
||||
[16] = SH_PFC_PIN_NONE,
|
||||
[17] = SH_PFC_PIN_NONE,
|
||||
[18] = SH_PFC_PIN_NONE,
|
||||
[19] = SH_PFC_PIN_NONE,
|
||||
[20] = SH_PFC_PIN_NONE,
|
||||
[21] = SH_PFC_PIN_NONE,
|
||||
[22] = SH_PFC_PIN_NONE,
|
||||
[23] = SH_PFC_PIN_NONE,
|
||||
[24] = SH_PFC_PIN_NONE,
|
||||
[25] = SH_PFC_PIN_NONE,
|
||||
[26] = SH_PFC_PIN_NONE,
|
||||
[27] = SH_PFC_PIN_NONE,
|
||||
[28] = SH_PFC_PIN_NONE,
|
||||
[29] = SH_PFC_PIN_NONE,
|
||||
[30] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(2, 0), /* DU0_DR0 */
|
||||
[ 1] = RCAR_GP_PIN(2, 1), /* DU0_DR1 */
|
||||
[ 2] = RCAR_GP_PIN(2, 2), /* DU0_DR2 */
|
||||
[ 3] = RCAR_GP_PIN(2, 3), /* DU0_DR3 */
|
||||
[ 4] = RCAR_GP_PIN(2, 4), /* DU0_DR4 */
|
||||
[ 5] = RCAR_GP_PIN(2, 5), /* DU0_DR5 */
|
||||
[ 6] = RCAR_GP_PIN(2, 6), /* DU0_DR6 */
|
||||
[ 7] = RCAR_GP_PIN(2, 7), /* DU0_DR7 */
|
||||
[ 8] = RCAR_GP_PIN(2, 8), /* DU0_DG0 */
|
||||
[ 9] = RCAR_GP_PIN(2, 9), /* DU0_DG1 */
|
||||
[10] = RCAR_GP_PIN(2, 10), /* DU0_DG2 */
|
||||
[11] = RCAR_GP_PIN(2, 11), /* DU0_DG3 */
|
||||
[12] = RCAR_GP_PIN(2, 12), /* DU0_DG4 */
|
||||
[13] = RCAR_GP_PIN(2, 13), /* DU0_DG5 */
|
||||
[14] = RCAR_GP_PIN(2, 14), /* DU0_DG6 */
|
||||
[15] = RCAR_GP_PIN(2, 15), /* DU0_DG7 */
|
||||
[16] = RCAR_GP_PIN(2, 16), /* DU0_DB0 */
|
||||
[17] = RCAR_GP_PIN(2, 17), /* DU0_DB1 */
|
||||
[18] = RCAR_GP_PIN(2, 18), /* DU0_DB2 */
|
||||
[19] = RCAR_GP_PIN(2, 19), /* DU0_DB3 */
|
||||
[20] = RCAR_GP_PIN(2, 20), /* DU0_DB4 */
|
||||
[21] = RCAR_GP_PIN(2, 21), /* DU0_DB5 */
|
||||
[22] = RCAR_GP_PIN(2, 22), /* DU0_DB6 */
|
||||
[23] = RCAR_GP_PIN(2, 23), /* DU0_DB7 */
|
||||
[24] = RCAR_GP_PIN(2, 24), /* DU0_DOTCLKIN */
|
||||
[25] = RCAR_GP_PIN(2, 25), /* DU0_DOTCLKOUT0 */
|
||||
[26] = RCAR_GP_PIN(2, 26), /* DU0_DOTCLKOUT1 */
|
||||
[27] = RCAR_GP_PIN(2, 27), /* DU0_EXHSYNC/DU0_HSYNC */
|
||||
[28] = RCAR_GP_PIN(2, 28), /* DU0_EXVSYNC/DU0_VSYNC */
|
||||
[29] = RCAR_GP_PIN(2, 29), /* DU0_EXODDF/DU0_ODDF_DISP_CDE */
|
||||
[30] = RCAR_GP_PIN(2, 30), /* DU0_DISP */
|
||||
[31] = RCAR_GP_PIN(2, 31), /* DU0_CDE */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(3, 2), /* VI0_DATA1_VI0_B1 */
|
||||
[ 1] = RCAR_GP_PIN(3, 3), /* VI0_DATA2_VI0_B2 */
|
||||
[ 2] = RCAR_GP_PIN(3, 4), /* VI0_DATA3_VI0_B3 */
|
||||
[ 3] = RCAR_GP_PIN(3, 5), /* VI0_DATA4_VI0_B4 */
|
||||
[ 4] = RCAR_GP_PIN(3, 6), /* VI0_DATA5_VI0_B5 */
|
||||
[ 5] = RCAR_GP_PIN(3, 7), /* VI0_DATA6_VI0_B6 */
|
||||
[ 6] = RCAR_GP_PIN(3, 8), /* VI0_DATA7_VI0_B7 */
|
||||
[ 7] = RCAR_GP_PIN(3, 9), /* VI0_CLKENB */
|
||||
[ 8] = RCAR_GP_PIN(3, 10), /* VI0_FIELD */
|
||||
[ 9] = RCAR_GP_PIN(3, 11), /* VI0_HSYNC# */
|
||||
[10] = RCAR_GP_PIN(3, 12), /* VI0_VSYNC# */
|
||||
[11] = RCAR_GP_PIN(3, 13), /* ETH_MDIO */
|
||||
[12] = RCAR_GP_PIN(3, 14), /* ETH_CRS_DV */
|
||||
[13] = RCAR_GP_PIN(3, 15), /* ETH_RX_ER */
|
||||
[14] = RCAR_GP_PIN(3, 16), /* ETH_RXD0 */
|
||||
[15] = RCAR_GP_PIN(3, 17), /* ETH_RXD1 */
|
||||
[16] = RCAR_GP_PIN(3, 18), /* ETH_LINK */
|
||||
[17] = RCAR_GP_PIN(3, 19), /* ETH_REF_CLK */
|
||||
[18] = RCAR_GP_PIN(3, 20), /* ETH_TXD1 */
|
||||
[19] = RCAR_GP_PIN(3, 21), /* ETH_TX_EN */
|
||||
[20] = RCAR_GP_PIN(3, 22), /* ETH_MAGIC */
|
||||
[21] = RCAR_GP_PIN(3, 23), /* ETH_TXD0 */
|
||||
[22] = RCAR_GP_PIN(3, 24), /* ETH_MDC */
|
||||
[23] = RCAR_GP_PIN(3, 25), /* HSCIF0_HRX */
|
||||
[24] = RCAR_GP_PIN(3, 26), /* HSCIF0_HTX */
|
||||
[25] = RCAR_GP_PIN(3, 27), /* HSCIF0_HCTS# */
|
||||
[26] = RCAR_GP_PIN(3, 28), /* HSCIF0_HRTS# */
|
||||
[27] = RCAR_GP_PIN(3, 29), /* HSCIF0_HSCK */
|
||||
[28] = RCAR_GP_PIN(3, 30), /* I2C0_SCL */
|
||||
[29] = RCAR_GP_PIN(3, 31), /* I2C0_SDA */
|
||||
[30] = RCAR_GP_PIN(4, 0), /* I2C1_SCL */
|
||||
[31] = RCAR_GP_PIN(4, 1), /* I2C1_SDA */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(4, 2), /* MSIOF0_RXD */
|
||||
[ 1] = RCAR_GP_PIN(4, 3), /* MSIOF0_TXD */
|
||||
[ 2] = RCAR_GP_PIN(4, 4), /* MSIOF0_SCK */
|
||||
[ 3] = RCAR_GP_PIN(4, 5), /* MSIOF0_SYNC */
|
||||
[ 4] = RCAR_GP_PIN(4, 6), /* MSIOF0_SS1 */
|
||||
[ 5] = RCAR_GP_PIN(4, 7), /* MSIOF0_SS2 */
|
||||
[ 6] = RCAR_GP_PIN(4, 8), /* HSCIF1_HRX */
|
||||
[ 7] = RCAR_GP_PIN(4, 9), /* HSCIF1_HTX */
|
||||
[ 8] = RCAR_GP_PIN(4, 10), /* HSCIF1_HSCK */
|
||||
[ 9] = RCAR_GP_PIN(4, 11), /* HSCIF1_HCTS# */
|
||||
[10] = RCAR_GP_PIN(4, 12), /* HSCIF1_HRTS# */
|
||||
[11] = RCAR_GP_PIN(4, 13), /* SCIF1_SCK */
|
||||
[12] = RCAR_GP_PIN(4, 14), /* SCIF1_RXD */
|
||||
[13] = RCAR_GP_PIN(4, 15), /* SCIF1_TXD */
|
||||
[14] = RCAR_GP_PIN(4, 16), /* SCIF2_RXD */
|
||||
[15] = RCAR_GP_PIN(4, 17), /* SCIF2_TXD */
|
||||
[16] = RCAR_GP_PIN(4, 18), /* SCIF2_SCK */
|
||||
[17] = RCAR_GP_PIN(4, 19), /* SCIF3_SCK */
|
||||
[18] = RCAR_GP_PIN(4, 20), /* SCIF3_RXD */
|
||||
[19] = RCAR_GP_PIN(4, 21), /* SCIF3_TXD */
|
||||
[20] = RCAR_GP_PIN(4, 22), /* I2C2_SCL */
|
||||
[21] = RCAR_GP_PIN(4, 23), /* I2C2_SDA */
|
||||
[22] = RCAR_GP_PIN(4, 24), /* SSI_SCK5 */
|
||||
[23] = RCAR_GP_PIN(4, 25), /* SSI_WS5 */
|
||||
[24] = RCAR_GP_PIN(4, 26), /* SSI_SDATA5 */
|
||||
[25] = RCAR_GP_PIN(4, 27), /* SSI_SCK6 */
|
||||
[26] = RCAR_GP_PIN(4, 28), /* SSI_WS6 */
|
||||
[27] = RCAR_GP_PIN(4, 29), /* SSI_SDATA6 */
|
||||
[28] = RCAR_GP_PIN(4, 30), /* SSI_SCK78 */
|
||||
[29] = RCAR_GP_PIN(4, 31), /* SSI_WS78 */
|
||||
[30] = RCAR_GP_PIN(5, 0), /* SSI_SDATA7 */
|
||||
[31] = RCAR_GP_PIN(5, 1), /* SSI_SCK0129 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(5, 2), /* SSI_WS0129 */
|
||||
[ 1] = RCAR_GP_PIN(5, 3), /* SSI_SDATA0 */
|
||||
[ 2] = RCAR_GP_PIN(5, 4), /* SSI_SCK34 */
|
||||
[ 3] = RCAR_GP_PIN(5, 5), /* SSI_WS34 */
|
||||
[ 4] = RCAR_GP_PIN(5, 6), /* SSI_SDATA3 */
|
||||
[ 5] = SH_PFC_PIN_NONE,
|
||||
[ 6] = SH_PFC_PIN_NONE,
|
||||
[ 7] = SH_PFC_PIN_NONE,
|
||||
[ 8] = RCAR_GP_PIN(5, 10), /* SSI_SDATA8 */
|
||||
[ 9] = RCAR_GP_PIN(5, 11), /* SSI_SCK1 */
|
||||
[10] = RCAR_GP_PIN(5, 12), /* SSI_WS1 */
|
||||
[11] = RCAR_GP_PIN(5, 13), /* SSI_SDATA1 */
|
||||
[12] = RCAR_GP_PIN(5, 14), /* SSI_SCK2 */
|
||||
[13] = RCAR_GP_PIN(5, 15), /* SSI_WS2 */
|
||||
[14] = RCAR_GP_PIN(5, 16), /* SSI_SDATA2 */
|
||||
[15] = RCAR_GP_PIN(5, 17), /* SSI_SCK9 */
|
||||
[16] = RCAR_GP_PIN(5, 18), /* SSI_WS9 */
|
||||
[17] = RCAR_GP_PIN(5, 19), /* SSI_SDATA9 */
|
||||
[18] = RCAR_GP_PIN(5, 20), /* AUDIO_CLKA */
|
||||
[19] = RCAR_GP_PIN(5, 21), /* AUDIO_CLKB */
|
||||
[20] = RCAR_GP_PIN(5, 22), /* AUDIO_CLKC */
|
||||
[21] = RCAR_GP_PIN(5, 23), /* AUDIO_CLKOUT */
|
||||
[22] = RCAR_GP_PIN(3, 0), /* VI0_CLK */
|
||||
[23] = RCAR_GP_PIN(3, 1), /* VI0_DATA0_VI0_B0 */
|
||||
[24] = SH_PFC_PIN_NONE,
|
||||
[25] = SH_PFC_PIN_NONE,
|
||||
[26] = SH_PFC_PIN_NONE,
|
||||
[27] = SH_PFC_PIN_NONE,
|
||||
[28] = SH_PFC_PIN_NONE,
|
||||
[29] = SH_PFC_PIN_NONE,
|
||||
[30] = SH_PFC_PIN_NONE,
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(6, 1), /* SD0_CMD */
|
||||
[ 1] = RCAR_GP_PIN(6, 2), /* SD0_DATA0 */
|
||||
[ 2] = RCAR_GP_PIN(6, 3), /* SD0_DATA1 */
|
||||
[ 3] = RCAR_GP_PIN(6, 4), /* SD0_DATA2 */
|
||||
[ 4] = RCAR_GP_PIN(6, 5), /* SD0_DATA3 */
|
||||
[ 5] = RCAR_GP_PIN(6, 6), /* SD0_CD */
|
||||
[ 6] = RCAR_GP_PIN(6, 7), /* SD0_WP */
|
||||
[ 7] = RCAR_GP_PIN(6, 9), /* SD1_CMD */
|
||||
[ 8] = RCAR_GP_PIN(6, 10), /* SD1_DATA0 */
|
||||
[ 9] = RCAR_GP_PIN(6, 11), /* SD1_DATA1 */
|
||||
[10] = RCAR_GP_PIN(6, 12), /* SD1_DATA2 */
|
||||
[11] = RCAR_GP_PIN(6, 13), /* SD1_DATA3 */
|
||||
[12] = RCAR_GP_PIN(6, 14), /* SD1_CD */
|
||||
[13] = RCAR_GP_PIN(6, 15), /* SD1_WP */
|
||||
[14] = SH_PFC_PIN_NONE,
|
||||
[15] = RCAR_GP_PIN(6, 17), /* MMC_CMD */
|
||||
[16] = RCAR_GP_PIN(6, 18), /* MMC_D0 */
|
||||
[17] = RCAR_GP_PIN(6, 19), /* MMC_D1 */
|
||||
[18] = RCAR_GP_PIN(6, 20), /* MMC_D2 */
|
||||
[19] = RCAR_GP_PIN(6, 21), /* MMC_D3 */
|
||||
[20] = RCAR_GP_PIN(6, 22), /* MMC_D4 */
|
||||
[21] = RCAR_GP_PIN(6, 23), /* MMC_D5 */
|
||||
[22] = RCAR_GP_PIN(6, 24), /* MMC_D6 */
|
||||
[23] = RCAR_GP_PIN(6, 25), /* MMC_D7 */
|
||||
[24] = SH_PFC_PIN_NONE,
|
||||
[25] = SH_PFC_PIN_NONE,
|
||||
[26] = SH_PFC_PIN_NONE,
|
||||
[27] = SH_PFC_PIN_NONE,
|
||||
[28] = SH_PFC_PIN_NONE,
|
||||
[29] = SH_PFC_PIN_NONE,
|
||||
[30] = SH_PFC_PIN_NONE,
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc)
|
||||
{
|
||||
/* Initialize TDSEL on old revisions */
|
||||
|
|
@ -5591,15 +5826,17 @@ static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
|
||||
static const struct sh_pfc_soc_operations r8a7794_pfc_ops = {
|
||||
.init = r8a7794_pinmux_soc_init,
|
||||
.pin_to_pocctrl = r8a7794_pin_to_pocctrl,
|
||||
.get_bias = rcar_pinmux_get_bias,
|
||||
.set_bias = rcar_pinmux_set_bias,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7745
|
||||
const struct sh_pfc_soc_info r8a7745_pinmux_info = {
|
||||
.name = "r8a77450_pfc",
|
||||
.ops = &r8a7794_pinmux_ops,
|
||||
.ops = &r8a7794_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
|
@ -5612,6 +5849,7 @@ const struct sh_pfc_soc_info r8a7745_pinmux_info = {
|
|||
.nr_functions = ARRAY_SIZE(pinmux_functions),
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.bias_regs = pinmux_bias_regs,
|
||||
|
||||
.pinmux_data = pinmux_data,
|
||||
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
|
||||
|
|
@ -5621,7 +5859,7 @@ const struct sh_pfc_soc_info r8a7745_pinmux_info = {
|
|||
#ifdef CONFIG_PINCTRL_PFC_R8A7794
|
||||
const struct sh_pfc_soc_info r8a7794_pinmux_info = {
|
||||
.name = "r8a77940_pfc",
|
||||
.ops = &r8a7794_pinmux_ops,
|
||||
.ops = &r8a7794_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
|
@ -5634,6 +5872,7 @@ const struct sh_pfc_soc_info r8a7794_pinmux_info = {
|
|||
.nr_functions = ARRAY_SIZE(pinmux_functions),
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.bias_regs = pinmux_bias_regs,
|
||||
|
||||
.pinmux_data = pinmux_data,
|
||||
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
|
||||
|
|
|
|||
|
|
@ -243,7 +243,7 @@
|
|||
#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
|
||||
#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
|
||||
#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
|
||||
#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
|
||||
#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
|
||||
|
||||
/* GPSR7 */
|
||||
#define GPSR7_3 FM(GP7_03)
|
||||
|
|
@ -670,7 +670,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
|
||||
PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
|
||||
PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
|
||||
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
|
||||
|
|
@ -1827,7 +1827,7 @@ static const unsigned int canfd1_data_mux[] = {
|
|||
CANFD1_TX_MARK, CANFD1_RX_MARK,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7795
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77951
|
||||
/* - DRIF0 --------------------------------------------------------------- */
|
||||
static const unsigned int drif0_ctrl_a_pins[] = {
|
||||
/* CLK, SYNC */
|
||||
|
|
@ -2042,7 +2042,7 @@ static const unsigned int drif3_data1_b_pins[] = {
|
|||
static const unsigned int drif3_data1_b_mux[] = {
|
||||
RIF3_D1_B_MARK,
|
||||
};
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A7795 */
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
|
||||
|
||||
/* - DU --------------------------------------------------------------------- */
|
||||
static const unsigned int du_rgb666_pins[] = {
|
||||
|
|
@ -2455,6 +2455,16 @@ static const unsigned int intc_ex_irq5_mux[] = {
|
|||
IRQ5_MARK,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77951
|
||||
/* - MLB+ ------------------------------------------------------------------- */
|
||||
static const unsigned int mlb_3pin_pins[] = {
|
||||
RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
|
||||
};
|
||||
static const unsigned int mlb_3pin_mux[] = {
|
||||
MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
|
||||
};
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
|
||||
|
||||
/* - MSIOF0 ----------------------------------------------------------------- */
|
||||
static const unsigned int msiof0_clk_pins[] = {
|
||||
/* SCK */
|
||||
|
|
@ -3260,20 +3270,13 @@ static const unsigned int qspi0_ctrl_pins[] = {
|
|||
static const unsigned int qspi0_ctrl_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data2_pins[] = {
|
||||
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
|
||||
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
|
||||
};
|
||||
static const unsigned int qspi0_data2_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data4_pins[] = {
|
||||
static const unsigned int qspi0_data_pins[] = {
|
||||
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
|
||||
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
|
||||
/* QSPI0_IO2, QSPI0_IO3 */
|
||||
PIN_QSPI0_IO2, PIN_QSPI0_IO3,
|
||||
};
|
||||
static const unsigned int qspi0_data4_mux[] = {
|
||||
static const unsigned int qspi0_data_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
|
||||
};
|
||||
|
|
@ -3285,20 +3288,13 @@ static const unsigned int qspi1_ctrl_pins[] = {
|
|||
static const unsigned int qspi1_ctrl_mux[] = {
|
||||
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data2_pins[] = {
|
||||
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
|
||||
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
|
||||
};
|
||||
static const unsigned int qspi1_data2_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data4_pins[] = {
|
||||
static const unsigned int qspi1_data_pins[] = {
|
||||
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
|
||||
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
|
||||
/* QSPI1_IO2, QSPI1_IO3 */
|
||||
PIN_QSPI1_IO2, PIN_QSPI1_IO3,
|
||||
};
|
||||
static const unsigned int qspi1_data4_mux[] = {
|
||||
static const unsigned int qspi1_data_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
|
||||
};
|
||||
|
|
@ -3533,19 +3529,12 @@ static const unsigned int scif_clk_b_mux[] = {
|
|||
};
|
||||
|
||||
/* - SDHI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi0_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(3, 2),
|
||||
};
|
||||
static const unsigned int sdhi0_data1_mux[] = {
|
||||
SD0_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi0_data4_pins[] = {
|
||||
static const unsigned int sdhi0_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
};
|
||||
static const unsigned int sdhi0_data4_mux[] = {
|
||||
static const unsigned int sdhi0_data_mux[] = {
|
||||
SD0_DAT0_MARK, SD0_DAT1_MARK,
|
||||
SD0_DAT2_MARK, SD0_DAT3_MARK,
|
||||
};
|
||||
|
|
@ -3571,19 +3560,12 @@ static const unsigned int sdhi0_wp_mux[] = {
|
|||
SD0_WP_MARK,
|
||||
};
|
||||
/* - SDHI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi1_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(3, 8),
|
||||
};
|
||||
static const unsigned int sdhi1_data1_mux[] = {
|
||||
SD1_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi1_data4_pins[] = {
|
||||
static const unsigned int sdhi1_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
};
|
||||
static const unsigned int sdhi1_data4_mux[] = {
|
||||
static const unsigned int sdhi1_data_mux[] = {
|
||||
SD1_DAT0_MARK, SD1_DAT1_MARK,
|
||||
SD1_DAT2_MARK, SD1_DAT3_MARK,
|
||||
};
|
||||
|
|
@ -3609,30 +3591,14 @@ static const unsigned int sdhi1_wp_mux[] = {
|
|||
SD1_WP_MARK,
|
||||
};
|
||||
/* - SDHI2 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi2_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(4, 2),
|
||||
};
|
||||
static const unsigned int sdhi2_data1_mux[] = {
|
||||
SD2_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
|
||||
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
|
||||
};
|
||||
static const unsigned int sdhi2_data4_mux[] = {
|
||||
SD2_DAT0_MARK, SD2_DAT1_MARK,
|
||||
SD2_DAT2_MARK, SD2_DAT3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_data8_pins[] = {
|
||||
static const unsigned int sdhi2_data_pins[] = {
|
||||
/* D[0:7] */
|
||||
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
|
||||
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
};
|
||||
static const unsigned int sdhi2_data8_mux[] = {
|
||||
static const unsigned int sdhi2_data_mux[] = {
|
||||
SD2_DAT0_MARK, SD2_DAT1_MARK,
|
||||
SD2_DAT2_MARK, SD2_DAT3_MARK,
|
||||
SD2_DAT4_MARK, SD2_DAT5_MARK,
|
||||
|
|
@ -3681,30 +3647,14 @@ static const unsigned int sdhi2_ds_mux[] = {
|
|||
SD2_DS_MARK,
|
||||
};
|
||||
/* - SDHI3 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi3_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(4, 9),
|
||||
};
|
||||
static const unsigned int sdhi3_data1_mux[] = {
|
||||
SD3_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi3_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
|
||||
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
|
||||
};
|
||||
static const unsigned int sdhi3_data4_mux[] = {
|
||||
SD3_DAT0_MARK, SD3_DAT1_MARK,
|
||||
SD3_DAT2_MARK, SD3_DAT3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi3_data8_pins[] = {
|
||||
static const unsigned int sdhi3_data_pins[] = {
|
||||
/* D[0:7] */
|
||||
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
|
||||
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
|
||||
RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
|
||||
RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
|
||||
};
|
||||
static const unsigned int sdhi3_data8_mux[] = {
|
||||
static const unsigned int sdhi3_data_mux[] = {
|
||||
SD3_DAT0_MARK, SD3_DAT1_MARK,
|
||||
SD3_DAT2_MARK, SD3_DAT3_MARK,
|
||||
SD3_DAT4_MARK, SD3_DAT5_MARK,
|
||||
|
|
@ -4063,69 +4013,61 @@ static const unsigned int vin4_data18_b_mux[] = {
|
|||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
static const union vin_data vin4_data_a_pins = {
|
||||
.data24 = {
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
},
|
||||
static const unsigned int vin4_data_a_pins[] = {
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
};
|
||||
static const union vin_data vin4_data_a_mux = {
|
||||
.data24 = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
},
|
||||
static const unsigned int vin4_data_a_mux[] = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
static const union vin_data vin4_data_b_pins = {
|
||||
.data24 = {
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
},
|
||||
static const unsigned int vin4_data_b_pins[] = {
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
};
|
||||
static const union vin_data vin4_data_b_mux = {
|
||||
.data24 = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
},
|
||||
static const unsigned int vin4_data_b_mux[] = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
static const unsigned int vin4_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
|
|
@ -4157,29 +4099,25 @@ static const unsigned int vin4_clk_mux[] = {
|
|||
};
|
||||
|
||||
/* - VIN5 ------------------------------------------------------------------- */
|
||||
static const union vin_data16 vin5_data_pins = {
|
||||
.data16 = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
},
|
||||
static const unsigned int vin5_data_pins[] = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
};
|
||||
static const union vin_data16 vin5_data_mux = {
|
||||
.data16 = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
VI5_DATA8_MARK, VI5_DATA9_MARK,
|
||||
VI5_DATA10_MARK, VI5_DATA11_MARK,
|
||||
VI5_DATA12_MARK, VI5_DATA13_MARK,
|
||||
VI5_DATA14_MARK, VI5_DATA15_MARK,
|
||||
},
|
||||
static const unsigned int vin5_data_mux[] = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
VI5_DATA8_MARK, VI5_DATA9_MARK,
|
||||
VI5_DATA10_MARK, VI5_DATA11_MARK,
|
||||
VI5_DATA12_MARK, VI5_DATA13_MARK,
|
||||
VI5_DATA14_MARK, VI5_DATA15_MARK,
|
||||
};
|
||||
static const unsigned int vin5_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
|
|
@ -4211,9 +4149,9 @@ static const unsigned int vin5_clk_mux[] = {
|
|||
};
|
||||
|
||||
static const struct {
|
||||
struct sh_pfc_pin_group common[326];
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7795
|
||||
struct sh_pfc_pin_group automotive[30];
|
||||
struct sh_pfc_pin_group common[328];
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77951
|
||||
struct sh_pfc_pin_group automotive[31];
|
||||
#endif
|
||||
} pinmux_groups = {
|
||||
.common = {
|
||||
|
|
@ -4417,11 +4355,11 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(pwm6_a),
|
||||
SH_PFC_PIN_GROUP(pwm6_b),
|
||||
SH_PFC_PIN_GROUP(qspi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi0_data2),
|
||||
SH_PFC_PIN_GROUP(qspi0_data4),
|
||||
BUS_DATA_PIN_GROUP(qspi0_data, 2),
|
||||
BUS_DATA_PIN_GROUP(qspi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(qspi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi1_data2),
|
||||
SH_PFC_PIN_GROUP(qspi1_data4),
|
||||
BUS_DATA_PIN_GROUP(qspi1_data, 2),
|
||||
BUS_DATA_PIN_GROUP(qspi1_data, 4),
|
||||
SH_PFC_PIN_GROUP(sata0_devslp_a),
|
||||
SH_PFC_PIN_GROUP(sata0_devslp_b),
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
|
|
@ -4453,28 +4391,28 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(scif5_clk_b),
|
||||
SH_PFC_PIN_GROUP(scif_clk_a),
|
||||
SH_PFC_PIN_GROUP(scif_clk_b),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi0_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi0_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi1_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi1_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data4),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data8),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 8),
|
||||
SH_PFC_PIN_GROUP(sdhi2_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi2_cd_a),
|
||||
SH_PFC_PIN_GROUP(sdhi2_wp_a),
|
||||
SH_PFC_PIN_GROUP(sdhi2_cd_b),
|
||||
SH_PFC_PIN_GROUP(sdhi2_wp_b),
|
||||
SH_PFC_PIN_GROUP(sdhi2_ds),
|
||||
SH_PFC_PIN_GROUP(sdhi3_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi3_data4),
|
||||
SH_PFC_PIN_GROUP(sdhi3_data8),
|
||||
BUS_DATA_PIN_GROUP(sdhi3_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi3_data, 4),
|
||||
BUS_DATA_PIN_GROUP(sdhi3_data, 8),
|
||||
SH_PFC_PIN_GROUP(sdhi3_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi3_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi3_wp),
|
||||
|
|
@ -4517,34 +4455,36 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(usb2),
|
||||
SH_PFC_PIN_GROUP(usb2_ch3),
|
||||
SH_PFC_PIN_GROUP(usb30),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
|
||||
SH_PFC_PIN_GROUP(vin4_data18_a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
|
||||
SH_PFC_PIN_GROUP(vin4_data18_b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
|
||||
SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
|
||||
SH_PFC_PIN_GROUP(vin4_sync),
|
||||
SH_PFC_PIN_GROUP(vin4_field),
|
||||
SH_PFC_PIN_GROUP(vin4_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin4_clk),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 8),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 16),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 16),
|
||||
SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
|
||||
SH_PFC_PIN_GROUP(vin5_sync),
|
||||
SH_PFC_PIN_GROUP(vin5_field),
|
||||
SH_PFC_PIN_GROUP(vin5_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin5_clk),
|
||||
},
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7795
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77951
|
||||
.automotive = {
|
||||
SH_PFC_PIN_GROUP(drif0_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(drif0_data0_a),
|
||||
|
|
@ -4576,8 +4516,9 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(drif3_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(drif3_data0_b),
|
||||
SH_PFC_PIN_GROUP(drif3_data1_b),
|
||||
SH_PFC_PIN_GROUP(mlb_3pin),
|
||||
}
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A7795 */
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
|
||||
};
|
||||
|
||||
static const char * const audio_clk_groups[] = {
|
||||
|
|
@ -4636,7 +4577,7 @@ static const char * const canfd1_groups[] = {
|
|||
"canfd1_data",
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7795
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77951
|
||||
static const char * const drif0_groups[] = {
|
||||
"drif0_ctrl_a",
|
||||
"drif0_data0_a",
|
||||
|
|
@ -4678,7 +4619,7 @@ static const char * const drif3_groups[] = {
|
|||
"drif3_data0_b",
|
||||
"drif3_data1_b",
|
||||
};
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A7795 */
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
|
||||
|
||||
static const char * const du_groups[] = {
|
||||
"du_rgb666",
|
||||
|
|
@ -4771,6 +4712,12 @@ static const char * const intc_ex_groups[] = {
|
|||
"intc_ex_irq5",
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77951
|
||||
static const char * const mlb_3pin_groups[] = {
|
||||
"mlb_3pin",
|
||||
};
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
|
||||
|
||||
static const char * const msiof0_groups[] = {
|
||||
"msiof0_clk",
|
||||
"msiof0_sync",
|
||||
|
|
@ -5098,6 +5045,7 @@ static const char * const vin4_groups[] = {
|
|||
"vin4_data18_b",
|
||||
"vin4_data20_b",
|
||||
"vin4_data24_b",
|
||||
"vin4_g8",
|
||||
"vin4_sync",
|
||||
"vin4_field",
|
||||
"vin4_clkenb",
|
||||
|
|
@ -5109,6 +5057,7 @@ static const char * const vin5_groups[] = {
|
|||
"vin5_data10",
|
||||
"vin5_data12",
|
||||
"vin5_data16",
|
||||
"vin5_high8",
|
||||
"vin5_sync",
|
||||
"vin5_field",
|
||||
"vin5_clkenb",
|
||||
|
|
@ -5117,8 +5066,8 @@ static const char * const vin5_groups[] = {
|
|||
|
||||
static const struct {
|
||||
struct sh_pfc_function common[55];
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7795
|
||||
struct sh_pfc_function automotive[4];
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77951
|
||||
struct sh_pfc_function automotive[5];
|
||||
#endif
|
||||
} pinmux_functions = {
|
||||
.common = {
|
||||
|
|
@ -5178,36 +5127,25 @@ static const struct {
|
|||
SH_PFC_FUNCTION(vin4),
|
||||
SH_PFC_FUNCTION(vin5),
|
||||
},
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7795
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77951
|
||||
.automotive = {
|
||||
SH_PFC_FUNCTION(drif0),
|
||||
SH_PFC_FUNCTION(drif1),
|
||||
SH_PFC_FUNCTION(drif2),
|
||||
SH_PFC_FUNCTION(drif3),
|
||||
SH_PFC_FUNCTION(mlb_3pin),
|
||||
}
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A7795 */
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
|
||||
};
|
||||
|
||||
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
#define F_(x, y) FN_##y
|
||||
#define FM(x) FN_##x
|
||||
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
|
||||
GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP0_31_16 RESERVED */
|
||||
GP_0_15_FN, GPSR0_15,
|
||||
GP_0_14_FN, GPSR0_14,
|
||||
GP_0_13_FN, GPSR0_13,
|
||||
|
|
@ -5259,24 +5197,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_1_1_FN, GPSR1_1,
|
||||
GP_1_0_FN, GPSR1_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
|
||||
GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP2_31_15 RESERVED */
|
||||
GP_2_14_FN, GPSR2_14,
|
||||
GP_2_13_FN, GPSR2_13,
|
||||
GP_2_12_FN, GPSR2_12,
|
||||
|
|
@ -5293,23 +5218,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_2_1_FN, GPSR2_1,
|
||||
GP_2_0_FN, GPSR2_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
|
||||
GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP3_31_16 RESERVED */
|
||||
GP_3_15_FN, GPSR3_15,
|
||||
GP_3_14_FN, GPSR3_14,
|
||||
GP_3_13_FN, GPSR3_13,
|
||||
|
|
@ -5327,21 +5240,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_3_1_FN, GPSR3_1,
|
||||
GP_3_0_FN, GPSR3_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
|
||||
GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP4_31_18 RESERVED */
|
||||
GP_4_17_FN, GPSR4_17,
|
||||
GP_4_16_FN, GPSR4_16,
|
||||
GP_4_15_FN, GPSR4_15,
|
||||
|
|
@ -5429,35 +5332,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_6_1_FN, GPSR6_1,
|
||||
GP_6_0_FN, GPSR6_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
|
||||
GROUP(-28, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP7_31_4 RESERVED */
|
||||
GP_7_3_FN, GPSR7_3,
|
||||
GP_7_2_FN, GPSR7_2,
|
||||
GP_7_1_FN, GPSR7_1,
|
||||
|
|
@ -5538,12 +5416,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
IP6_7_4
|
||||
IP6_3_0 ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
|
||||
{ PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
|
||||
GROUP(4, 4, 4, 4, -4, 4, 4, 4),
|
||||
GROUP(
|
||||
IP7_31_28
|
||||
IP7_27_24
|
||||
IP7_23_20
|
||||
IP7_19_16
|
||||
/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP7_15_12 RESERVED */
|
||||
IP7_11_8
|
||||
IP7_7_4
|
||||
IP7_3_0 ))
|
||||
|
|
@ -5648,13 +5528,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
IP17_7_4
|
||||
IP17_3_0 ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
|
||||
/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
|
||||
GROUP(-24, 4, 4),
|
||||
GROUP(
|
||||
/* IP18_31_8 RESERVED */
|
||||
IP18_7_4
|
||||
IP18_3_0 ))
|
||||
},
|
||||
|
|
@ -5664,8 +5541,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
#define F_(x, y) x,
|
||||
#define FM(x) FN_##x,
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
|
||||
GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
|
||||
1, 1, 1, 2, 2, 1, 2, 3),
|
||||
GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
|
||||
1, 1, 1, 2, 2, 1, 2, -3),
|
||||
GROUP(
|
||||
MOD_SEL0_31_30_29
|
||||
MOD_SEL0_28_27
|
||||
|
|
@ -5677,7 +5554,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL0_19
|
||||
MOD_SEL0_18_17
|
||||
MOD_SEL0_16
|
||||
0, 0, /* RESERVED 15 */
|
||||
/* RESERVED 15 */
|
||||
MOD_SEL0_14_13
|
||||
MOD_SEL0_12
|
||||
MOD_SEL0_11
|
||||
|
|
@ -5686,12 +5563,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL0_7_6
|
||||
MOD_SEL0_5
|
||||
MOD_SEL0_4_3
|
||||
/* RESERVED 2, 1, 0 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0 ))
|
||||
/* RESERVED 2, 1, 0 */ ))
|
||||
},
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
|
||||
GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
|
||||
1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
|
||||
1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
MOD_SEL1_31_30
|
||||
MOD_SEL1_29_28_27
|
||||
|
|
@ -5708,7 +5584,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL1_11
|
||||
MOD_SEL1_10
|
||||
MOD_SEL1_9
|
||||
0, 0, 0, 0, /* RESERVED 8, 7 */
|
||||
/* RESERVED 8, 7 */
|
||||
MOD_SEL1_6
|
||||
MOD_SEL1_5
|
||||
MOD_SEL1_4
|
||||
|
|
@ -5718,8 +5594,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL1_0 ))
|
||||
},
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
|
||||
GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
|
||||
1, 4, 4, 4, 3, 1),
|
||||
GROUP(1, 1, 1, 2, 1, 3, -1, 1, 1, 1, 1, 1,
|
||||
-16, 1),
|
||||
GROUP(
|
||||
MOD_SEL2_31
|
||||
MOD_SEL2_30
|
||||
|
|
@ -5728,25 +5604,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL2_26
|
||||
MOD_SEL2_25_24_23
|
||||
/* RESERVED 22 */
|
||||
0, 0,
|
||||
MOD_SEL2_21
|
||||
MOD_SEL2_20
|
||||
MOD_SEL2_19
|
||||
MOD_SEL2_18
|
||||
MOD_SEL2_17
|
||||
/* RESERVED 16 */
|
||||
0, 0,
|
||||
/* RESERVED 15, 14, 13, 12 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 11, 10, 9, 8 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 7, 6, 5, 4 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 3, 2, 1 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 16-1 */
|
||||
MOD_SEL2_0 ))
|
||||
},
|
||||
{ },
|
||||
|
|
@ -5874,7 +5737,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7795
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77951
|
||||
{ PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
|
||||
#endif
|
||||
{ PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
|
||||
|
|
@ -6014,8 +5877,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
|||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int r8a77951_pin_to_pocctrl(struct sh_pfc *pfc,
|
||||
unsigned int pin, u32 *pocctrl)
|
||||
static int r8a77951_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = -EINVAL;
|
||||
|
||||
|
|
@ -6272,57 +6134,16 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
|
||||
unsigned int pin)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
unsigned int bit;
|
||||
|
||||
reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
|
||||
if (!reg)
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
|
||||
if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
|
||||
return PIN_CONFIG_BIAS_PULL_UP;
|
||||
else
|
||||
return PIN_CONFIG_BIAS_PULL_DOWN;
|
||||
}
|
||||
|
||||
static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
u32 enable, updown;
|
||||
unsigned int bit;
|
||||
|
||||
reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
|
||||
if (!reg)
|
||||
return;
|
||||
|
||||
enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
|
||||
if (bias != PIN_CONFIG_BIAS_DISABLE)
|
||||
enable |= BIT(bit);
|
||||
|
||||
updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
|
||||
if (bias == PIN_CONFIG_BIAS_PULL_UP)
|
||||
updown |= BIT(bit);
|
||||
|
||||
sh_pfc_write(pfc, reg->pud, updown);
|
||||
sh_pfc_write(pfc, reg->puen, enable);
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = {
|
||||
static const struct sh_pfc_soc_operations r8a77951_pfc_ops = {
|
||||
.pin_to_pocctrl = r8a77951_pin_to_pocctrl,
|
||||
.get_bias = r8a7795_pinmux_get_bias,
|
||||
.set_bias = r8a7795_pinmux_set_bias,
|
||||
.get_bias = rcar_pinmux_get_bias,
|
||||
.set_bias = rcar_pinmux_set_bias,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A774E1
|
||||
const struct sh_pfc_soc_info r8a774e1_pinmux_info = {
|
||||
.name = "r8a774e1_pfc",
|
||||
.ops = &r8a77951_pinmux_ops,
|
||||
.ops = &r8a77951_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
|
@ -6344,10 +6165,10 @@ const struct sh_pfc_soc_info r8a774e1_pinmux_info = {
|
|||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7795
|
||||
const struct sh_pfc_soc_info r8a7795_pinmux_info = {
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77951
|
||||
const struct sh_pfc_soc_info r8a77951_pinmux_info = {
|
||||
.name = "r8a77951_pfc",
|
||||
.ops = &r8a77951_pinmux_ops,
|
||||
.ops = &r8a77951_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
|
|
|||
|
|
@ -70,6 +70,7 @@
|
|||
PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(PRESET_N, "PRESET#", fn, SH_PFC_PIN_CFG_PULL_DOWN),\
|
||||
PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
|
||||
|
|
@ -1551,7 +1552,7 @@ static const u16 pinmux_data[] = {
|
|||
* core will do the right thing and skip trying to mux the pin
|
||||
* while still applying configuration to it.
|
||||
*/
|
||||
#define FM(x) PINMUX_DATA(x##_MARK, 0),
|
||||
#define FM(x) PINMUX_DATA(x##_MARK, 0),
|
||||
PINMUX_STATIC
|
||||
#undef FM
|
||||
};
|
||||
|
|
@ -1832,7 +1833,7 @@ static const unsigned int canfd1_data_mux[] = {
|
|||
CANFD1_TX_MARK, CANFD1_RX_MARK,
|
||||
};
|
||||
|
||||
#if defined(CONFIG_PINCTRL_PFC_R8A7796)
|
||||
#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
|
||||
/* - DRIF0 --------------------------------------------------------------- */
|
||||
static const unsigned int drif0_ctrl_a_pins[] = {
|
||||
/* CLK, SYNC */
|
||||
|
|
@ -2047,7 +2048,7 @@ static const unsigned int drif3_data1_b_pins[] = {
|
|||
static const unsigned int drif3_data1_b_mux[] = {
|
||||
RIF3_D1_B_MARK,
|
||||
};
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
|
||||
|
||||
/* - DU --------------------------------------------------------------------- */
|
||||
static const unsigned int du_rgb666_pins[] = {
|
||||
|
|
@ -2460,6 +2461,16 @@ static const unsigned int intc_ex_irq5_mux[] = {
|
|||
IRQ5_MARK,
|
||||
};
|
||||
|
||||
#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
|
||||
/* - MLB+ ------------------------------------------------------------------- */
|
||||
static const unsigned int mlb_3pin_pins[] = {
|
||||
RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
|
||||
};
|
||||
static const unsigned int mlb_3pin_mux[] = {
|
||||
MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
|
||||
};
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
|
||||
|
||||
/* - MSIOF0 ----------------------------------------------------------------- */
|
||||
static const unsigned int msiof0_clk_pins[] = {
|
||||
/* SCK */
|
||||
|
|
@ -3266,20 +3277,13 @@ static const unsigned int qspi0_ctrl_pins[] = {
|
|||
static const unsigned int qspi0_ctrl_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data2_pins[] = {
|
||||
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
|
||||
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
|
||||
};
|
||||
static const unsigned int qspi0_data2_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data4_pins[] = {
|
||||
static const unsigned int qspi0_data_pins[] = {
|
||||
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
|
||||
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
|
||||
/* QSPI0_IO2, QSPI0_IO3 */
|
||||
PIN_QSPI0_IO2, PIN_QSPI0_IO3,
|
||||
};
|
||||
static const unsigned int qspi0_data4_mux[] = {
|
||||
static const unsigned int qspi0_data_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
|
||||
};
|
||||
|
|
@ -3291,20 +3295,13 @@ static const unsigned int qspi1_ctrl_pins[] = {
|
|||
static const unsigned int qspi1_ctrl_mux[] = {
|
||||
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data2_pins[] = {
|
||||
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
|
||||
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
|
||||
};
|
||||
static const unsigned int qspi1_data2_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data4_pins[] = {
|
||||
static const unsigned int qspi1_data_pins[] = {
|
||||
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
|
||||
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
|
||||
/* QSPI1_IO2, QSPI1_IO3 */
|
||||
PIN_QSPI1_IO2, PIN_QSPI1_IO3,
|
||||
};
|
||||
static const unsigned int qspi1_data4_mux[] = {
|
||||
static const unsigned int qspi1_data_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
|
||||
};
|
||||
|
|
@ -3524,19 +3521,12 @@ static const unsigned int scif_clk_b_mux[] = {
|
|||
};
|
||||
|
||||
/* - SDHI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi0_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(3, 2),
|
||||
};
|
||||
static const unsigned int sdhi0_data1_mux[] = {
|
||||
SD0_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi0_data4_pins[] = {
|
||||
static const unsigned int sdhi0_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
};
|
||||
static const unsigned int sdhi0_data4_mux[] = {
|
||||
static const unsigned int sdhi0_data_mux[] = {
|
||||
SD0_DAT0_MARK, SD0_DAT1_MARK,
|
||||
SD0_DAT2_MARK, SD0_DAT3_MARK,
|
||||
};
|
||||
|
|
@ -3562,19 +3552,12 @@ static const unsigned int sdhi0_wp_mux[] = {
|
|||
SD0_WP_MARK,
|
||||
};
|
||||
/* - SDHI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi1_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(3, 8),
|
||||
};
|
||||
static const unsigned int sdhi1_data1_mux[] = {
|
||||
SD1_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi1_data4_pins[] = {
|
||||
static const unsigned int sdhi1_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
};
|
||||
static const unsigned int sdhi1_data4_mux[] = {
|
||||
static const unsigned int sdhi1_data_mux[] = {
|
||||
SD1_DAT0_MARK, SD1_DAT1_MARK,
|
||||
SD1_DAT2_MARK, SD1_DAT3_MARK,
|
||||
};
|
||||
|
|
@ -3600,30 +3583,14 @@ static const unsigned int sdhi1_wp_mux[] = {
|
|||
SD1_WP_MARK,
|
||||
};
|
||||
/* - SDHI2 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi2_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(4, 2),
|
||||
};
|
||||
static const unsigned int sdhi2_data1_mux[] = {
|
||||
SD2_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
|
||||
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
|
||||
};
|
||||
static const unsigned int sdhi2_data4_mux[] = {
|
||||
SD2_DAT0_MARK, SD2_DAT1_MARK,
|
||||
SD2_DAT2_MARK, SD2_DAT3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi2_data8_pins[] = {
|
||||
static const unsigned int sdhi2_data_pins[] = {
|
||||
/* D[0:7] */
|
||||
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
|
||||
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
};
|
||||
static const unsigned int sdhi2_data8_mux[] = {
|
||||
static const unsigned int sdhi2_data_mux[] = {
|
||||
SD2_DAT0_MARK, SD2_DAT1_MARK,
|
||||
SD2_DAT2_MARK, SD2_DAT3_MARK,
|
||||
SD2_DAT4_MARK, SD2_DAT5_MARK,
|
||||
|
|
@ -3672,30 +3639,14 @@ static const unsigned int sdhi2_ds_mux[] = {
|
|||
SD2_DS_MARK,
|
||||
};
|
||||
/* - SDHI3 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi3_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(4, 9),
|
||||
};
|
||||
static const unsigned int sdhi3_data1_mux[] = {
|
||||
SD3_DAT0_MARK,
|
||||
};
|
||||
static const unsigned int sdhi3_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
|
||||
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
|
||||
};
|
||||
static const unsigned int sdhi3_data4_mux[] = {
|
||||
SD3_DAT0_MARK, SD3_DAT1_MARK,
|
||||
SD3_DAT2_MARK, SD3_DAT3_MARK,
|
||||
};
|
||||
static const unsigned int sdhi3_data8_pins[] = {
|
||||
static const unsigned int sdhi3_data_pins[] = {
|
||||
/* D[0:7] */
|
||||
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
|
||||
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
|
||||
RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
|
||||
RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
|
||||
};
|
||||
static const unsigned int sdhi3_data8_mux[] = {
|
||||
static const unsigned int sdhi3_data_mux[] = {
|
||||
SD3_DAT0_MARK, SD3_DAT1_MARK,
|
||||
SD3_DAT2_MARK, SD3_DAT3_MARK,
|
||||
SD3_DAT4_MARK, SD3_DAT5_MARK,
|
||||
|
|
@ -4038,69 +3989,61 @@ static const unsigned int vin4_data18_b_mux[] = {
|
|||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
static const union vin_data vin4_data_a_pins = {
|
||||
.data24 = {
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
},
|
||||
static const unsigned int vin4_data_a_pins[] = {
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
};
|
||||
static const union vin_data vin4_data_a_mux = {
|
||||
.data24 = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
},
|
||||
static const unsigned int vin4_data_a_mux[] = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
static const union vin_data vin4_data_b_pins = {
|
||||
.data24 = {
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
},
|
||||
static const unsigned int vin4_data_b_pins[] = {
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
};
|
||||
static const union vin_data vin4_data_b_mux = {
|
||||
.data24 = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
},
|
||||
static const unsigned int vin4_data_b_mux[] = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
static const unsigned int vin4_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
|
|
@ -4132,29 +4075,25 @@ static const unsigned int vin4_clk_mux[] = {
|
|||
};
|
||||
|
||||
/* - VIN5 ------------------------------------------------------------------- */
|
||||
static const union vin_data16 vin5_data_pins = {
|
||||
.data16 = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
},
|
||||
static const unsigned int vin5_data_pins[] = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
};
|
||||
static const union vin_data16 vin5_data_mux = {
|
||||
.data16 = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
VI5_DATA8_MARK, VI5_DATA9_MARK,
|
||||
VI5_DATA10_MARK, VI5_DATA11_MARK,
|
||||
VI5_DATA12_MARK, VI5_DATA13_MARK,
|
||||
VI5_DATA14_MARK, VI5_DATA15_MARK,
|
||||
},
|
||||
static const unsigned int vin5_data_mux[] = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
VI5_DATA8_MARK, VI5_DATA9_MARK,
|
||||
VI5_DATA10_MARK, VI5_DATA11_MARK,
|
||||
VI5_DATA12_MARK, VI5_DATA13_MARK,
|
||||
VI5_DATA14_MARK, VI5_DATA15_MARK,
|
||||
};
|
||||
static const unsigned int vin5_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
|
|
@ -4186,9 +4125,9 @@ static const unsigned int vin5_clk_mux[] = {
|
|||
};
|
||||
|
||||
static const struct {
|
||||
struct sh_pfc_pin_group common[322];
|
||||
#if defined(CONFIG_PINCTRL_PFC_R8A7796)
|
||||
struct sh_pfc_pin_group automotive[30];
|
||||
struct sh_pfc_pin_group common[324];
|
||||
#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
|
||||
struct sh_pfc_pin_group automotive[31];
|
||||
#endif
|
||||
} pinmux_groups = {
|
||||
.common = {
|
||||
|
|
@ -4212,7 +4151,7 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(avb_link),
|
||||
SH_PFC_PIN_GROUP(avb_magic),
|
||||
SH_PFC_PIN_GROUP(avb_phy_int),
|
||||
SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
|
||||
SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
|
||||
SH_PFC_PIN_GROUP(avb_mdio),
|
||||
SH_PFC_PIN_GROUP(avb_mii),
|
||||
SH_PFC_PIN_GROUP(avb_avtp_pps),
|
||||
|
|
@ -4392,11 +4331,11 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(pwm6_a),
|
||||
SH_PFC_PIN_GROUP(pwm6_b),
|
||||
SH_PFC_PIN_GROUP(qspi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi0_data2),
|
||||
SH_PFC_PIN_GROUP(qspi0_data4),
|
||||
BUS_DATA_PIN_GROUP(qspi0_data, 2),
|
||||
BUS_DATA_PIN_GROUP(qspi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(qspi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi1_data2),
|
||||
SH_PFC_PIN_GROUP(qspi1_data4),
|
||||
BUS_DATA_PIN_GROUP(qspi1_data, 2),
|
||||
BUS_DATA_PIN_GROUP(qspi1_data, 4),
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
SH_PFC_PIN_GROUP(scif0_clk),
|
||||
SH_PFC_PIN_GROUP(scif0_ctrl),
|
||||
|
|
@ -4426,28 +4365,28 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(scif5_clk_b),
|
||||
SH_PFC_PIN_GROUP(scif_clk_a),
|
||||
SH_PFC_PIN_GROUP(scif_clk_b),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi0_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi0_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi1_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi1_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data4),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data8),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 8),
|
||||
SH_PFC_PIN_GROUP(sdhi2_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi2_cd_a),
|
||||
SH_PFC_PIN_GROUP(sdhi2_wp_a),
|
||||
SH_PFC_PIN_GROUP(sdhi2_cd_b),
|
||||
SH_PFC_PIN_GROUP(sdhi2_wp_b),
|
||||
SH_PFC_PIN_GROUP(sdhi2_ds),
|
||||
SH_PFC_PIN_GROUP(sdhi3_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi3_data4),
|
||||
SH_PFC_PIN_GROUP(sdhi3_data8),
|
||||
BUS_DATA_PIN_GROUP(sdhi3_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi3_data, 4),
|
||||
BUS_DATA_PIN_GROUP(sdhi3_data, 8),
|
||||
SH_PFC_PIN_GROUP(sdhi3_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi3_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi3_wp),
|
||||
|
|
@ -4488,34 +4427,36 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(usb0),
|
||||
SH_PFC_PIN_GROUP(usb1),
|
||||
SH_PFC_PIN_GROUP(usb30),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
|
||||
SH_PFC_PIN_GROUP(vin4_data18_a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
|
||||
SH_PFC_PIN_GROUP(vin4_data18_b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
|
||||
SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
|
||||
SH_PFC_PIN_GROUP(vin4_sync),
|
||||
SH_PFC_PIN_GROUP(vin4_field),
|
||||
SH_PFC_PIN_GROUP(vin4_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin4_clk),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 8),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 16),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 16),
|
||||
SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
|
||||
SH_PFC_PIN_GROUP(vin5_sync),
|
||||
SH_PFC_PIN_GROUP(vin5_field),
|
||||
SH_PFC_PIN_GROUP(vin5_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin5_clk),
|
||||
},
|
||||
#if defined(CONFIG_PINCTRL_PFC_R8A7796)
|
||||
#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
|
||||
.automotive = {
|
||||
SH_PFC_PIN_GROUP(drif0_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(drif0_data0_a),
|
||||
|
|
@ -4547,8 +4488,9 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(drif3_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(drif3_data0_b),
|
||||
SH_PFC_PIN_GROUP(drif3_data1_b),
|
||||
SH_PFC_PIN_GROUP(mlb_3pin),
|
||||
}
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
|
||||
};
|
||||
|
||||
static const char * const audio_clk_groups[] = {
|
||||
|
|
@ -4607,7 +4549,7 @@ static const char * const canfd1_groups[] = {
|
|||
"canfd1_data",
|
||||
};
|
||||
|
||||
#if defined(CONFIG_PINCTRL_PFC_R8A7796)
|
||||
#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
|
||||
static const char * const drif0_groups[] = {
|
||||
"drif0_ctrl_a",
|
||||
"drif0_data0_a",
|
||||
|
|
@ -4649,7 +4591,7 @@ static const char * const drif3_groups[] = {
|
|||
"drif3_data0_b",
|
||||
"drif3_data1_b",
|
||||
};
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
|
||||
|
||||
static const char * const du_groups[] = {
|
||||
"du_rgb666",
|
||||
|
|
@ -4742,6 +4684,12 @@ static const char * const intc_ex_groups[] = {
|
|||
"intc_ex_irq5",
|
||||
};
|
||||
|
||||
#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
|
||||
static const char * const mlb_3pin_groups[] = {
|
||||
"mlb_3pin",
|
||||
};
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
|
||||
|
||||
static const char * const msiof0_groups[] = {
|
||||
"msiof0_clk",
|
||||
"msiof0_sync",
|
||||
|
|
@ -5056,6 +5004,7 @@ static const char * const vin4_groups[] = {
|
|||
"vin4_data18_b",
|
||||
"vin4_data20_b",
|
||||
"vin4_data24_b",
|
||||
"vin4_g8",
|
||||
"vin4_sync",
|
||||
"vin4_field",
|
||||
"vin4_clkenb",
|
||||
|
|
@ -5067,6 +5016,7 @@ static const char * const vin5_groups[] = {
|
|||
"vin5_data10",
|
||||
"vin5_data12",
|
||||
"vin5_data16",
|
||||
"vin5_high8",
|
||||
"vin5_sync",
|
||||
"vin5_field",
|
||||
"vin5_clkenb",
|
||||
|
|
@ -5075,8 +5025,8 @@ static const char * const vin5_groups[] = {
|
|||
|
||||
static const struct {
|
||||
struct sh_pfc_function common[52];
|
||||
#if defined(CONFIG_PINCTRL_PFC_R8A7796)
|
||||
struct sh_pfc_function automotive[4];
|
||||
#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
|
||||
struct sh_pfc_function automotive[5];
|
||||
#endif
|
||||
} pinmux_functions = {
|
||||
.common = {
|
||||
|
|
@ -5133,36 +5083,25 @@ static const struct {
|
|||
SH_PFC_FUNCTION(vin4),
|
||||
SH_PFC_FUNCTION(vin5),
|
||||
},
|
||||
#if defined(CONFIG_PINCTRL_PFC_R8A7796)
|
||||
#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
|
||||
.automotive = {
|
||||
SH_PFC_FUNCTION(drif0),
|
||||
SH_PFC_FUNCTION(drif1),
|
||||
SH_PFC_FUNCTION(drif2),
|
||||
SH_PFC_FUNCTION(drif3),
|
||||
SH_PFC_FUNCTION(mlb_3pin),
|
||||
}
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
|
||||
};
|
||||
|
||||
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
#define F_(x, y) FN_##y
|
||||
#define FM(x) FN_##x
|
||||
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
|
||||
GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP0_31_16 RESERVED */
|
||||
GP_0_15_FN, GPSR0_15,
|
||||
GP_0_14_FN, GPSR0_14,
|
||||
GP_0_13_FN, GPSR0_13,
|
||||
|
|
@ -5214,24 +5153,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_1_1_FN, GPSR1_1,
|
||||
GP_1_0_FN, GPSR1_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
|
||||
GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP2_31_15 RESERVED */
|
||||
GP_2_14_FN, GPSR2_14,
|
||||
GP_2_13_FN, GPSR2_13,
|
||||
GP_2_12_FN, GPSR2_12,
|
||||
|
|
@ -5248,23 +5174,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_2_1_FN, GPSR2_1,
|
||||
GP_2_0_FN, GPSR2_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
|
||||
GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP3_31_16 RESERVED */
|
||||
GP_3_15_FN, GPSR3_15,
|
||||
GP_3_14_FN, GPSR3_14,
|
||||
GP_3_13_FN, GPSR3_13,
|
||||
|
|
@ -5282,21 +5196,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_3_1_FN, GPSR3_1,
|
||||
GP_3_0_FN, GPSR3_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
|
||||
GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP4_31_18 RESERVED */
|
||||
GP_4_17_FN, GPSR4_17,
|
||||
GP_4_16_FN, GPSR4_16,
|
||||
GP_4_15_FN, GPSR4_15,
|
||||
|
|
@ -5384,35 +5288,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_6_1_FN, GPSR6_1,
|
||||
GP_6_0_FN, GPSR6_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
|
||||
GROUP(-28, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP7_31_4 RESERVED */
|
||||
GP_7_3_FN, GPSR7_3,
|
||||
GP_7_2_FN, GPSR7_2,
|
||||
GP_7_1_FN, GPSR7_1,
|
||||
|
|
@ -5493,12 +5372,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
IP6_7_4
|
||||
IP6_3_0 ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
|
||||
{ PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
|
||||
GROUP(4, 4, 4, 4, -4, 4, 4, 4),
|
||||
GROUP(
|
||||
IP7_31_28
|
||||
IP7_27_24
|
||||
IP7_23_20
|
||||
IP7_19_16
|
||||
/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP7_15_12 RESERVED */
|
||||
IP7_11_8
|
||||
IP7_7_4
|
||||
IP7_3_0 ))
|
||||
|
|
@ -5603,13 +5484,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
IP17_7_4
|
||||
IP17_3_0 ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
|
||||
/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
|
||||
GROUP(-24, 4, 4),
|
||||
GROUP(
|
||||
/* IP18_31_8 RESERVED */
|
||||
IP18_7_4
|
||||
IP18_3_0 ))
|
||||
},
|
||||
|
|
@ -5619,8 +5497,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
#define F_(x, y) x,
|
||||
#define FM(x) FN_##x,
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
|
||||
GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
|
||||
1, 1, 1, 2, 2, 1, 2, 3),
|
||||
GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
|
||||
1, 1, 1, 2, 2, 1, 2, -3),
|
||||
GROUP(
|
||||
MOD_SEL0_31_30_29
|
||||
MOD_SEL0_28_27
|
||||
|
|
@ -5632,7 +5510,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL0_19
|
||||
MOD_SEL0_18_17
|
||||
MOD_SEL0_16
|
||||
0, 0, /* RESERVED 15 */
|
||||
/* RESERVED 15 */
|
||||
MOD_SEL0_14_13
|
||||
MOD_SEL0_12
|
||||
MOD_SEL0_11
|
||||
|
|
@ -5641,12 +5519,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL0_7_6
|
||||
MOD_SEL0_5
|
||||
MOD_SEL0_4_3
|
||||
/* RESERVED 2, 1, 0 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0 ))
|
||||
/* RESERVED 2, 1, 0 */ ))
|
||||
},
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
|
||||
GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
|
||||
1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
|
||||
1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
MOD_SEL1_31_30
|
||||
MOD_SEL1_29_28_27
|
||||
|
|
@ -5663,7 +5540,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL1_11
|
||||
MOD_SEL1_10
|
||||
MOD_SEL1_9
|
||||
0, 0, 0, 0, /* RESERVED 8, 7 */
|
||||
/* RESERVED 8, 7 */
|
||||
MOD_SEL1_6
|
||||
MOD_SEL1_5
|
||||
MOD_SEL1_4
|
||||
|
|
@ -5674,7 +5551,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
},
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
|
||||
GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
|
||||
1, 4, 4, 4, 3, 1),
|
||||
-16, 1),
|
||||
GROUP(
|
||||
MOD_SEL2_31
|
||||
MOD_SEL2_30
|
||||
|
|
@ -5688,19 +5565,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL2_19
|
||||
MOD_SEL2_18
|
||||
MOD_SEL2_17
|
||||
/* RESERVED 16 */
|
||||
0, 0,
|
||||
/* RESERVED 15, 14, 13, 12 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 11, 10, 9, 8 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 7, 6, 5, 4 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 3, 2, 1 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 16-1 */
|
||||
MOD_SEL2_0 ))
|
||||
},
|
||||
{ },
|
||||
|
|
@ -5965,7 +5830,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
|||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
|
||||
static int r8a7796_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = -EINVAL;
|
||||
|
||||
|
|
@ -6193,7 +6058,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
|
||||
[ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
|
||||
[ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
|
||||
[ 7] = SH_PFC_PIN_NONE,
|
||||
[ 7] = PIN_PRESET_N, /* PRESET# */
|
||||
[ 8] = SH_PFC_PIN_NONE,
|
||||
[ 9] = SH_PFC_PIN_NONE,
|
||||
[10] = SH_PFC_PIN_NONE,
|
||||
|
|
@ -6222,57 +6087,16 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
|
||||
unsigned int pin)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
unsigned int bit;
|
||||
|
||||
reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
|
||||
if (!reg)
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
|
||||
if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
|
||||
return PIN_CONFIG_BIAS_PULL_UP;
|
||||
else
|
||||
return PIN_CONFIG_BIAS_PULL_DOWN;
|
||||
}
|
||||
|
||||
static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
u32 enable, updown;
|
||||
unsigned int bit;
|
||||
|
||||
reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
|
||||
if (!reg)
|
||||
return;
|
||||
|
||||
enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
|
||||
if (bias != PIN_CONFIG_BIAS_DISABLE)
|
||||
enable |= BIT(bit);
|
||||
|
||||
updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
|
||||
if (bias == PIN_CONFIG_BIAS_PULL_UP)
|
||||
updown |= BIT(bit);
|
||||
|
||||
sh_pfc_write(pfc, reg->pud, updown);
|
||||
sh_pfc_write(pfc, reg->puen, enable);
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
|
||||
static const struct sh_pfc_soc_operations r8a7796_pfc_ops = {
|
||||
.pin_to_pocctrl = r8a7796_pin_to_pocctrl,
|
||||
.get_bias = r8a7796_pinmux_get_bias,
|
||||
.set_bias = r8a7796_pinmux_set_bias,
|
||||
.get_bias = rcar_pinmux_get_bias,
|
||||
.set_bias = rcar_pinmux_set_bias,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A774A1
|
||||
const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
|
||||
.name = "r8a774a1_pfc",
|
||||
.ops = &r8a7796_pinmux_ops,
|
||||
.ops = &r8a7796_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
|
@ -6294,10 +6118,37 @@ const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
|
|||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7796
|
||||
const struct sh_pfc_soc_info r8a7796_pinmux_info = {
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77960
|
||||
const struct sh_pfc_soc_info r8a77960_pinmux_info = {
|
||||
.name = "r8a77960_pfc",
|
||||
.ops = &r8a7796_pinmux_ops,
|
||||
.ops = &r8a7796_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
||||
.pins = pinmux_pins,
|
||||
.nr_pins = ARRAY_SIZE(pinmux_pins),
|
||||
.groups = pinmux_groups.common,
|
||||
.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
|
||||
ARRAY_SIZE(pinmux_groups.automotive),
|
||||
.functions = pinmux_functions.common,
|
||||
.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
|
||||
ARRAY_SIZE(pinmux_functions.automotive),
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.drive_regs = pinmux_drive_regs,
|
||||
.bias_regs = pinmux_bias_regs,
|
||||
.ioctrl_regs = pinmux_ioctrl_regs,
|
||||
|
||||
.pinmux_data = pinmux_data,
|
||||
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77961
|
||||
const struct sh_pfc_soc_info r8a77961_pinmux_info = {
|
||||
.name = "r8a77961_pfc",
|
||||
.ops = &r8a7796_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
|
|
|||
|
|
@ -669,14 +669,14 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
|
||||
PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
|
||||
|
||||
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
|
||||
PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
|
||||
|
||||
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
|
||||
PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
|
||||
|
|
@ -730,16 +730,16 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
|
||||
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
|
||||
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
|
||||
PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
|
||||
PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
|
||||
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
|
||||
PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
|
||||
PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP1_31_28, A0),
|
||||
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
|
||||
|
|
@ -1174,13 +1174,13 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
|
||||
PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
|
||||
PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
|
||||
|
|
@ -1556,7 +1556,7 @@ static const u16 pinmux_data[] = {
|
|||
* core will do the right thing and skip trying to mux the pin
|
||||
* while still applying configuration to it.
|
||||
*/
|
||||
#define FM(x) PINMUX_DATA(x##_MARK, 0),
|
||||
#define FM(x) PINMUX_DATA(x##_MARK, 0),
|
||||
PINMUX_STATIC
|
||||
#undef FM
|
||||
};
|
||||
|
|
@ -2612,6 +2612,16 @@ static const unsigned int intc_ex_irq5_mux[] = {
|
|||
IRQ5_MARK,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77965
|
||||
/* - MLB+ ------------------------------------------------------------------- */
|
||||
static const unsigned int mlb_3pin_pins[] = {
|
||||
RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
|
||||
};
|
||||
static const unsigned int mlb_3pin_mux[] = {
|
||||
MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
|
||||
};
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
|
||||
|
||||
/* - MSIOF0 ----------------------------------------------------------------- */
|
||||
static const unsigned int msiof0_clk_pins[] = {
|
||||
/* SCK */
|
||||
|
|
@ -3417,20 +3427,13 @@ static const unsigned int qspi0_ctrl_pins[] = {
|
|||
static const unsigned int qspi0_ctrl_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data2_pins[] = {
|
||||
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
|
||||
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
|
||||
};
|
||||
static const unsigned int qspi0_data2_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data4_pins[] = {
|
||||
static const unsigned int qspi0_data_pins[] = {
|
||||
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
|
||||
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
|
||||
/* QSPI0_IO2, QSPI0_IO3 */
|
||||
PIN_QSPI0_IO2, PIN_QSPI0_IO3,
|
||||
};
|
||||
static const unsigned int qspi0_data4_mux[] = {
|
||||
static const unsigned int qspi0_data_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
|
||||
};
|
||||
|
|
@ -3442,20 +3445,13 @@ static const unsigned int qspi1_ctrl_pins[] = {
|
|||
static const unsigned int qspi1_ctrl_mux[] = {
|
||||
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data2_pins[] = {
|
||||
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
|
||||
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
|
||||
};
|
||||
static const unsigned int qspi1_data2_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data4_pins[] = {
|
||||
static const unsigned int qspi1_data_pins[] = {
|
||||
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
|
||||
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
|
||||
/* QSPI1_IO2, QSPI1_IO3 */
|
||||
PIN_QSPI1_IO2, PIN_QSPI1_IO3,
|
||||
};
|
||||
static const unsigned int qspi1_data4_mux[] = {
|
||||
static const unsigned int qspi1_data_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
|
||||
};
|
||||
|
|
@ -3691,22 +3687,13 @@ static const unsigned int scif_clk_b_mux[] = {
|
|||
};
|
||||
|
||||
/* - SDHI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi0_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(3, 2),
|
||||
};
|
||||
|
||||
static const unsigned int sdhi0_data1_mux[] = {
|
||||
SD0_DAT0_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int sdhi0_data4_pins[] = {
|
||||
static const unsigned int sdhi0_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
};
|
||||
|
||||
static const unsigned int sdhi0_data4_mux[] = {
|
||||
static const unsigned int sdhi0_data_mux[] = {
|
||||
SD0_DAT0_MARK, SD0_DAT1_MARK,
|
||||
SD0_DAT2_MARK, SD0_DAT3_MARK,
|
||||
};
|
||||
|
|
@ -3739,22 +3726,13 @@ static const unsigned int sdhi0_wp_mux[] = {
|
|||
};
|
||||
|
||||
/* - SDHI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi1_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(3, 8),
|
||||
};
|
||||
|
||||
static const unsigned int sdhi1_data1_mux[] = {
|
||||
SD1_DAT0_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int sdhi1_data4_pins[] = {
|
||||
static const unsigned int sdhi1_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
};
|
||||
|
||||
static const unsigned int sdhi1_data4_mux[] = {
|
||||
static const unsigned int sdhi1_data_mux[] = {
|
||||
SD1_DAT0_MARK, SD1_DAT1_MARK,
|
||||
SD1_DAT2_MARK, SD1_DAT3_MARK,
|
||||
};
|
||||
|
|
@ -3787,27 +3765,7 @@ static const unsigned int sdhi1_wp_mux[] = {
|
|||
};
|
||||
|
||||
/* - SDHI2 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi2_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(4, 2),
|
||||
};
|
||||
|
||||
static const unsigned int sdhi2_data1_mux[] = {
|
||||
SD2_DAT0_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int sdhi2_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
|
||||
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
|
||||
};
|
||||
|
||||
static const unsigned int sdhi2_data4_mux[] = {
|
||||
SD2_DAT0_MARK, SD2_DAT1_MARK,
|
||||
SD2_DAT2_MARK, SD2_DAT3_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int sdhi2_data8_pins[] = {
|
||||
static const unsigned int sdhi2_data_pins[] = {
|
||||
/* D[0:7] */
|
||||
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
|
||||
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
|
||||
|
|
@ -3815,7 +3773,7 @@ static const unsigned int sdhi2_data8_pins[] = {
|
|||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
};
|
||||
|
||||
static const unsigned int sdhi2_data8_mux[] = {
|
||||
static const unsigned int sdhi2_data_mux[] = {
|
||||
SD2_DAT0_MARK, SD2_DAT1_MARK,
|
||||
SD2_DAT2_MARK, SD2_DAT3_MARK,
|
||||
SD2_DAT4_MARK, SD2_DAT5_MARK,
|
||||
|
|
@ -3877,27 +3835,7 @@ static const unsigned int sdhi2_ds_mux[] = {
|
|||
};
|
||||
|
||||
/* - SDHI3 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi3_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(4, 9),
|
||||
};
|
||||
|
||||
static const unsigned int sdhi3_data1_mux[] = {
|
||||
SD3_DAT0_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int sdhi3_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
|
||||
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
|
||||
};
|
||||
|
||||
static const unsigned int sdhi3_data4_mux[] = {
|
||||
SD3_DAT0_MARK, SD3_DAT1_MARK,
|
||||
SD3_DAT2_MARK, SD3_DAT3_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int sdhi3_data8_pins[] = {
|
||||
static const unsigned int sdhi3_data_pins[] = {
|
||||
/* D[0:7] */
|
||||
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
|
||||
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
|
||||
|
|
@ -3905,7 +3843,7 @@ static const unsigned int sdhi3_data8_pins[] = {
|
|||
RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
|
||||
};
|
||||
|
||||
static const unsigned int sdhi3_data8_mux[] = {
|
||||
static const unsigned int sdhi3_data_mux[] = {
|
||||
SD3_DAT0_MARK, SD3_DAT1_MARK,
|
||||
SD3_DAT2_MARK, SD3_DAT3_MARK,
|
||||
SD3_DAT4_MARK, SD3_DAT5_MARK,
|
||||
|
|
@ -4227,60 +4165,56 @@ static const unsigned int vin4_data18_a_pins[] = {
|
|||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
};
|
||||
|
||||
static const unsigned int vin4_data18_a_mux[] = {
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int vin4_data_a_pins[] = {
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
};
|
||||
|
||||
static const unsigned int vin4_data_a_mux[] = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
|
||||
static const union vin_data vin4_data_a_pins = {
|
||||
.data24 = {
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
|
||||
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
},
|
||||
};
|
||||
|
||||
static const union vin_data vin4_data_a_mux = {
|
||||
.data24 = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
},
|
||||
};
|
||||
|
||||
static const unsigned int vin4_data18_b_pins[] = {
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
|
|
@ -4297,48 +4231,44 @@ static const unsigned int vin4_data18_b_mux[] = {
|
|||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int vin4_data_b_pins[] = {
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
};
|
||||
|
||||
static const unsigned int vin4_data_b_mux[] = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
|
||||
static const union vin_data vin4_data_b_pins = {
|
||||
.data24 = {
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
|
||||
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
},
|
||||
};
|
||||
|
||||
static const union vin_data vin4_data_b_mux = {
|
||||
.data24 = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
},
|
||||
};
|
||||
|
||||
static const unsigned int vin4_sync_pins[] = {
|
||||
/* VSYNC_N, HSYNC_N */
|
||||
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
|
||||
|
|
@ -4373,30 +4303,26 @@ static const unsigned int vin4_clk_mux[] = {
|
|||
};
|
||||
|
||||
/* - VIN5 ------------------------------------------------------------------- */
|
||||
static const union vin_data16 vin5_data_pins = {
|
||||
.data16 = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
},
|
||||
static const unsigned int vin5_data_pins[] = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
};
|
||||
|
||||
static const union vin_data16 vin5_data_mux = {
|
||||
.data16 = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
VI5_DATA8_MARK, VI5_DATA9_MARK,
|
||||
VI5_DATA10_MARK, VI5_DATA11_MARK,
|
||||
VI5_DATA12_MARK, VI5_DATA13_MARK,
|
||||
VI5_DATA14_MARK, VI5_DATA15_MARK,
|
||||
},
|
||||
static const unsigned int vin5_data_mux[] = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
VI5_DATA8_MARK, VI5_DATA9_MARK,
|
||||
VI5_DATA10_MARK, VI5_DATA11_MARK,
|
||||
VI5_DATA12_MARK, VI5_DATA13_MARK,
|
||||
VI5_DATA14_MARK, VI5_DATA15_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int vin5_sync_pins[] = {
|
||||
|
|
@ -4433,9 +4359,9 @@ static const unsigned int vin5_clk_mux[] = {
|
|||
};
|
||||
|
||||
static const struct {
|
||||
struct sh_pfc_pin_group common[324];
|
||||
struct sh_pfc_pin_group common[326];
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77965
|
||||
struct sh_pfc_pin_group automotive[30];
|
||||
struct sh_pfc_pin_group automotive[31];
|
||||
#endif
|
||||
} pinmux_groups = {
|
||||
.common = {
|
||||
|
|
@ -4639,11 +4565,11 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(pwm6_a),
|
||||
SH_PFC_PIN_GROUP(pwm6_b),
|
||||
SH_PFC_PIN_GROUP(qspi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi0_data2),
|
||||
SH_PFC_PIN_GROUP(qspi0_data4),
|
||||
BUS_DATA_PIN_GROUP(qspi0_data, 2),
|
||||
BUS_DATA_PIN_GROUP(qspi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(qspi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi1_data2),
|
||||
SH_PFC_PIN_GROUP(qspi1_data4),
|
||||
BUS_DATA_PIN_GROUP(qspi1_data, 2),
|
||||
BUS_DATA_PIN_GROUP(qspi1_data, 4),
|
||||
SH_PFC_PIN_GROUP(sata0_devslp_a),
|
||||
SH_PFC_PIN_GROUP(sata0_devslp_b),
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
|
|
@ -4675,28 +4601,28 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(scif5_clk_b),
|
||||
SH_PFC_PIN_GROUP(scif_clk_a),
|
||||
SH_PFC_PIN_GROUP(scif_clk_b),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi0_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi0_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi1_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi1_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data4),
|
||||
SH_PFC_PIN_GROUP(sdhi2_data8),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
|
||||
BUS_DATA_PIN_GROUP(sdhi2_data, 8),
|
||||
SH_PFC_PIN_GROUP(sdhi2_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi2_cd_a),
|
||||
SH_PFC_PIN_GROUP(sdhi2_wp_a),
|
||||
SH_PFC_PIN_GROUP(sdhi2_cd_b),
|
||||
SH_PFC_PIN_GROUP(sdhi2_wp_b),
|
||||
SH_PFC_PIN_GROUP(sdhi2_ds),
|
||||
SH_PFC_PIN_GROUP(sdhi3_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi3_data4),
|
||||
SH_PFC_PIN_GROUP(sdhi3_data8),
|
||||
BUS_DATA_PIN_GROUP(sdhi3_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi3_data, 4),
|
||||
BUS_DATA_PIN_GROUP(sdhi3_data, 8),
|
||||
SH_PFC_PIN_GROUP(sdhi3_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi3_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi3_wp),
|
||||
|
|
@ -4737,28 +4663,30 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(usb0),
|
||||
SH_PFC_PIN_GROUP(usb1),
|
||||
SH_PFC_PIN_GROUP(usb30),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
|
||||
SH_PFC_PIN_GROUP(vin4_data18_a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
|
||||
SH_PFC_PIN_GROUP(vin4_data18_b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
|
||||
SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
|
||||
SH_PFC_PIN_GROUP(vin4_sync),
|
||||
SH_PFC_PIN_GROUP(vin4_field),
|
||||
SH_PFC_PIN_GROUP(vin4_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin4_clk),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 8),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 16),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 16),
|
||||
SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
|
||||
SH_PFC_PIN_GROUP(vin5_sync),
|
||||
SH_PFC_PIN_GROUP(vin5_field),
|
||||
SH_PFC_PIN_GROUP(vin5_clkenb),
|
||||
|
|
@ -4796,6 +4724,7 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(drif3_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(drif3_data0_b),
|
||||
SH_PFC_PIN_GROUP(drif3_data1_b),
|
||||
SH_PFC_PIN_GROUP(mlb_3pin),
|
||||
}
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
|
||||
};
|
||||
|
|
@ -4991,6 +4920,12 @@ static const char * const intc_ex_groups[] = {
|
|||
"intc_ex_irq5",
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77965
|
||||
static const char * const mlb_3pin_groups[] = {
|
||||
"mlb_3pin",
|
||||
};
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
|
||||
|
||||
static const char * const msiof0_groups[] = {
|
||||
"msiof0_clk",
|
||||
"msiof0_sync",
|
||||
|
|
@ -5309,6 +5244,7 @@ static const char * const vin4_groups[] = {
|
|||
"vin4_data18_b",
|
||||
"vin4_data20_b",
|
||||
"vin4_data24_b",
|
||||
"vin4_g8",
|
||||
"vin4_sync",
|
||||
"vin4_field",
|
||||
"vin4_clkenb",
|
||||
|
|
@ -5320,6 +5256,7 @@ static const char * const vin5_groups[] = {
|
|||
"vin5_data10",
|
||||
"vin5_data12",
|
||||
"vin5_data16",
|
||||
"vin5_high8",
|
||||
"vin5_sync",
|
||||
"vin5_field",
|
||||
"vin5_clkenb",
|
||||
|
|
@ -5329,7 +5266,7 @@ static const char * const vin5_groups[] = {
|
|||
static const struct {
|
||||
struct sh_pfc_function common[53];
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77965
|
||||
struct sh_pfc_function automotive[4];
|
||||
struct sh_pfc_function automotive[5];
|
||||
#endif
|
||||
} pinmux_functions = {
|
||||
.common = {
|
||||
|
|
@ -5393,6 +5330,7 @@ static const struct {
|
|||
SH_PFC_FUNCTION(drif1),
|
||||
SH_PFC_FUNCTION(drif2),
|
||||
SH_PFC_FUNCTION(drif3),
|
||||
SH_PFC_FUNCTION(mlb_3pin),
|
||||
}
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
|
||||
};
|
||||
|
|
@ -5400,23 +5338,11 @@ static const struct {
|
|||
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
#define F_(x, y) FN_##y
|
||||
#define FM(x) FN_##x
|
||||
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
|
||||
GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP0_31_16 RESERVED */
|
||||
GP_0_15_FN, GPSR0_15,
|
||||
GP_0_14_FN, GPSR0_14,
|
||||
GP_0_13_FN, GPSR0_13,
|
||||
|
|
@ -5468,24 +5394,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_1_1_FN, GPSR1_1,
|
||||
GP_1_0_FN, GPSR1_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
|
||||
GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP2_31_15 RESERVED */
|
||||
GP_2_14_FN, GPSR2_14,
|
||||
GP_2_13_FN, GPSR2_13,
|
||||
GP_2_12_FN, GPSR2_12,
|
||||
|
|
@ -5502,23 +5415,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_2_1_FN, GPSR2_1,
|
||||
GP_2_0_FN, GPSR2_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
|
||||
GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP3_31_16 RESERVED */
|
||||
GP_3_15_FN, GPSR3_15,
|
||||
GP_3_14_FN, GPSR3_14,
|
||||
GP_3_13_FN, GPSR3_13,
|
||||
|
|
@ -5536,21 +5437,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_3_1_FN, GPSR3_1,
|
||||
GP_3_0_FN, GPSR3_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
|
||||
GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP4_31_18 RESERVED */
|
||||
GP_4_17_FN, GPSR4_17,
|
||||
GP_4_16_FN, GPSR4_16,
|
||||
GP_4_15_FN, GPSR4_15,
|
||||
|
|
@ -5638,35 +5529,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_6_1_FN, GPSR6_1,
|
||||
GP_6_0_FN, GPSR6_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
|
||||
GROUP(-28, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP7_31_4 RESERVED */
|
||||
GP_7_3_FN, GPSR7_3,
|
||||
GP_7_2_FN, GPSR7_2,
|
||||
GP_7_1_FN, GPSR7_1,
|
||||
|
|
@ -5747,12 +5613,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
IP6_7_4
|
||||
IP6_3_0 ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
|
||||
{ PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
|
||||
GROUP(4, 4, 4, 4, -4, 4, 4, 4),
|
||||
GROUP(
|
||||
IP7_31_28
|
||||
IP7_27_24
|
||||
IP7_23_20
|
||||
IP7_19_16
|
||||
/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP7_15_12 RESERVED */
|
||||
IP7_11_8
|
||||
IP7_7_4
|
||||
IP7_3_0 ))
|
||||
|
|
@ -5857,13 +5725,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
IP17_7_4
|
||||
IP17_3_0 ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
|
||||
/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
|
||||
GROUP(-24, 4, 4),
|
||||
GROUP(
|
||||
/* IP18_31_8 RESERVED */
|
||||
IP18_7_4
|
||||
IP18_3_0 ))
|
||||
},
|
||||
|
|
@ -5873,8 +5738,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
#define F_(x, y) x,
|
||||
#define FM(x) FN_##x,
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
|
||||
GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
|
||||
1, 1, 1, 2, 2, 1, 2, 3),
|
||||
GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
|
||||
1, 1, 1, 2, 2, 1, 2, -3),
|
||||
GROUP(
|
||||
MOD_SEL0_31_30_29
|
||||
MOD_SEL0_28_27
|
||||
|
|
@ -5886,7 +5751,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL0_19
|
||||
MOD_SEL0_18_17
|
||||
MOD_SEL0_16
|
||||
0, 0, /* RESERVED 15 */
|
||||
/* RESERVED 15 */
|
||||
MOD_SEL0_14_13
|
||||
MOD_SEL0_12
|
||||
MOD_SEL0_11
|
||||
|
|
@ -5895,12 +5760,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL0_7_6
|
||||
MOD_SEL0_5
|
||||
MOD_SEL0_4_3
|
||||
/* RESERVED 2, 1, 0 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0 ))
|
||||
/* RESERVED 2, 1, 0 */ ))
|
||||
},
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
|
||||
GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
|
||||
1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
|
||||
1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
MOD_SEL1_31_30
|
||||
MOD_SEL1_29_28_27
|
||||
|
|
@ -5917,7 +5781,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL1_11
|
||||
MOD_SEL1_10
|
||||
MOD_SEL1_9
|
||||
0, 0, 0, 0, /* RESERVED 8, 7 */
|
||||
/* RESERVED 8, 7 */
|
||||
MOD_SEL1_6
|
||||
MOD_SEL1_5
|
||||
MOD_SEL1_4
|
||||
|
|
@ -5928,7 +5792,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
},
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
|
||||
GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
|
||||
1, 4, 4, 4, 3, 1),
|
||||
-16, 1),
|
||||
GROUP(
|
||||
MOD_SEL2_31
|
||||
MOD_SEL2_30
|
||||
|
|
@ -5942,19 +5806,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL2_19
|
||||
MOD_SEL2_18
|
||||
MOD_SEL2_17
|
||||
/* RESERVED 16 */
|
||||
0, 0,
|
||||
/* RESERVED 15, 14, 13, 12 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 11, 10, 9, 8 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 7, 6, 5, 4 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 3, 2, 1 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 16-1 */
|
||||
MOD_SEL2_0 ))
|
||||
},
|
||||
{ },
|
||||
|
|
@ -6219,7 +6071,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
|||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
|
||||
static int r8a77965_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = -EINVAL;
|
||||
|
||||
|
|
@ -6476,57 +6328,16 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc,
|
||||
unsigned int pin)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
unsigned int bit;
|
||||
|
||||
reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
|
||||
if (!reg)
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
|
||||
if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
|
||||
return PIN_CONFIG_BIAS_PULL_UP;
|
||||
else
|
||||
return PIN_CONFIG_BIAS_PULL_DOWN;
|
||||
}
|
||||
|
||||
static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
u32 enable, updown;
|
||||
unsigned int bit;
|
||||
|
||||
reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
|
||||
if (!reg)
|
||||
return;
|
||||
|
||||
enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
|
||||
if (bias != PIN_CONFIG_BIAS_DISABLE)
|
||||
enable |= BIT(bit);
|
||||
|
||||
updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
|
||||
if (bias == PIN_CONFIG_BIAS_PULL_UP)
|
||||
updown |= BIT(bit);
|
||||
|
||||
sh_pfc_write(pfc, reg->pud, updown);
|
||||
sh_pfc_write(pfc, reg->puen, enable);
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
|
||||
static const struct sh_pfc_soc_operations r8a77965_pfc_ops = {
|
||||
.pin_to_pocctrl = r8a77965_pin_to_pocctrl,
|
||||
.get_bias = r8a77965_pinmux_get_bias,
|
||||
.set_bias = r8a77965_pinmux_set_bias,
|
||||
.get_bias = rcar_pinmux_get_bias,
|
||||
.set_bias = rcar_pinmux_set_bias,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A774B1
|
||||
const struct sh_pfc_soc_info r8a774b1_pinmux_info = {
|
||||
.name = "r8a774b1_pfc",
|
||||
.ops = &r8a77965_pinmux_ops,
|
||||
.ops = &r8a77965_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
|
@ -6551,7 +6362,7 @@ const struct sh_pfc_soc_info r8a774b1_pinmux_info = {
|
|||
#ifdef CONFIG_PINCTRL_PFC_R8A77965
|
||||
const struct sh_pfc_soc_info r8a77965_pinmux_info = {
|
||||
.name = "r8a77965_pfc",
|
||||
.ops = &r8a77965_pinmux_ops,
|
||||
.ops = &r8a77965_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
|
|
|||
|
|
@ -21,12 +21,23 @@
|
|||
#include "sh_pfc.h"
|
||||
|
||||
#define CPU_ALL_GP(fn, sfx) \
|
||||
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_28(1, fn, sfx), \
|
||||
PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_6(4, fn, sfx), \
|
||||
PORT_GP_15(5, fn, sfx)
|
||||
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
|
||||
|
||||
#define CPU_ALL_NOGP(fn) \
|
||||
PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
|
||||
PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
|
||||
PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
|
||||
|
||||
/*
|
||||
* F_() : just information
|
||||
* FM() : macro for FN_xxx / xxx_MARK
|
||||
|
|
@ -161,7 +172,7 @@
|
|||
#define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
|
@ -222,7 +233,6 @@
|
|||
#define IP8_19_16 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP8_23_20 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP8_27_24 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP8_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
||||
#define PINMUX_GPSR \
|
||||
\
|
||||
|
|
@ -281,8 +291,7 @@ FM(IP8_11_8) IP8_11_8 \
|
|||
FM(IP8_15_12) IP8_15_12 \
|
||||
FM(IP8_19_16) IP8_19_16 \
|
||||
FM(IP8_23_20) IP8_23_20 \
|
||||
FM(IP8_27_24) IP8_27_24 \
|
||||
FM(IP8_31_28) IP8_31_28
|
||||
FM(IP8_27_24) IP8_27_24
|
||||
|
||||
/* MOD_SEL0 */ /* 0 */ /* 1 */
|
||||
#define MOD_SEL0_11 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
|
||||
|
|
@ -720,8 +729,17 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_OUT),
|
||||
};
|
||||
|
||||
/*
|
||||
* Pins not associated with a GPIO port.
|
||||
*/
|
||||
enum {
|
||||
GP_ASSIGN_LAST(),
|
||||
NOGP_ALL(),
|
||||
};
|
||||
|
||||
static const struct sh_pfc_pin pinmux_pins[] = {
|
||||
PINMUX_GPIO_GP_ALL(),
|
||||
PINMUX_NOGP_ALL(),
|
||||
};
|
||||
|
||||
/* - AVB0 ------------------------------------------------------------------- */
|
||||
|
|
@ -1084,30 +1102,14 @@ static const unsigned int intc_ex_irq5_mux[] = {
|
|||
};
|
||||
|
||||
/* - MMC -------------------------------------------------------------------- */
|
||||
static const unsigned int mmc_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(3, 6),
|
||||
};
|
||||
static const unsigned int mmc_data1_mux[] = {
|
||||
MMC_D0_MARK,
|
||||
};
|
||||
static const unsigned int mmc_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
};
|
||||
static const unsigned int mmc_data4_mux[] = {
|
||||
MMC_D0_MARK, MMC_D1_MARK,
|
||||
MMC_D2_MARK, MMC_D3_MARK,
|
||||
};
|
||||
static const unsigned int mmc_data8_pins[] = {
|
||||
static const unsigned int mmc_data_pins[] = {
|
||||
/* D[0:7] */
|
||||
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
|
||||
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
|
||||
};
|
||||
static const unsigned int mmc_data8_mux[] = {
|
||||
static const unsigned int mmc_data_mux[] = {
|
||||
MMC_D0_MARK, MMC_D1_MARK,
|
||||
MMC_D2_MARK, MMC_D3_MARK,
|
||||
MMC_D4_MARK, MMC_D5_MARK,
|
||||
|
|
@ -1375,22 +1377,6 @@ static const unsigned int qspi0_ctrl_pins[] = {
|
|||
static const unsigned int qspi0_ctrl_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data2_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1 */
|
||||
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
|
||||
};
|
||||
static const unsigned int qspi0_data2_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data4_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
|
||||
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
|
||||
RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
|
||||
};
|
||||
static const unsigned int qspi0_data4_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
QSPI0_IO2_MARK, QSPI0_IO3_MARK
|
||||
};
|
||||
|
||||
/* - QSPI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int qspi1_ctrl_pins[] = {
|
||||
|
|
@ -1400,36 +1386,14 @@ static const unsigned int qspi1_ctrl_pins[] = {
|
|||
static const unsigned int qspi1_ctrl_mux[] = {
|
||||
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data2_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1 */
|
||||
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
|
||||
};
|
||||
static const unsigned int qspi1_data2_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data4_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
|
||||
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
|
||||
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
|
||||
};
|
||||
static const unsigned int qspi1_data4_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
QSPI1_IO2_MARK, QSPI1_IO3_MARK
|
||||
};
|
||||
|
||||
/* - RPC -------------------------------------------------------------------- */
|
||||
static const unsigned int rpc_clk1_pins[] = {
|
||||
static const unsigned int rpc_clk_pins[] = {
|
||||
/* Octal-SPI flash: C/SCLK */
|
||||
RCAR_GP_PIN(5, 0),
|
||||
};
|
||||
static const unsigned int rpc_clk1_mux[] = {
|
||||
QSPI0_SPCLK_MARK,
|
||||
};
|
||||
static const unsigned int rpc_clk2_pins[] = {
|
||||
/* HyperFlash: CK, CK# */
|
||||
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
|
||||
};
|
||||
static const unsigned int rpc_clk2_mux[] = {
|
||||
static const unsigned int rpc_clk_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
|
||||
};
|
||||
static const unsigned int rpc_ctrl_pins[] = {
|
||||
|
|
@ -1621,25 +1585,21 @@ static const unsigned int tmu_tclk2_b_mux[] = {
|
|||
};
|
||||
|
||||
/* - VIN0 ------------------------------------------------------------------- */
|
||||
static const union vin_data12 vin0_data_pins = {
|
||||
.data12 = {
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
|
||||
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
|
||||
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
|
||||
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
|
||||
},
|
||||
static const unsigned int vin0_data_pins[] = {
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
|
||||
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
|
||||
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
|
||||
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
|
||||
};
|
||||
static const union vin_data12 vin0_data_mux = {
|
||||
.data12 = {
|
||||
VI0_DATA0_MARK, VI0_DATA1_MARK,
|
||||
VI0_DATA2_MARK, VI0_DATA3_MARK,
|
||||
VI0_DATA4_MARK, VI0_DATA5_MARK,
|
||||
VI0_DATA6_MARK, VI0_DATA7_MARK,
|
||||
VI0_DATA8_MARK, VI0_DATA9_MARK,
|
||||
VI0_DATA10_MARK, VI0_DATA11_MARK,
|
||||
},
|
||||
static const unsigned int vin0_data_mux[] = {
|
||||
VI0_DATA0_MARK, VI0_DATA1_MARK,
|
||||
VI0_DATA2_MARK, VI0_DATA3_MARK,
|
||||
VI0_DATA4_MARK, VI0_DATA5_MARK,
|
||||
VI0_DATA6_MARK, VI0_DATA7_MARK,
|
||||
VI0_DATA8_MARK, VI0_DATA9_MARK,
|
||||
VI0_DATA10_MARK, VI0_DATA11_MARK,
|
||||
};
|
||||
static const unsigned int vin0_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
|
|
@ -1671,25 +1631,21 @@ static const unsigned int vin0_clk_mux[] = {
|
|||
};
|
||||
|
||||
/* - VIN1 ------------------------------------------------------------------- */
|
||||
static const union vin_data12 vin1_data_pins = {
|
||||
.data12 = {
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
|
||||
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
|
||||
},
|
||||
static const unsigned int vin1_data_pins[] = {
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
|
||||
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
|
||||
};
|
||||
static const union vin_data12 vin1_data_mux = {
|
||||
.data12 = {
|
||||
VI1_DATA0_MARK, VI1_DATA1_MARK,
|
||||
VI1_DATA2_MARK, VI1_DATA3_MARK,
|
||||
VI1_DATA4_MARK, VI1_DATA5_MARK,
|
||||
VI1_DATA6_MARK, VI1_DATA7_MARK,
|
||||
VI1_DATA8_MARK, VI1_DATA9_MARK,
|
||||
VI1_DATA10_MARK, VI1_DATA11_MARK,
|
||||
},
|
||||
static const unsigned int vin1_data_mux[] = {
|
||||
VI1_DATA0_MARK, VI1_DATA1_MARK,
|
||||
VI1_DATA2_MARK, VI1_DATA3_MARK,
|
||||
VI1_DATA4_MARK, VI1_DATA5_MARK,
|
||||
VI1_DATA6_MARK, VI1_DATA7_MARK,
|
||||
VI1_DATA8_MARK, VI1_DATA9_MARK,
|
||||
VI1_DATA10_MARK, VI1_DATA11_MARK,
|
||||
};
|
||||
static const unsigned int vin1_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
|
|
@ -1765,9 +1721,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(intc_ex_irq3),
|
||||
SH_PFC_PIN_GROUP(intc_ex_irq4),
|
||||
SH_PFC_PIN_GROUP(intc_ex_irq5),
|
||||
SH_PFC_PIN_GROUP(mmc_data1),
|
||||
SH_PFC_PIN_GROUP(mmc_data4),
|
||||
SH_PFC_PIN_GROUP(mmc_data8),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 1),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 4),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 8),
|
||||
SH_PFC_PIN_GROUP(mmc_ctrl),
|
||||
SH_PFC_PIN_GROUP(msiof0_clk),
|
||||
SH_PFC_PIN_GROUP(msiof0_sync),
|
||||
|
|
@ -1804,13 +1760,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(pwm4_a),
|
||||
SH_PFC_PIN_GROUP(pwm4_b),
|
||||
SH_PFC_PIN_GROUP(qspi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi0_data2),
|
||||
SH_PFC_PIN_GROUP(qspi0_data4),
|
||||
SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
|
||||
SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
|
||||
SH_PFC_PIN_GROUP(qspi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi1_data2),
|
||||
SH_PFC_PIN_GROUP(qspi1_data4),
|
||||
SH_PFC_PIN_GROUP(rpc_clk1),
|
||||
SH_PFC_PIN_GROUP(rpc_clk2),
|
||||
SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
|
||||
SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
|
||||
BUS_DATA_PIN_GROUP(rpc_clk, 1),
|
||||
BUS_DATA_PIN_GROUP(rpc_clk, 2),
|
||||
SH_PFC_PIN_GROUP(rpc_ctrl),
|
||||
SH_PFC_PIN_GROUP(rpc_data),
|
||||
SH_PFC_PIN_GROUP(rpc_reset),
|
||||
|
|
@ -1835,16 +1791,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(tmu_tclk1_b),
|
||||
SH_PFC_PIN_GROUP(tmu_tclk2_a),
|
||||
SH_PFC_PIN_GROUP(tmu_tclk2_b),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 8),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 12),
|
||||
SH_PFC_PIN_GROUP(vin0_sync),
|
||||
SH_PFC_PIN_GROUP(vin0_field),
|
||||
SH_PFC_PIN_GROUP(vin0_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin0_clk),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 8),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 12),
|
||||
SH_PFC_PIN_GROUP(vin1_sync),
|
||||
SH_PFC_PIN_GROUP(vin1_field),
|
||||
SH_PFC_PIN_GROUP(vin1_clkenb),
|
||||
|
|
@ -2129,17 +2085,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
|||
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
#define F_(x, y) FN_##y
|
||||
#define FM(x) FN_##x
|
||||
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
|
||||
GROUP(-10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP0_31_22 RESERVED */
|
||||
GP_0_21_FN, GPSR0_21,
|
||||
GP_0_20_FN, GPSR0_20,
|
||||
GP_0_19_FN, GPSR0_19,
|
||||
|
|
@ -2197,22 +2147,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_1_1_FN, GPSR1_1,
|
||||
GP_1_0_FN, GPSR1_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
|
||||
GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP2_31_17 RESERVED */
|
||||
GP_2_16_FN, GPSR2_16,
|
||||
GP_2_15_FN, GPSR2_15,
|
||||
GP_2_14_FN, GPSR2_14,
|
||||
|
|
@ -2231,22 +2170,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_2_1_FN, GPSR2_1,
|
||||
GP_2_0_FN, GPSR2_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
|
||||
GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP3_31_17 RESERVED */
|
||||
GP_3_16_FN, GPSR3_16,
|
||||
GP_3_15_FN, GPSR3_15,
|
||||
GP_3_14_FN, GPSR3_14,
|
||||
|
|
@ -2265,33 +2193,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_3_1_FN, GPSR3_1,
|
||||
GP_3_0_FN, GPSR3_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
|
||||
GROUP(-26, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP4_31_6 RESERVED */
|
||||
GP_4_5_FN, GPSR4_5,
|
||||
GP_4_4_FN, GPSR4_4,
|
||||
GP_4_3_FN, GPSR4_3,
|
||||
|
|
@ -2299,24 +2204,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_4_1_FN, GPSR4_1,
|
||||
GP_4_0_FN, GPSR4_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
|
||||
GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP5_31_15 RESERVED */
|
||||
GP_5_14_FN, GPSR5_14,
|
||||
GP_5_13_FN, GPSR5_13,
|
||||
GP_5_12_FN, GPSR5_12,
|
||||
|
|
@ -2418,8 +2310,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
IP7_7_4
|
||||
IP7_3_0 ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
|
||||
IP8_31_28
|
||||
{ PINMUX_CFG_REG_VAR("IPSR8", 0xe6060220, 32,
|
||||
GROUP(-4, 4, 4, 4, 4, 4, 4, 4),
|
||||
GROUP(
|
||||
/* IP8_31_28 RESERVED */
|
||||
IP8_27_24
|
||||
IP8_23_20
|
||||
IP8_19_16
|
||||
|
|
@ -2434,19 +2328,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
#define F_(x, y) x,
|
||||
#define FM(x) FN_##x,
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
|
||||
GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1),
|
||||
GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* RESERVED 31, 30, 29, 28 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 27, 26, 25, 24 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 23, 22, 21, 20 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 19, 18, 17, 16 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 15, 14, 13, 12 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 31-12 */
|
||||
MOD_SEL0_11
|
||||
MOD_SEL0_10
|
||||
MOD_SEL0_9
|
||||
|
|
@ -2478,8 +2362,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
|||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
|
||||
u32 *pocctrl)
|
||||
static int r8a77970_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = pin & 0x1f;
|
||||
|
||||
|
|
@ -2498,13 +2381,155 @@ static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations pinmux_ops = {
|
||||
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
|
||||
[ 0] = RCAR_GP_PIN(0, 0), /* DU_DR2 */
|
||||
[ 1] = RCAR_GP_PIN(0, 1), /* DU_DR3 */
|
||||
[ 2] = RCAR_GP_PIN(0, 2), /* DU_DR4 */
|
||||
[ 3] = RCAR_GP_PIN(0, 3), /* DU_DR5 */
|
||||
[ 4] = RCAR_GP_PIN(0, 4), /* DU_DR6 */
|
||||
[ 5] = RCAR_GP_PIN(0, 5), /* DU_DR7 */
|
||||
[ 6] = RCAR_GP_PIN(0, 6), /* DU_DG2 */
|
||||
[ 7] = RCAR_GP_PIN(0, 7), /* DU_DG3 */
|
||||
[ 8] = RCAR_GP_PIN(0, 8), /* DU_DG4 */
|
||||
[ 9] = RCAR_GP_PIN(0, 9), /* DU_DG5 */
|
||||
[10] = RCAR_GP_PIN(0, 10), /* DU_DG6 */
|
||||
[11] = RCAR_GP_PIN(0, 11), /* DU_DG7 */
|
||||
[12] = RCAR_GP_PIN(0, 12), /* DU_DB2 */
|
||||
[13] = RCAR_GP_PIN(0, 13), /* DU_DB3 */
|
||||
[14] = RCAR_GP_PIN(0, 14), /* DU_DB4 */
|
||||
[15] = RCAR_GP_PIN(0, 15), /* DU_DB5 */
|
||||
[16] = RCAR_GP_PIN(0, 16), /* DU_DB6 */
|
||||
[17] = RCAR_GP_PIN(0, 17), /* DU_DB7 */
|
||||
[18] = RCAR_GP_PIN(0, 18), /* DU_DOTCLKOUT */
|
||||
[19] = RCAR_GP_PIN(0, 19), /* DU_EXHSYNC/DU_HSYNC */
|
||||
[20] = RCAR_GP_PIN(0, 20), /* DU_EXVSYNC/DU_VSYNC */
|
||||
[21] = RCAR_GP_PIN(0, 21), /* DU_EXODDF/DU_ODDF/DISP/CDE */
|
||||
[22] = PIN_DU_DOTCLKIN, /* DU_DOTCLKIN */
|
||||
[23] = PIN_PRESETOUT_N, /* PRESETOUT# */
|
||||
[24] = PIN_EXTALR, /* EXTALR */
|
||||
[25] = PIN_FSCLKST_N, /* FSCLKST# */
|
||||
[26] = RCAR_GP_PIN(1, 0), /* IRQ0 */
|
||||
[27] = PIN_TRST_N, /* TRST# */
|
||||
[28] = PIN_TCK, /* TCK */
|
||||
[29] = PIN_TMS, /* TMS */
|
||||
[30] = PIN_TDI, /* TDI */
|
||||
[31] = RCAR_GP_PIN(2, 0), /* VI0_CLK */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
|
||||
[ 0] = RCAR_GP_PIN(2, 1), /* VI0_CLKENB */
|
||||
[ 1] = RCAR_GP_PIN(2, 2), /* VI0_HSYNC# */
|
||||
[ 2] = RCAR_GP_PIN(2, 3), /* VI0_VSYNC# */
|
||||
[ 3] = RCAR_GP_PIN(2, 4), /* VI0_DATA0 */
|
||||
[ 4] = RCAR_GP_PIN(2, 5), /* VI0_DATA1 */
|
||||
[ 5] = RCAR_GP_PIN(2, 6), /* VI0_DATA2 */
|
||||
[ 6] = RCAR_GP_PIN(2, 7), /* VI0_DATA3 */
|
||||
[ 7] = RCAR_GP_PIN(2, 8), /* VI0_DATA4 */
|
||||
[ 8] = RCAR_GP_PIN(2, 9), /* VI0_DATA5 */
|
||||
[ 9] = RCAR_GP_PIN(2, 10), /* VI0_DATA6 */
|
||||
[10] = RCAR_GP_PIN(2, 11), /* VI0_DATA7 */
|
||||
[11] = RCAR_GP_PIN(2, 12), /* VI0_DATA8 */
|
||||
[12] = RCAR_GP_PIN(2, 13), /* VI0_DATA9 */
|
||||
[13] = RCAR_GP_PIN(2, 14), /* VI0_DATA10 */
|
||||
[14] = RCAR_GP_PIN(2, 15), /* VI0_DATA11 */
|
||||
[15] = RCAR_GP_PIN(2, 16), /* VI0_FIELD */
|
||||
[16] = RCAR_GP_PIN(3, 0), /* VI1_CLK */
|
||||
[17] = RCAR_GP_PIN(3, 1), /* VI1_CLKENB */
|
||||
[18] = RCAR_GP_PIN(3, 2), /* VI1_HSYNC# */
|
||||
[19] = RCAR_GP_PIN(3, 3), /* VI1_VSYNC# */
|
||||
[20] = RCAR_GP_PIN(3, 4), /* VI1_DATA0 */
|
||||
[21] = RCAR_GP_PIN(3, 5), /* VI1_DATA1 */
|
||||
[22] = RCAR_GP_PIN(3, 6), /* VI1_DATA2 */
|
||||
[23] = RCAR_GP_PIN(3, 7), /* VI1_DATA3 */
|
||||
[24] = RCAR_GP_PIN(3, 8), /* VI1_DATA4 */
|
||||
[25] = RCAR_GP_PIN(3, 9), /* VI1_DATA5 */
|
||||
[26] = RCAR_GP_PIN(3, 10), /* VI1_DATA6 */
|
||||
[27] = RCAR_GP_PIN(3, 11), /* VI1_DATA7 */
|
||||
[28] = RCAR_GP_PIN(3, 12), /* VI1_DATA8 */
|
||||
[29] = RCAR_GP_PIN(3, 13), /* VI1_DATA9 */
|
||||
[30] = RCAR_GP_PIN(3, 14), /* VI1_DATA10 */
|
||||
[31] = RCAR_GP_PIN(3, 15), /* VI1_DATA11 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
|
||||
[ 0] = RCAR_GP_PIN(3, 16), /* VI1_FIELD */
|
||||
[ 1] = RCAR_GP_PIN(4, 0), /* SCL0 */
|
||||
[ 2] = RCAR_GP_PIN(4, 1), /* SDA0 */
|
||||
[ 3] = RCAR_GP_PIN(4, 2), /* SCL1 */
|
||||
[ 4] = RCAR_GP_PIN(4, 3), /* SDA1 */
|
||||
[ 5] = RCAR_GP_PIN(4, 4), /* SCL2 */
|
||||
[ 6] = RCAR_GP_PIN(4, 5), /* SDA2 */
|
||||
[ 7] = RCAR_GP_PIN(1, 1), /* AVB0_RX_CTL */
|
||||
[ 8] = RCAR_GP_PIN(1, 2), /* AVB0_RXC */
|
||||
[ 9] = RCAR_GP_PIN(1, 3), /* AVB0_RD0 */
|
||||
[10] = RCAR_GP_PIN(1, 4), /* AVB0_RD1 */
|
||||
[11] = RCAR_GP_PIN(1, 5), /* AVB0_RD2 */
|
||||
[12] = RCAR_GP_PIN(1, 6), /* AVB0_RD3 */
|
||||
[13] = RCAR_GP_PIN(1, 7), /* AVB0_TX_CTL */
|
||||
[14] = RCAR_GP_PIN(1, 8), /* AVB0_TXC */
|
||||
[15] = RCAR_GP_PIN(1, 9), /* AVB0_TD0 */
|
||||
[16] = RCAR_GP_PIN(1, 10), /* AVB0_TD1 */
|
||||
[17] = RCAR_GP_PIN(1, 11), /* AVB0_TD2 */
|
||||
[18] = RCAR_GP_PIN(1, 12), /* AVB0_TD3 */
|
||||
[19] = RCAR_GP_PIN(1, 13), /* AVB0_TXCREFCLK */
|
||||
[20] = RCAR_GP_PIN(1, 14), /* AVB0_MDIO */
|
||||
[21] = RCAR_GP_PIN(1, 15), /* AVB0_MDC */
|
||||
[22] = RCAR_GP_PIN(1, 16), /* AVB0_MAGIC */
|
||||
[23] = RCAR_GP_PIN(1, 17), /* AVB0_PHY_INT */
|
||||
[24] = RCAR_GP_PIN(1, 18), /* AVB0_LINK */
|
||||
[25] = RCAR_GP_PIN(1, 19), /* AVB0_AVTP_MATCH */
|
||||
[26] = RCAR_GP_PIN(1, 20), /* AVB0_AVTP_CAPTURE */
|
||||
[27] = RCAR_GP_PIN(1, 21), /* CANFD0_TX_A */
|
||||
[28] = RCAR_GP_PIN(1, 22), /* CANFD0_RX_A */
|
||||
[29] = RCAR_GP_PIN(1, 23), /* CANFD1_TX */
|
||||
[30] = RCAR_GP_PIN(1, 24), /* CANFD1_RX */
|
||||
[31] = RCAR_GP_PIN(1, 25), /* CANFD_CLK */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
|
||||
[ 0] = RCAR_GP_PIN(5, 0), /* QSPI0_SPCLK */
|
||||
[ 1] = RCAR_GP_PIN(5, 1), /* QSPI0_MOSI_IO0 */
|
||||
[ 2] = RCAR_GP_PIN(5, 2), /* QSPI0_MISO_IO1 */
|
||||
[ 3] = RCAR_GP_PIN(5, 3), /* QSPI0_IO2 */
|
||||
[ 4] = RCAR_GP_PIN(5, 4), /* QSPI0_IO3 */
|
||||
[ 5] = RCAR_GP_PIN(5, 5), /* QSPI0_SSL */
|
||||
[ 6] = RCAR_GP_PIN(5, 6), /* QSPI1_SPCLK */
|
||||
[ 7] = RCAR_GP_PIN(5, 7), /* QSPI1_MOSI_IO0 */
|
||||
[ 8] = RCAR_GP_PIN(5, 8), /* QSPI1_MISO_IO1 */
|
||||
[ 9] = RCAR_GP_PIN(5, 9), /* QSPI1_IO2 */
|
||||
[10] = RCAR_GP_PIN(5, 10), /* QSPI1_IO3 */
|
||||
[11] = RCAR_GP_PIN(5, 11), /* QSPI1_SSL */
|
||||
[12] = RCAR_GP_PIN(5, 12), /* RPC_RESET# */
|
||||
[13] = RCAR_GP_PIN(5, 13), /* RPC_WP# */
|
||||
[14] = RCAR_GP_PIN(5, 14), /* RPC_INT# */
|
||||
[15] = RCAR_GP_PIN(1, 26), /* DIGRF_CLKIN */
|
||||
[16] = RCAR_GP_PIN(1, 27), /* DIGRF_CLKOUT */
|
||||
[17] = SH_PFC_PIN_NONE,
|
||||
[18] = SH_PFC_PIN_NONE,
|
||||
[19] = SH_PFC_PIN_NONE,
|
||||
[20] = SH_PFC_PIN_NONE,
|
||||
[21] = SH_PFC_PIN_NONE,
|
||||
[22] = SH_PFC_PIN_NONE,
|
||||
[23] = SH_PFC_PIN_NONE,
|
||||
[24] = SH_PFC_PIN_NONE,
|
||||
[25] = SH_PFC_PIN_NONE,
|
||||
[26] = SH_PFC_PIN_NONE,
|
||||
[27] = SH_PFC_PIN_NONE,
|
||||
[28] = SH_PFC_PIN_NONE,
|
||||
[29] = SH_PFC_PIN_NONE,
|
||||
[30] = SH_PFC_PIN_NONE,
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a77970_pfc_ops = {
|
||||
.pin_to_pocctrl = r8a77970_pin_to_pocctrl,
|
||||
.get_bias = rcar_pinmux_get_bias,
|
||||
.set_bias = rcar_pinmux_set_bias,
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info r8a77970_pinmux_info = {
|
||||
.name = "r8a77970_pfc",
|
||||
.ops = &pinmux_ops,
|
||||
.ops = &r8a77970_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
|
@ -2517,6 +2542,7 @@ const struct sh_pfc_soc_info r8a77970_pinmux_info = {
|
|||
.nr_functions = ARRAY_SIZE(pinmux_functions),
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.bias_regs = pinmux_bias_regs,
|
||||
.ioctrl_regs = pinmux_ioctrl_regs,
|
||||
|
||||
.pinmux_data = pinmux_data,
|
||||
|
|
|
|||
|
|
@ -21,12 +21,23 @@
|
|||
#include "sh_pfc.h"
|
||||
|
||||
#define CPU_ALL_GP(fn, sfx) \
|
||||
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_28(1, fn, sfx), \
|
||||
PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_25(4, fn, sfx), \
|
||||
PORT_GP_15(5, fn, sfx)
|
||||
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
|
||||
|
||||
#define CPU_ALL_NOGP(fn) \
|
||||
PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PIN_NOGP_CFG(DCUTRST_N, "DCUTRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
|
||||
|
||||
/*
|
||||
* F_() : just information
|
||||
|
|
@ -88,7 +99,7 @@
|
|||
#define GPSR1_0 F_(IRQ0, IP2_27_24)
|
||||
|
||||
/* GPSR2 */
|
||||
#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
|
||||
#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
|
||||
#define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12)
|
||||
#define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8)
|
||||
#define GPSR2_26 F_(SDA3, IP10_7_4)
|
||||
|
|
@ -253,11 +264,11 @@
|
|||
#define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
|
@ -269,9 +280,6 @@
|
|||
#define IP10_11_8 FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) FM(VI0_DATA22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP10_15_12 FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) FM(VI0_DATA23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP10_19_16 FM(FSO_TOE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP10_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP10_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP10_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
||||
#define PINMUX_GPSR \
|
||||
\
|
||||
|
|
@ -331,9 +339,9 @@ FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 \
|
|||
FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 \
|
||||
FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 \
|
||||
FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 \
|
||||
FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 \
|
||||
FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 \
|
||||
FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28
|
||||
FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 \
|
||||
FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 \
|
||||
FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28
|
||||
|
||||
/* MOD_SEL0 */ /* 0 */ /* 1 */
|
||||
#define MOD_SEL0_11 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
|
||||
|
|
@ -832,8 +840,17 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_GPSR(IP10_19_16, FSO_TOE_N),
|
||||
};
|
||||
|
||||
/*
|
||||
* Pins not associated with a GPIO port.
|
||||
*/
|
||||
enum {
|
||||
GP_ASSIGN_LAST(),
|
||||
NOGP_ALL(),
|
||||
};
|
||||
|
||||
static const struct sh_pfc_pin pinmux_pins[] = {
|
||||
PINMUX_GPIO_GP_ALL(),
|
||||
PINMUX_NOGP_ALL(),
|
||||
};
|
||||
|
||||
/* - AVB -------------------------------------------------------------------- */
|
||||
|
|
@ -1347,30 +1364,14 @@ static const unsigned int intc_ex_irq5_mux[] = {
|
|||
};
|
||||
|
||||
/* - MMC -------------------------------------------------------------------- */
|
||||
static const unsigned int mmc_data1_pins[] = {
|
||||
/* MMC_D0 */
|
||||
RCAR_GP_PIN(3, 8),
|
||||
};
|
||||
static const unsigned int mmc_data1_mux[] = {
|
||||
MMC_D0_MARK,
|
||||
};
|
||||
static const unsigned int mmc_data4_pins[] = {
|
||||
/* MMC_D[0:3] */
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
};
|
||||
static const unsigned int mmc_data4_mux[] = {
|
||||
MMC_D0_MARK, MMC_D1_MARK,
|
||||
MMC_D2_MARK, MMC_D3_MARK,
|
||||
};
|
||||
static const unsigned int mmc_data8_pins[] = {
|
||||
static const unsigned int mmc_data_pins[] = {
|
||||
/* MMC_D[0:7] */
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
|
||||
RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
|
||||
};
|
||||
static const unsigned int mmc_data8_mux[] = {
|
||||
static const unsigned int mmc_data_mux[] = {
|
||||
MMC_D0_MARK, MMC_D1_MARK,
|
||||
MMC_D2_MARK, MMC_D3_MARK,
|
||||
MMC_D4_MARK, MMC_D5_MARK,
|
||||
|
|
@ -1669,22 +1670,6 @@ static const unsigned int qspi0_ctrl_pins[] = {
|
|||
static const unsigned int qspi0_ctrl_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data2_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1 */
|
||||
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
|
||||
};
|
||||
static const unsigned int qspi0_data2_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data4_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
|
||||
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
|
||||
RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
|
||||
};
|
||||
static const unsigned int qspi0_data4_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
QSPI0_IO2_MARK, QSPI0_IO3_MARK
|
||||
};
|
||||
|
||||
/* - QSPI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int qspi1_ctrl_pins[] = {
|
||||
|
|
@ -1694,36 +1679,14 @@ static const unsigned int qspi1_ctrl_pins[] = {
|
|||
static const unsigned int qspi1_ctrl_mux[] = {
|
||||
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data2_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1 */
|
||||
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
|
||||
};
|
||||
static const unsigned int qspi1_data2_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data4_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
|
||||
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
|
||||
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
|
||||
};
|
||||
static const unsigned int qspi1_data4_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
QSPI1_IO2_MARK, QSPI1_IO3_MARK
|
||||
};
|
||||
|
||||
/* - RPC -------------------------------------------------------------------- */
|
||||
static const unsigned int rpc_clk1_pins[] = {
|
||||
static const unsigned int rpc_clk_pins[] = {
|
||||
/* Octal-SPI flash: C/SCLK */
|
||||
RCAR_GP_PIN(5, 0),
|
||||
};
|
||||
static const unsigned int rpc_clk1_mux[] = {
|
||||
QSPI0_SPCLK_MARK,
|
||||
};
|
||||
static const unsigned int rpc_clk2_pins[] = {
|
||||
/* HyperFlash: CK, CK# */
|
||||
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
|
||||
};
|
||||
static const unsigned int rpc_clk2_mux[] = {
|
||||
static const unsigned int rpc_clk_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
|
||||
};
|
||||
static const unsigned int rpc_ctrl_pins[] = {
|
||||
|
|
@ -1945,37 +1908,33 @@ static const unsigned int tpu_to3_mux[] = {
|
|||
};
|
||||
|
||||
/* - VIN0 ------------------------------------------------------------------- */
|
||||
static const union vin_data vin0_data_pins = {
|
||||
.data24 = {
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
|
||||
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
|
||||
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
|
||||
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
|
||||
RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
|
||||
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
|
||||
RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
|
||||
RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
|
||||
RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
|
||||
RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
|
||||
},
|
||||
static const unsigned int vin0_data_pins[] = {
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
|
||||
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
|
||||
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
|
||||
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
|
||||
RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
|
||||
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
|
||||
RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
|
||||
RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
|
||||
RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
|
||||
RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
|
||||
};
|
||||
static const union vin_data vin0_data_mux = {
|
||||
.data24 = {
|
||||
VI0_DATA0_MARK, VI0_DATA1_MARK,
|
||||
VI0_DATA2_MARK, VI0_DATA3_MARK,
|
||||
VI0_DATA4_MARK, VI0_DATA5_MARK,
|
||||
VI0_DATA6_MARK, VI0_DATA7_MARK,
|
||||
VI0_DATA8_MARK, VI0_DATA9_MARK,
|
||||
VI0_DATA10_MARK, VI0_DATA11_MARK,
|
||||
VI0_DATA12_MARK, VI0_DATA13_MARK,
|
||||
VI0_DATA14_MARK, VI0_DATA15_MARK,
|
||||
VI0_DATA16_MARK, VI0_DATA17_MARK,
|
||||
VI0_DATA18_MARK, VI0_DATA19_MARK,
|
||||
VI0_DATA20_MARK, VI0_DATA21_MARK,
|
||||
VI0_DATA22_MARK, VI0_DATA23_MARK,
|
||||
},
|
||||
static const unsigned int vin0_data_mux[] = {
|
||||
VI0_DATA0_MARK, VI0_DATA1_MARK,
|
||||
VI0_DATA2_MARK, VI0_DATA3_MARK,
|
||||
VI0_DATA4_MARK, VI0_DATA5_MARK,
|
||||
VI0_DATA6_MARK, VI0_DATA7_MARK,
|
||||
VI0_DATA8_MARK, VI0_DATA9_MARK,
|
||||
VI0_DATA10_MARK, VI0_DATA11_MARK,
|
||||
VI0_DATA12_MARK, VI0_DATA13_MARK,
|
||||
VI0_DATA14_MARK, VI0_DATA15_MARK,
|
||||
VI0_DATA16_MARK, VI0_DATA17_MARK,
|
||||
VI0_DATA18_MARK, VI0_DATA19_MARK,
|
||||
VI0_DATA20_MARK, VI0_DATA21_MARK,
|
||||
VI0_DATA22_MARK, VI0_DATA23_MARK,
|
||||
};
|
||||
static const unsigned int vin0_data18_pins[] = {
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
|
|
@ -2029,25 +1988,21 @@ static const unsigned int vin0_clk_mux[] = {
|
|||
};
|
||||
|
||||
/* - VIN1 ------------------------------------------------------------------- */
|
||||
static const union vin_data12 vin1_data_pins = {
|
||||
.data12 = {
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
|
||||
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
|
||||
},
|
||||
static const unsigned int vin1_data_pins[] = {
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
|
||||
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
|
||||
};
|
||||
static const union vin_data12 vin1_data_mux = {
|
||||
.data12 = {
|
||||
VI1_DATA0_MARK, VI1_DATA1_MARK,
|
||||
VI1_DATA2_MARK, VI1_DATA3_MARK,
|
||||
VI1_DATA4_MARK, VI1_DATA5_MARK,
|
||||
VI1_DATA6_MARK, VI1_DATA7_MARK,
|
||||
VI1_DATA8_MARK, VI1_DATA9_MARK,
|
||||
VI1_DATA10_MARK, VI1_DATA11_MARK,
|
||||
},
|
||||
static const unsigned int vin1_data_mux[] = {
|
||||
VI1_DATA0_MARK, VI1_DATA1_MARK,
|
||||
VI1_DATA2_MARK, VI1_DATA3_MARK,
|
||||
VI1_DATA4_MARK, VI1_DATA5_MARK,
|
||||
VI1_DATA6_MARK, VI1_DATA7_MARK,
|
||||
VI1_DATA8_MARK, VI1_DATA9_MARK,
|
||||
VI1_DATA10_MARK, VI1_DATA11_MARK,
|
||||
};
|
||||
static const unsigned int vin1_sync_pins[] = {
|
||||
/* VI1_VSYNC#, VI1_HSYNC# */
|
||||
|
|
@ -2138,9 +2093,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(intc_ex_irq3),
|
||||
SH_PFC_PIN_GROUP(intc_ex_irq4),
|
||||
SH_PFC_PIN_GROUP(intc_ex_irq5),
|
||||
SH_PFC_PIN_GROUP(mmc_data1),
|
||||
SH_PFC_PIN_GROUP(mmc_data4),
|
||||
SH_PFC_PIN_GROUP(mmc_data8),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 1),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 4),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 8),
|
||||
SH_PFC_PIN_GROUP(mmc_ctrl),
|
||||
SH_PFC_PIN_GROUP(mmc_cd),
|
||||
SH_PFC_PIN_GROUP(mmc_wp),
|
||||
|
|
@ -2180,13 +2135,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(pwm4_a),
|
||||
SH_PFC_PIN_GROUP(pwm4_b),
|
||||
SH_PFC_PIN_GROUP(qspi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi0_data2),
|
||||
SH_PFC_PIN_GROUP(qspi0_data4),
|
||||
SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
|
||||
SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
|
||||
SH_PFC_PIN_GROUP(qspi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi1_data2),
|
||||
SH_PFC_PIN_GROUP(qspi1_data4),
|
||||
SH_PFC_PIN_GROUP(rpc_clk1),
|
||||
SH_PFC_PIN_GROUP(rpc_clk2),
|
||||
SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
|
||||
SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
|
||||
BUS_DATA_PIN_GROUP(rpc_clk, 1),
|
||||
BUS_DATA_PIN_GROUP(rpc_clk, 2),
|
||||
SH_PFC_PIN_GROUP(rpc_ctrl),
|
||||
SH_PFC_PIN_GROUP(rpc_data),
|
||||
SH_PFC_PIN_GROUP(rpc_reset),
|
||||
|
|
@ -2215,20 +2170,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(tpu_to1),
|
||||
SH_PFC_PIN_GROUP(tpu_to2),
|
||||
SH_PFC_PIN_GROUP(tpu_to3),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 8),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 16),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 16),
|
||||
SH_PFC_PIN_GROUP(vin0_data18),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 20),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 24),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 20),
|
||||
BUS_DATA_PIN_GROUP(vin0_data, 24),
|
||||
SH_PFC_PIN_GROUP(vin0_sync),
|
||||
SH_PFC_PIN_GROUP(vin0_field),
|
||||
SH_PFC_PIN_GROUP(vin0_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin0_clk),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 8),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin1_data, 12),
|
||||
SH_PFC_PIN_GROUP(vin1_sync),
|
||||
SH_PFC_PIN_GROUP(vin1_field),
|
||||
SH_PFC_PIN_GROUP(vin1_clkenb),
|
||||
|
|
@ -2551,17 +2506,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
|||
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
#define F_(x, y) FN_##y
|
||||
#define FM(x) FN_##x
|
||||
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
|
||||
GROUP(-10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP0_31_22 RESERVED */
|
||||
GP_0_21_FN, GPSR0_21,
|
||||
GP_0_20_FN, GPSR0_20,
|
||||
GP_0_19_FN, GPSR0_19,
|
||||
|
|
@ -2653,22 +2602,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_2_1_FN, GPSR2_1,
|
||||
GP_2_0_FN, GPSR2_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
|
||||
GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP3_31_17 RESERVED */
|
||||
GP_3_16_FN, GPSR3_16,
|
||||
GP_3_15_FN, GPSR3_15,
|
||||
GP_3_14_FN, GPSR3_14,
|
||||
|
|
@ -2687,14 +2625,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_3_1_FN, GPSR3_1,
|
||||
GP_3_0_FN, GPSR3_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
|
||||
GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1),
|
||||
GROUP(
|
||||
/* GP4_31_25 RESERVED */
|
||||
GP_4_24_FN, GPSR4_24,
|
||||
GP_4_23_FN, GPSR4_23,
|
||||
GP_4_22_FN, GPSR4_22,
|
||||
|
|
@ -2721,24 +2657,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_4_1_FN, GPSR4_1,
|
||||
GP_4_0_FN, GPSR4_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
|
||||
GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP5_31_15 RESERVED */
|
||||
GP_5_14_FN, GPSR5_14,
|
||||
GP_5_13_FN, GPSR5_13,
|
||||
GP_5_12_FN, GPSR5_12,
|
||||
|
|
@ -2860,10 +2783,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
IP9_7_4
|
||||
IP9_3_0 ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
|
||||
IP10_31_28
|
||||
IP10_27_24
|
||||
IP10_23_20
|
||||
{ PINMUX_CFG_REG_VAR("IPSR10", 0xe6060228, 32,
|
||||
GROUP(-12, 4, 4, 4, 4, 4),
|
||||
GROUP(
|
||||
/* IP10_31_20 RESERVED */
|
||||
IP10_19_16
|
||||
IP10_15_12
|
||||
IP10_11_8
|
||||
|
|
@ -2876,19 +2799,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
#define F_(x, y) x,
|
||||
#define FM(x) FN_##x,
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
|
||||
GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1),
|
||||
GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, -1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* RESERVED 31, 30, 29, 28 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 27, 26, 25, 24 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 23, 22, 21, 20 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 19, 18, 17, 16 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 15, 14, 13, 12 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 31-12 */
|
||||
MOD_SEL0_11
|
||||
MOD_SEL0_10
|
||||
MOD_SEL0_9
|
||||
|
|
@ -2897,7 +2810,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL0_6
|
||||
MOD_SEL0_5
|
||||
MOD_SEL0_4
|
||||
0, 0,
|
||||
/* RESERVED 3 */
|
||||
MOD_SEL0_2
|
||||
MOD_SEL0_1
|
||||
MOD_SEL0_0 ))
|
||||
|
|
@ -2922,8 +2835,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
|||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
|
||||
u32 *pocctrl)
|
||||
static int r8a77980_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = pin & 0x1f;
|
||||
|
||||
|
|
@ -2947,13 +2859,189 @@ static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations pinmux_ops = {
|
||||
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
|
||||
[ 0] = RCAR_GP_PIN(0, 0), /* DU_DR2 */
|
||||
[ 1] = RCAR_GP_PIN(0, 1), /* DU_DR3 */
|
||||
[ 2] = RCAR_GP_PIN(0, 2), /* DU_DR4 */
|
||||
[ 3] = RCAR_GP_PIN(0, 3), /* DU_DR5 */
|
||||
[ 4] = RCAR_GP_PIN(0, 4), /* DU_DR6 */
|
||||
[ 5] = RCAR_GP_PIN(0, 5), /* DU_DR7 */
|
||||
[ 6] = RCAR_GP_PIN(0, 6), /* DU_DG2 */
|
||||
[ 7] = RCAR_GP_PIN(0, 7), /* DU_DG3 */
|
||||
[ 8] = RCAR_GP_PIN(0, 8), /* DU_DG4 */
|
||||
[ 9] = RCAR_GP_PIN(0, 9), /* DU_DG5 */
|
||||
[10] = RCAR_GP_PIN(0, 10), /* DU_DG6 */
|
||||
[11] = RCAR_GP_PIN(0, 11), /* DU_DG7 */
|
||||
[12] = RCAR_GP_PIN(0, 12), /* DU_DB2 */
|
||||
[13] = RCAR_GP_PIN(0, 13), /* DU_DB3 */
|
||||
[14] = RCAR_GP_PIN(0, 14), /* DU_DB4 */
|
||||
[15] = RCAR_GP_PIN(0, 15), /* DU_DB5 */
|
||||
[16] = RCAR_GP_PIN(0, 16), /* DU_DB6 */
|
||||
[17] = RCAR_GP_PIN(0, 17), /* DU_DB7 */
|
||||
[18] = RCAR_GP_PIN(0, 18), /* DU_DOTCLKOUT */
|
||||
[19] = RCAR_GP_PIN(0, 19), /* DU_EXHSYNC/DU_HSYNC */
|
||||
[20] = RCAR_GP_PIN(0, 20), /* DU_EXVSYNC/DU_VSYNC */
|
||||
[21] = RCAR_GP_PIN(0, 21), /* DU_EXODDF/DU_ODDF/DISP/CDE */
|
||||
[22] = SH_PFC_PIN_NONE,
|
||||
[23] = SH_PFC_PIN_NONE,
|
||||
[24] = PIN_DU_DOTCLKIN, /* DU_DOTCLKIN */
|
||||
[25] = SH_PFC_PIN_NONE,
|
||||
[26] = PIN_PRESETOUT_N, /* PRESETOUT# */
|
||||
[27] = SH_PFC_PIN_NONE,
|
||||
[28] = SH_PFC_PIN_NONE,
|
||||
[29] = SH_PFC_PIN_NONE,
|
||||
[30] = PIN_EXTALR, /* EXTALR */
|
||||
[31] = PIN_FSCLKST_N, /* FSCLKST# */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
|
||||
[ 0] = PIN_FSCLKST, /* FSCLKST */
|
||||
[ 1] = SH_PFC_PIN_NONE,
|
||||
[ 2] = RCAR_GP_PIN(1, 0), /* IRQ0 */
|
||||
[ 3] = PIN_DCUTRST_N, /* DCUTRST# */
|
||||
[ 4] = PIN_DCUTCK_LPDCLK, /* DCUTCK_LPDCLK */
|
||||
[ 5] = PIN_DCUTMS, /* DCUTMS */
|
||||
[ 6] = PIN_DCUTDI_LPDI, /* DCUTDI_LPDI */
|
||||
[ 7] = SH_PFC_PIN_NONE,
|
||||
[ 8] = RCAR_GP_PIN(2, 0), /* VI0_CLK */
|
||||
[ 9] = RCAR_GP_PIN(2, 1), /* VI0_CLKENB */
|
||||
[10] = RCAR_GP_PIN(2, 2), /* VI0_HSYNC# */
|
||||
[11] = RCAR_GP_PIN(2, 3), /* VI0_VSYNC# */
|
||||
[12] = RCAR_GP_PIN(2, 4), /* VI0_DATA0 */
|
||||
[13] = RCAR_GP_PIN(2, 5), /* VI0_DATA1 */
|
||||
[14] = RCAR_GP_PIN(2, 6), /* VI0_DATA2 */
|
||||
[15] = RCAR_GP_PIN(2, 7), /* VI0_DATA3 */
|
||||
[16] = RCAR_GP_PIN(2, 8), /* VI0_DATA4 */
|
||||
[17] = RCAR_GP_PIN(2, 9), /* VI0_DATA5 */
|
||||
[18] = RCAR_GP_PIN(2, 10), /* VI0_DATA6 */
|
||||
[19] = RCAR_GP_PIN(2, 11), /* VI0_DATA7 */
|
||||
[20] = RCAR_GP_PIN(2, 12), /* VI0_DATA8 */
|
||||
[21] = RCAR_GP_PIN(2, 13), /* VI0_DATA9 */
|
||||
[22] = RCAR_GP_PIN(2, 14), /* VI0_DATA10 */
|
||||
[23] = RCAR_GP_PIN(2, 15), /* VI0_DATA11 */
|
||||
[24] = RCAR_GP_PIN(2, 16), /* VI0_FIELD */
|
||||
[25] = RCAR_GP_PIN(3, 0), /* VI1_CLK */
|
||||
[26] = RCAR_GP_PIN(3, 1), /* VI1_CLKENB */
|
||||
[27] = RCAR_GP_PIN(3, 2), /* VI1_HSYNC# */
|
||||
[28] = RCAR_GP_PIN(3, 3), /* VI1_VSYNC# */
|
||||
[29] = RCAR_GP_PIN(3, 4), /* VI1_DATA0 */
|
||||
[30] = RCAR_GP_PIN(3, 5), /* VI1_DATA1 */
|
||||
[31] = RCAR_GP_PIN(3, 6), /* VI1_DATA2 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
|
||||
[ 0] = RCAR_GP_PIN(3, 7), /* VI1_DATA3 */
|
||||
[ 1] = RCAR_GP_PIN(3, 8), /* VI1_DATA4 */
|
||||
[ 2] = RCAR_GP_PIN(3, 9), /* VI1_DATA5 */
|
||||
[ 3] = RCAR_GP_PIN(3, 10), /* VI1_DATA6 */
|
||||
[ 4] = RCAR_GP_PIN(3, 11), /* VI1_DATA7 */
|
||||
[ 5] = RCAR_GP_PIN(3, 12), /* VI1_DATA8 */
|
||||
[ 6] = RCAR_GP_PIN(3, 13), /* VI1_DATA9 */
|
||||
[ 7] = RCAR_GP_PIN(3, 14), /* VI1_DATA10 */
|
||||
[ 8] = RCAR_GP_PIN(3, 15), /* VI1_DATA11 */
|
||||
[ 9] = RCAR_GP_PIN(3, 16), /* VI1_FIELD */
|
||||
[10] = RCAR_GP_PIN(4, 0), /* SCL0 */
|
||||
[11] = RCAR_GP_PIN(4, 1), /* SDA0 */
|
||||
[12] = RCAR_GP_PIN(4, 2), /* SCL1 */
|
||||
[13] = RCAR_GP_PIN(4, 3), /* SDA1 */
|
||||
[14] = RCAR_GP_PIN(4, 4), /* SCL2 */
|
||||
[15] = RCAR_GP_PIN(4, 5), /* SDA2 */
|
||||
[16] = RCAR_GP_PIN(1, 1), /* AVB_RX_CTL */
|
||||
[17] = RCAR_GP_PIN(1, 2), /* AVB_RXC */
|
||||
[18] = RCAR_GP_PIN(1, 3), /* AVB_RD0 */
|
||||
[19] = RCAR_GP_PIN(1, 4), /* AVB_RD1 */
|
||||
[20] = RCAR_GP_PIN(1, 5), /* AVB_RD2 */
|
||||
[21] = RCAR_GP_PIN(1, 6), /* AVB_RD3 */
|
||||
[22] = RCAR_GP_PIN(1, 7), /* AVB_TX_CTL */
|
||||
[23] = RCAR_GP_PIN(1, 8), /* AVB_TXC */
|
||||
[24] = RCAR_GP_PIN(1, 9), /* AVB_TD0 */
|
||||
[25] = RCAR_GP_PIN(1, 10), /* AVB_TD1 */
|
||||
[26] = RCAR_GP_PIN(1, 11), /* AVB_TD2 */
|
||||
[27] = RCAR_GP_PIN(1, 12), /* AVB_TD3 */
|
||||
[28] = RCAR_GP_PIN(1, 13), /* AVB_TXCREFCLK */
|
||||
[29] = RCAR_GP_PIN(1, 14), /* AVB_MDIO */
|
||||
[30] = RCAR_GP_PIN(1, 15), /* AVB_MDC */
|
||||
[31] = RCAR_GP_PIN(1, 16), /* AVB_MAGIC */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
|
||||
[ 0] = RCAR_GP_PIN(1, 17), /* AVB_PHY_INT */
|
||||
[ 1] = RCAR_GP_PIN(1, 18), /* AVB_LINK */
|
||||
[ 2] = RCAR_GP_PIN(1, 19), /* AVB_AVTP_MATCH */
|
||||
[ 3] = RCAR_GP_PIN(1, 20), /* AVTP_CAPTURE */
|
||||
[ 4] = RCAR_GP_PIN(4, 6), /* GETHER_RX_CTL */
|
||||
[ 5] = RCAR_GP_PIN(4, 7), /* GETHER_RXC */
|
||||
[ 6] = RCAR_GP_PIN(4, 8), /* GETHER_RD0 */
|
||||
[ 7] = RCAR_GP_PIN(4, 9), /* GETHER_RD1 */
|
||||
[ 8] = RCAR_GP_PIN(4, 10), /* GETHER_RD2 */
|
||||
[ 9] = RCAR_GP_PIN(4, 11), /* GETHER_RD3 */
|
||||
[10] = RCAR_GP_PIN(4, 12), /* GETHER_TX_CTL */
|
||||
[11] = RCAR_GP_PIN(4, 13), /* GETHER_TXC */
|
||||
[12] = RCAR_GP_PIN(4, 14), /* GETHER_TD0 */
|
||||
[13] = RCAR_GP_PIN(4, 15), /* GETHER_TD1 */
|
||||
[14] = RCAR_GP_PIN(4, 16), /* GETHER_TD2 */
|
||||
[15] = RCAR_GP_PIN(4, 17), /* GETHER_TD3 */
|
||||
[16] = RCAR_GP_PIN(4, 18), /* GETHER_TXCREFCLK */
|
||||
[17] = RCAR_GP_PIN(4, 19), /* GETHER_TXCREFCLK_MEGA */
|
||||
[18] = RCAR_GP_PIN(4, 20), /* GETHER_MDIO_A */
|
||||
[19] = RCAR_GP_PIN(4, 21), /* GETHER_MDC_A */
|
||||
[20] = RCAR_GP_PIN(4, 22), /* GETHER_MAGIC */
|
||||
[21] = RCAR_GP_PIN(4, 23), /* GETHER_PHY_INT_A */
|
||||
[22] = RCAR_GP_PIN(4, 24), /* GETHER_LINK_A */
|
||||
[23] = RCAR_GP_PIN(1, 21), /* CANFD0_TX_A */
|
||||
[24] = RCAR_GP_PIN(1, 22), /* CANFD0_RX_A */
|
||||
[25] = RCAR_GP_PIN(1, 23), /* CANFD1_TX */
|
||||
[26] = RCAR_GP_PIN(1, 24), /* CANFD1_RX */
|
||||
[27] = RCAR_GP_PIN(1, 25), /* CAN_CLK_A */
|
||||
[28] = RCAR_GP_PIN(5, 0), /* QSPI0_SPCLK */
|
||||
[29] = RCAR_GP_PIN(5, 1), /* QSPI0_MOSI_IO0 */
|
||||
[30] = RCAR_GP_PIN(5, 2), /* QSPI0_MISO_IO1 */
|
||||
[31] = RCAR_GP_PIN(5, 3), /* QSPI0_IO2 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
|
||||
[ 0] = RCAR_GP_PIN(5, 4), /* QSPI0_IO3 */
|
||||
[ 1] = RCAR_GP_PIN(5, 5), /* QSPI0_SSL */
|
||||
[ 2] = RCAR_GP_PIN(5, 6), /* QSPI1_SPCLK */
|
||||
[ 3] = RCAR_GP_PIN(5, 7), /* QSPI1_MOSI_IO0 */
|
||||
[ 4] = RCAR_GP_PIN(5, 8), /* QSPI1_MISO_IO1 */
|
||||
[ 5] = RCAR_GP_PIN(5, 9), /* QSPI1_IO2 */
|
||||
[ 6] = RCAR_GP_PIN(5, 10), /* QSPI1_IO3 */
|
||||
[ 7] = RCAR_GP_PIN(5, 11), /* QSPI1_SSL */
|
||||
[ 8] = RCAR_GP_PIN(5, 12), /* RPC_RESET# */
|
||||
[ 9] = RCAR_GP_PIN(5, 13), /* RPC_WP# */
|
||||
[10] = RCAR_GP_PIN(5, 14), /* RPC_INT# */
|
||||
[11] = RCAR_GP_PIN(1, 26), /* DIGRF_CLKIN */
|
||||
[12] = RCAR_GP_PIN(1, 27), /* DIGRF_CLKOUT */
|
||||
[13] = RCAR_GP_PIN(2, 17), /* IRQ4 */
|
||||
[14] = RCAR_GP_PIN(2, 18), /* IRQ5 */
|
||||
[15] = RCAR_GP_PIN(2, 25), /* SCL3 */
|
||||
[16] = RCAR_GP_PIN(2, 26), /* SDA3 */
|
||||
[17] = RCAR_GP_PIN(2, 19), /* MSIOF0_RXD */
|
||||
[18] = RCAR_GP_PIN(2, 20), /* MSIOF0_TXD */
|
||||
[19] = RCAR_GP_PIN(2, 21), /* MSIOF0_SCK */
|
||||
[20] = RCAR_GP_PIN(2, 22), /* MSIOF0_SYNC */
|
||||
[21] = RCAR_GP_PIN(2, 23), /* MSIOF0_SS1 */
|
||||
[22] = RCAR_GP_PIN(2, 24), /* MSIOF0_SS2 */
|
||||
[23] = RCAR_GP_PIN(2, 27), /* FSO_CFE_0# */
|
||||
[24] = RCAR_GP_PIN(2, 28), /* FSO_CFE_1# */
|
||||
[25] = RCAR_GP_PIN(2, 29), /* FSO_TOE# */
|
||||
[26] = SH_PFC_PIN_NONE,
|
||||
[27] = SH_PFC_PIN_NONE,
|
||||
[28] = SH_PFC_PIN_NONE,
|
||||
[29] = SH_PFC_PIN_NONE,
|
||||
[30] = SH_PFC_PIN_NONE,
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a77980_pfc_ops = {
|
||||
.pin_to_pocctrl = r8a77980_pin_to_pocctrl,
|
||||
.get_bias = rcar_pinmux_get_bias,
|
||||
.set_bias = rcar_pinmux_set_bias,
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info r8a77980_pinmux_info = {
|
||||
.name = "r8a77980_pfc",
|
||||
.ops = &pinmux_ops,
|
||||
.ops = &r8a77980_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
|
@ -2966,6 +3054,7 @@ const struct sh_pfc_soc_info r8a77980_pinmux_info = {
|
|||
.nr_functions = ARRAY_SIZE(pinmux_functions),
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.bias_regs = pinmux_bias_regs,
|
||||
.ioctrl_regs = pinmux_ioctrl_regs,
|
||||
|
||||
.pinmux_data = pinmux_data,
|
||||
|
|
|
|||
|
|
@ -26,12 +26,12 @@
|
|||
PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
|
|
@ -57,10 +57,10 @@
|
|||
PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(TCK, "TCK", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(TDI, "TDI", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
|
||||
PIN_NOGP_CFG(TRST_N, "TRST_N", fn, CFG_FLAGS)
|
||||
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP)
|
||||
|
||||
/*
|
||||
* F_() : just information
|
||||
|
|
@ -2343,6 +2343,16 @@ static const unsigned int intc_ex_irq5_mux[] = {
|
|||
IRQ5_MARK,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77990
|
||||
/* - MLB+ ------------------------------------------------------------------- */
|
||||
static const unsigned int mlb_3pin_pins[] = {
|
||||
RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
|
||||
};
|
||||
static const unsigned int mlb_3pin_mux[] = {
|
||||
MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
|
||||
};
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
|
||||
|
||||
/* - MSIOF0 ----------------------------------------------------------------- */
|
||||
static const unsigned int msiof0_clk_pins[] = {
|
||||
/* SCK */
|
||||
|
|
@ -2821,23 +2831,6 @@ static const unsigned int qspi0_ctrl_pins[] = {
|
|||
static const unsigned int qspi0_ctrl_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data2_pins[] = {
|
||||
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
|
||||
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
|
||||
};
|
||||
static const unsigned int qspi0_data2_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data4_pins[] = {
|
||||
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
|
||||
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
|
||||
/* QSPI0_IO2, QSPI0_IO3 */
|
||||
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
|
||||
};
|
||||
static const unsigned int qspi0_data4_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
|
||||
};
|
||||
/* - QSPI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int qspi1_ctrl_pins[] = {
|
||||
/* QSPI1_SPCLK, QSPI1_SSL */
|
||||
|
|
@ -2846,23 +2839,51 @@ static const unsigned int qspi1_ctrl_pins[] = {
|
|||
static const unsigned int qspi1_ctrl_mux[] = {
|
||||
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data2_pins[] = {
|
||||
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
|
||||
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
|
||||
|
||||
/* - RPC -------------------------------------------------------------------- */
|
||||
static const unsigned int rpc_clk_pins[] = {
|
||||
/* Octal-SPI flash: C/SCLK */
|
||||
/* HyperFlash: CK, CK# */
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 6),
|
||||
};
|
||||
static const unsigned int qspi1_data2_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
static const unsigned int rpc_clk_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data4_pins[] = {
|
||||
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
|
||||
static const unsigned int rpc_ctrl_pins[] = {
|
||||
/* Octal-SPI flash: S#/CS, DQS */
|
||||
/* HyperFlash: CS#, RDS */
|
||||
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 11),
|
||||
};
|
||||
static const unsigned int rpc_ctrl_mux[] = {
|
||||
QSPI0_SSL_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
static const unsigned int rpc_data_pins[] = {
|
||||
/* DQ[0:7] */
|
||||
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
|
||||
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
|
||||
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
|
||||
/* QSPI1_IO2, QSPI1_IO3 */
|
||||
RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
|
||||
};
|
||||
static const unsigned int qspi1_data4_mux[] = {
|
||||
static const unsigned int rpc_data_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
|
||||
};
|
||||
static const unsigned int rpc_reset_pins[] = {
|
||||
/* RPC_RESET# */
|
||||
RCAR_GP_PIN(2, 13),
|
||||
};
|
||||
static const unsigned int rpc_reset_mux[] = {
|
||||
RPC_RESET_N_MARK,
|
||||
};
|
||||
static const unsigned int rpc_int_pins[] = {
|
||||
/* RPC_INT# */
|
||||
RCAR_GP_PIN(2, 12),
|
||||
};
|
||||
static const unsigned int rpc_int_mux[] = {
|
||||
RPC_INT_N_MARK,
|
||||
};
|
||||
|
||||
/* - SCIF0 ------------------------------------------------------------------ */
|
||||
static const unsigned int scif0_data_a_pins[] = {
|
||||
|
|
@ -3142,22 +3163,13 @@ static const unsigned int scif_clk_b_mux[] = {
|
|||
};
|
||||
|
||||
/* - SDHI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi0_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(3, 2),
|
||||
};
|
||||
|
||||
static const unsigned int sdhi0_data1_mux[] = {
|
||||
SD0_DAT0_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int sdhi0_data4_pins[] = {
|
||||
static const unsigned int sdhi0_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
};
|
||||
|
||||
static const unsigned int sdhi0_data4_mux[] = {
|
||||
static const unsigned int sdhi0_data_mux[] = {
|
||||
SD0_DAT0_MARK, SD0_DAT1_MARK,
|
||||
SD0_DAT2_MARK, SD0_DAT3_MARK,
|
||||
};
|
||||
|
|
@ -3190,22 +3202,13 @@ static const unsigned int sdhi0_wp_mux[] = {
|
|||
};
|
||||
|
||||
/* - SDHI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi1_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(3, 8),
|
||||
};
|
||||
|
||||
static const unsigned int sdhi1_data1_mux[] = {
|
||||
SD1_DAT0_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int sdhi1_data4_pins[] = {
|
||||
static const unsigned int sdhi1_data_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
};
|
||||
|
||||
static const unsigned int sdhi1_data4_mux[] = {
|
||||
static const unsigned int sdhi1_data_mux[] = {
|
||||
SD1_DAT0_MARK, SD1_DAT1_MARK,
|
||||
SD1_DAT2_MARK, SD1_DAT3_MARK,
|
||||
};
|
||||
|
|
@ -3238,27 +3241,7 @@ static const unsigned int sdhi1_wp_mux[] = {
|
|||
};
|
||||
|
||||
/* - SDHI3 ------------------------------------------------------------------ */
|
||||
static const unsigned int sdhi3_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(4, 2),
|
||||
};
|
||||
|
||||
static const unsigned int sdhi3_data1_mux[] = {
|
||||
SD3_DAT0_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int sdhi3_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
|
||||
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
|
||||
};
|
||||
|
||||
static const unsigned int sdhi3_data4_mux[] = {
|
||||
SD3_DAT0_MARK, SD3_DAT1_MARK,
|
||||
SD3_DAT2_MARK, SD3_DAT3_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int sdhi3_data8_pins[] = {
|
||||
static const unsigned int sdhi3_data_pins[] = {
|
||||
/* D[0:7] */
|
||||
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
|
||||
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
|
||||
|
|
@ -3266,7 +3249,7 @@ static const unsigned int sdhi3_data8_pins[] = {
|
|||
RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
|
||||
};
|
||||
|
||||
static const unsigned int sdhi3_data8_mux[] = {
|
||||
static const unsigned int sdhi3_data_mux[] = {
|
||||
SD3_DAT0_MARK, SD3_DAT1_MARK,
|
||||
SD3_DAT2_MARK, SD3_DAT3_MARK,
|
||||
SD3_DAT4_MARK, SD3_DAT5_MARK,
|
||||
|
|
@ -3608,38 +3591,34 @@ static const unsigned int vin4_data18_a_mux[] = {
|
|||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
|
||||
static const union vin_data vin4_data_a_pins = {
|
||||
.data24 = {
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
|
||||
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
|
||||
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
|
||||
RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
|
||||
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
|
||||
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
|
||||
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
|
||||
RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
|
||||
},
|
||||
static const unsigned int vin4_data_a_pins[] = {
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
|
||||
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
|
||||
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
|
||||
RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
|
||||
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
|
||||
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
|
||||
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
|
||||
RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
|
||||
};
|
||||
|
||||
static const union vin_data vin4_data_a_mux = {
|
||||
.data24 = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
},
|
||||
static const unsigned int vin4_data_a_mux[] = {
|
||||
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
|
||||
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
|
||||
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
|
||||
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int vin4_data18_b_pins[] = {
|
||||
|
|
@ -3666,38 +3645,34 @@ static const unsigned int vin4_data18_b_mux[] = {
|
|||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
|
||||
static const union vin_data vin4_data_b_pins = {
|
||||
.data24 = {
|
||||
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
|
||||
RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
|
||||
RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
|
||||
RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
|
||||
RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
|
||||
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
|
||||
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
|
||||
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
|
||||
RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
|
||||
},
|
||||
static const unsigned int vin4_data_b_pins[] = {
|
||||
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
|
||||
RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
|
||||
RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
|
||||
RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
|
||||
RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
|
||||
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
|
||||
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
|
||||
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
|
||||
RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
|
||||
};
|
||||
|
||||
static const union vin_data vin4_data_b_mux = {
|
||||
.data24 = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
},
|
||||
static const unsigned int vin4_data_b_mux[] = {
|
||||
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
|
||||
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
|
||||
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
|
||||
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int vin4_sync_pins[] = {
|
||||
|
|
@ -3734,30 +3709,26 @@ static const unsigned int vin4_clk_mux[] = {
|
|||
};
|
||||
|
||||
/* - VIN5 ------------------------------------------------------------------- */
|
||||
static const union vin_data16 vin5_data_a_pins = {
|
||||
.data16 = {
|
||||
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
|
||||
RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12),
|
||||
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
|
||||
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
},
|
||||
static const unsigned int vin5_data_a_pins[] = {
|
||||
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
|
||||
RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12),
|
||||
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
|
||||
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11),
|
||||
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
};
|
||||
|
||||
static const union vin_data16 vin5_data_a_mux = {
|
||||
.data16 = {
|
||||
VI5_DATA0_A_MARK, VI5_DATA1_A_MARK,
|
||||
VI5_DATA2_A_MARK, VI5_DATA3_A_MARK,
|
||||
VI5_DATA4_A_MARK, VI5_DATA5_A_MARK,
|
||||
VI5_DATA6_A_MARK, VI5_DATA7_A_MARK,
|
||||
VI5_DATA8_A_MARK, VI5_DATA9_A_MARK,
|
||||
VI5_DATA10_A_MARK, VI5_DATA11_A_MARK,
|
||||
VI5_DATA12_A_MARK, VI5_DATA13_A_MARK,
|
||||
VI5_DATA14_A_MARK, VI5_DATA15_A_MARK,
|
||||
},
|
||||
static const unsigned int vin5_data_a_mux[] = {
|
||||
VI5_DATA0_A_MARK, VI5_DATA1_A_MARK,
|
||||
VI5_DATA2_A_MARK, VI5_DATA3_A_MARK,
|
||||
VI5_DATA4_A_MARK, VI5_DATA5_A_MARK,
|
||||
VI5_DATA6_A_MARK, VI5_DATA7_A_MARK,
|
||||
VI5_DATA8_A_MARK, VI5_DATA9_A_MARK,
|
||||
VI5_DATA10_A_MARK, VI5_DATA11_A_MARK,
|
||||
VI5_DATA12_A_MARK, VI5_DATA13_A_MARK,
|
||||
VI5_DATA14_A_MARK, VI5_DATA15_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int vin5_data8_b_pins[] = {
|
||||
|
|
@ -3816,9 +3787,9 @@ static const unsigned int vin5_clk_b_mux[] = {
|
|||
};
|
||||
|
||||
static const struct {
|
||||
struct sh_pfc_pin_group common[253];
|
||||
struct sh_pfc_pin_group common[261];
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77990
|
||||
struct sh_pfc_pin_group automotive[21];
|
||||
struct sh_pfc_pin_group automotive[22];
|
||||
#endif
|
||||
} pinmux_groups = {
|
||||
.common = {
|
||||
|
|
@ -3965,11 +3936,17 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(pwm6_a),
|
||||
SH_PFC_PIN_GROUP(pwm6_b),
|
||||
SH_PFC_PIN_GROUP(qspi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi0_data2),
|
||||
SH_PFC_PIN_GROUP(qspi0_data4),
|
||||
SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
|
||||
SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
|
||||
SH_PFC_PIN_GROUP(qspi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi1_data2),
|
||||
SH_PFC_PIN_GROUP(qspi1_data4),
|
||||
SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
|
||||
SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
|
||||
BUS_DATA_PIN_GROUP(rpc_clk, 1),
|
||||
BUS_DATA_PIN_GROUP(rpc_clk, 2),
|
||||
SH_PFC_PIN_GROUP(rpc_ctrl),
|
||||
SH_PFC_PIN_GROUP(rpc_data),
|
||||
SH_PFC_PIN_GROUP(rpc_reset),
|
||||
SH_PFC_PIN_GROUP(rpc_int),
|
||||
SH_PFC_PIN_GROUP(scif0_data_a),
|
||||
SH_PFC_PIN_GROUP(scif0_clk_a),
|
||||
SH_PFC_PIN_GROUP(scif0_ctrl_a),
|
||||
|
|
@ -4000,19 +3977,19 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(scif5_data_c),
|
||||
SH_PFC_PIN_GROUP(scif_clk_a),
|
||||
SH_PFC_PIN_GROUP(scif_clk_b),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi0_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi0_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi0_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi1_data4),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
|
||||
SH_PFC_PIN_GROUP(sdhi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi1_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi1_wp),
|
||||
SH_PFC_PIN_GROUP(sdhi3_data1),
|
||||
SH_PFC_PIN_GROUP(sdhi3_data4),
|
||||
SH_PFC_PIN_GROUP(sdhi3_data8),
|
||||
BUS_DATA_PIN_GROUP(sdhi3_data, 1),
|
||||
BUS_DATA_PIN_GROUP(sdhi3_data, 4),
|
||||
BUS_DATA_PIN_GROUP(sdhi3_data, 8),
|
||||
SH_PFC_PIN_GROUP(sdhi3_ctrl),
|
||||
SH_PFC_PIN_GROUP(sdhi3_cd),
|
||||
SH_PFC_PIN_GROUP(sdhi3_wp),
|
||||
|
|
@ -4047,29 +4024,31 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(usb0_id),
|
||||
SH_PFC_PIN_GROUP(usb30),
|
||||
SH_PFC_PIN_GROUP(usb30_id),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
|
||||
SH_PFC_PIN_GROUP(vin4_data18_a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
|
||||
SH_PFC_PIN_GROUP(vin4_data18_b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
|
||||
SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
|
||||
SH_PFC_PIN_GROUP(vin4_sync),
|
||||
SH_PFC_PIN_GROUP(vin4_field),
|
||||
SH_PFC_PIN_GROUP(vin4_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin4_clk),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 8, _a),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 10, _a),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 12, _a),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 16, _a),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 8, _a),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 10, _a),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 12, _a),
|
||||
BUS_DATA_PIN_GROUP(vin5_data, 16, _a),
|
||||
SH_PFC_PIN_GROUP(vin5_data8_b),
|
||||
SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data_a, 8, 8),
|
||||
SH_PFC_PIN_GROUP(vin5_sync_a),
|
||||
SH_PFC_PIN_GROUP(vin5_field_a),
|
||||
SH_PFC_PIN_GROUP(vin5_clkenb_a),
|
||||
|
|
@ -4099,6 +4078,7 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(drif3_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(drif3_data0_b),
|
||||
SH_PFC_PIN_GROUP(drif3_data1_b),
|
||||
SH_PFC_PIN_GROUP(mlb_3pin),
|
||||
}
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
|
||||
};
|
||||
|
|
@ -4289,6 +4269,12 @@ static const char * const intc_ex_groups[] = {
|
|||
"intc_ex_irq5",
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77990
|
||||
static const char * const mlb_3pin_groups[] = {
|
||||
"mlb_3pin",
|
||||
};
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
|
||||
|
||||
static const char * const msiof0_groups[] = {
|
||||
"msiof0_clk",
|
||||
"msiof0_sync",
|
||||
|
|
@ -4385,6 +4371,15 @@ static const char * const qspi1_groups[] = {
|
|||
"qspi1_data4",
|
||||
};
|
||||
|
||||
static const char * const rpc_groups[] = {
|
||||
"rpc_clk1",
|
||||
"rpc_clk2",
|
||||
"rpc_ctrl",
|
||||
"rpc_data",
|
||||
"rpc_reset",
|
||||
"rpc_int",
|
||||
};
|
||||
|
||||
static const char * const scif0_groups[] = {
|
||||
"scif0_data_a",
|
||||
"scif0_clk_a",
|
||||
|
|
@ -4519,6 +4514,7 @@ static const char * const vin4_groups[] = {
|
|||
"vin4_data18_b",
|
||||
"vin4_data20_b",
|
||||
"vin4_data24_b",
|
||||
"vin4_g8",
|
||||
"vin4_sync",
|
||||
"vin4_field",
|
||||
"vin4_clkenb",
|
||||
|
|
@ -4531,6 +4527,7 @@ static const char * const vin5_groups[] = {
|
|||
"vin5_data12_a",
|
||||
"vin5_data16_a",
|
||||
"vin5_data8_b",
|
||||
"vin5_high8",
|
||||
"vin5_sync_a",
|
||||
"vin5_field_a",
|
||||
"vin5_clkenb_a",
|
||||
|
|
@ -4539,9 +4536,9 @@ static const char * const vin5_groups[] = {
|
|||
};
|
||||
|
||||
static const struct {
|
||||
struct sh_pfc_function common[49];
|
||||
struct sh_pfc_function common[50];
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77990
|
||||
struct sh_pfc_function automotive[4];
|
||||
struct sh_pfc_function automotive[5];
|
||||
#endif
|
||||
} pinmux_functions = {
|
||||
.common = {
|
||||
|
|
@ -4578,6 +4575,7 @@ static const struct {
|
|||
SH_PFC_FUNCTION(pwm6),
|
||||
SH_PFC_FUNCTION(qspi0),
|
||||
SH_PFC_FUNCTION(qspi1),
|
||||
SH_PFC_FUNCTION(rpc),
|
||||
SH_PFC_FUNCTION(scif0),
|
||||
SH_PFC_FUNCTION(scif1),
|
||||
SH_PFC_FUNCTION(scif2),
|
||||
|
|
@ -4601,6 +4599,7 @@ static const struct {
|
|||
SH_PFC_FUNCTION(drif1),
|
||||
SH_PFC_FUNCTION(drif2),
|
||||
SH_PFC_FUNCTION(drif3),
|
||||
SH_PFC_FUNCTION(mlb_3pin),
|
||||
}
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
|
||||
};
|
||||
|
|
@ -4608,21 +4607,11 @@ static const struct {
|
|||
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
#define F_(x, y) FN_##y
|
||||
#define FM(x) FN_##x
|
||||
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
|
||||
GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP0_31_18 RESERVED */
|
||||
GP_0_17_FN, GPSR0_17,
|
||||
GP_0_16_FN, GPSR0_16,
|
||||
GP_0_15_FN, GPSR0_15,
|
||||
|
|
@ -4642,16 +4631,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_0_1_FN, GPSR0_1,
|
||||
GP_0_0_FN, GPSR0_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR1", 0xe6060104, 32,
|
||||
GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP1_31_23 RESERVED */
|
||||
GP_1_22_FN, GPSR1_22,
|
||||
GP_1_21_FN, GPSR1_21,
|
||||
GP_1_20_FN, GPSR1_20,
|
||||
|
|
@ -4710,23 +4694,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_2_1_FN, GPSR2_1,
|
||||
GP_2_0_FN, GPSR2_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
|
||||
GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP3_31_16 RESERVED */
|
||||
GP_3_15_FN, GPSR3_15,
|
||||
GP_3_14_FN, GPSR3_14,
|
||||
GP_3_13_FN, GPSR3_13,
|
||||
|
|
@ -4744,28 +4716,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_3_1_FN, GPSR3_1,
|
||||
GP_3_0_FN, GPSR3_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
|
||||
GROUP(-21, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP4_31_11 RESERVED */
|
||||
GP_4_10_FN, GPSR4_10,
|
||||
GP_4_9_FN, GPSR4_9,
|
||||
GP_4_8_FN, GPSR4_8,
|
||||
|
|
@ -4778,19 +4732,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_4_1_FN, GPSR4_1,
|
||||
GP_4_0_FN, GPSR4_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
|
||||
GROUP(-12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP5_31_20 RESERVED */
|
||||
GP_5_19_FN, GPSR5_19,
|
||||
GP_5_18_FN, GPSR5_18,
|
||||
GP_5_17_FN, GPSR5_17,
|
||||
|
|
@ -4812,21 +4758,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_5_1_FN, GPSR5_1,
|
||||
GP_5_0_FN, GPSR5_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR6", 0xe6060118, 32,
|
||||
GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP6_31_18 RESERVED */
|
||||
GP_6_17_FN, GPSR6_17,
|
||||
GP_6_16_FN, GPSR6_16,
|
||||
GP_6_15_FN, GPSR6_15,
|
||||
|
|
@ -5017,11 +4953,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
#define F_(x, y) x,
|
||||
#define FM(x) FN_##x,
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
|
||||
GROUP(1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1,
|
||||
GROUP(-1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1,
|
||||
1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2),
|
||||
GROUP(
|
||||
/* RESERVED 31 */
|
||||
0, 0,
|
||||
MOD_SEL0_30_29
|
||||
MOD_SEL0_28
|
||||
MOD_SEL0_27_26
|
||||
|
|
@ -5046,15 +4981,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL0_1_0 ))
|
||||
},
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
|
||||
GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
|
||||
1, 2, 2, 2, 1, 1, 2, 1, 4),
|
||||
GROUP(1, 1, 1, 1, -1, 1, 1, 3, 3, 1, 1, 1,
|
||||
1, 2, 2, 2, 1, 1, 2, 1, -4),
|
||||
GROUP(
|
||||
MOD_SEL1_31
|
||||
MOD_SEL1_30
|
||||
MOD_SEL1_29
|
||||
MOD_SEL1_28
|
||||
/* RESERVED 27 */
|
||||
0, 0,
|
||||
MOD_SEL1_26
|
||||
MOD_SEL1_25
|
||||
MOD_SEL1_24_23_22
|
||||
|
|
@ -5070,12 +5004,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL1_7
|
||||
MOD_SEL1_6_5
|
||||
MOD_SEL1_4
|
||||
/* RESERVED 3, 2, 1, 0 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
|
||||
/* RESERVED 3, 2, 1, 0 */ ))
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
|
||||
{ RCAR_GP_PIN(3, 0), 18, 2 }, /* SD0_CLK */
|
||||
{ RCAR_GP_PIN(3, 1), 15, 2 }, /* SD0_CMD */
|
||||
{ RCAR_GP_PIN(3, 2), 12, 2 }, /* SD0_DAT0 */
|
||||
{ RCAR_GP_PIN(3, 3), 9, 2 }, /* SD0_DAT1 */
|
||||
{ RCAR_GP_PIN(3, 4), 6, 2 }, /* SD0_DAT2 */
|
||||
{ RCAR_GP_PIN(3, 5), 3, 2 }, /* SD0_DAT3 */
|
||||
{ RCAR_GP_PIN(3, 6), 0, 2 }, /* SD1_CLK */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
|
||||
{ RCAR_GP_PIN(3, 7), 29, 2 }, /* SD1_CMD */
|
||||
{ RCAR_GP_PIN(3, 8), 26, 2 }, /* SD1_DAT0 */
|
||||
{ RCAR_GP_PIN(3, 9), 23, 2 }, /* SD1_DAT1 */
|
||||
{ RCAR_GP_PIN(3, 10), 20, 2 }, /* SD1_DAT2 */
|
||||
{ RCAR_GP_PIN(3, 11), 17, 2 }, /* SD1_DAT3 */
|
||||
{ RCAR_GP_PIN(4, 0), 14, 2 }, /* SD3_CLK */
|
||||
{ RCAR_GP_PIN(4, 1), 11, 2 }, /* SD3_CMD */
|
||||
{ RCAR_GP_PIN(4, 2), 8, 2 }, /* SD3_DAT0 */
|
||||
{ RCAR_GP_PIN(4, 3), 5, 2 }, /* SD3_DAT1 */
|
||||
{ RCAR_GP_PIN(4, 4), 2, 2 }, /* SD3_DAT2 */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
|
||||
{ RCAR_GP_PIN(4, 5), 29, 2 }, /* SD3_DAT3 */
|
||||
{ RCAR_GP_PIN(4, 6), 26, 2 }, /* SD3_DAT4 */
|
||||
{ RCAR_GP_PIN(4, 7), 23, 2 }, /* SD3_DAT5 */
|
||||
{ RCAR_GP_PIN(4, 8), 20, 2 }, /* SD3_DAT6 */
|
||||
{ RCAR_GP_PIN(4, 9), 17, 2 }, /* SD3_DAT7 */
|
||||
{ RCAR_GP_PIN(4, 10), 14, 2 }, /* SD3_DS */
|
||||
} },
|
||||
{ },
|
||||
};
|
||||
|
||||
enum ioctrl_regs {
|
||||
POCCTRL0,
|
||||
TDSELCTRL,
|
||||
|
|
@ -5087,8 +5053,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
|||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
|
||||
u32 *pocctrl)
|
||||
static int r8a77990_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = -EINVAL;
|
||||
|
||||
|
|
@ -5169,8 +5134,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[27] = RCAR_GP_PIN(1, 0), /* A0 */
|
||||
[28] = SH_PFC_PIN_NONE,
|
||||
[29] = SH_PFC_PIN_NONE,
|
||||
[30] = RCAR_GP_PIN(2, 25), /* PUEN_EX_WAIT0 */
|
||||
[31] = RCAR_GP_PIN(2, 24), /* PUEN_RD/WR# */
|
||||
[30] = RCAR_GP_PIN(2, 25), /* EX_WAIT0 */
|
||||
[31] = RCAR_GP_PIN(2, 24), /* RD/WR# */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
|
||||
[0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
|
||||
|
|
@ -5305,63 +5270,22 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[27] = SH_PFC_PIN_NONE,
|
||||
[28] = SH_PFC_PIN_NONE,
|
||||
[29] = SH_PFC_PIN_NONE,
|
||||
[30] = RCAR_GP_PIN(6, 9), /* PUEN_USB30_OVC */
|
||||
[31] = RCAR_GP_PIN(6, 17), /* PUEN_USB30_PWEN */
|
||||
[30] = RCAR_GP_PIN(6, 9), /* USB30_OVC */
|
||||
[31] = RCAR_GP_PIN(6, 17), /* USB30_PWEN */
|
||||
} },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc,
|
||||
unsigned int pin)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
unsigned int bit;
|
||||
|
||||
reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
|
||||
if (!reg)
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
|
||||
if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
|
||||
return PIN_CONFIG_BIAS_PULL_UP;
|
||||
else
|
||||
return PIN_CONFIG_BIAS_PULL_DOWN;
|
||||
}
|
||||
|
||||
static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
u32 enable, updown;
|
||||
unsigned int bit;
|
||||
|
||||
reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
|
||||
if (!reg)
|
||||
return;
|
||||
|
||||
enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
|
||||
if (bias != PIN_CONFIG_BIAS_DISABLE)
|
||||
enable |= BIT(bit);
|
||||
|
||||
updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
|
||||
if (bias == PIN_CONFIG_BIAS_PULL_UP)
|
||||
updown |= BIT(bit);
|
||||
|
||||
sh_pfc_write(pfc, reg->pud, updown);
|
||||
sh_pfc_write(pfc, reg->puen, enable);
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = {
|
||||
static const struct sh_pfc_soc_operations r8a77990_pfc_ops = {
|
||||
.pin_to_pocctrl = r8a77990_pin_to_pocctrl,
|
||||
.get_bias = r8a77990_pinmux_get_bias,
|
||||
.set_bias = r8a77990_pinmux_set_bias,
|
||||
.get_bias = rcar_pinmux_get_bias,
|
||||
.set_bias = rcar_pinmux_set_bias,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A774C0
|
||||
const struct sh_pfc_soc_info r8a774c0_pinmux_info = {
|
||||
.name = "r8a774c0_pfc",
|
||||
.ops = &r8a77990_pinmux_ops,
|
||||
.ops = &r8a77990_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
|
@ -5374,6 +5298,7 @@ const struct sh_pfc_soc_info r8a774c0_pinmux_info = {
|
|||
.nr_functions = ARRAY_SIZE(pinmux_functions.common),
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.drive_regs = pinmux_drive_regs,
|
||||
.bias_regs = pinmux_bias_regs,
|
||||
.ioctrl_regs = pinmux_ioctrl_regs,
|
||||
|
||||
|
|
@ -5385,7 +5310,7 @@ const struct sh_pfc_soc_info r8a774c0_pinmux_info = {
|
|||
#ifdef CONFIG_PINCTRL_PFC_R8A77990
|
||||
const struct sh_pfc_soc_info r8a77990_pinmux_info = {
|
||||
.name = "r8a77990_pfc",
|
||||
.ops = &r8a77990_pinmux_ops,
|
||||
.ops = &r8a77990_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
|
@ -5400,6 +5325,7 @@ const struct sh_pfc_soc_info r8a77990_pinmux_info = {
|
|||
ARRAY_SIZE(pinmux_functions.automotive),
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.drive_regs = pinmux_drive_regs,
|
||||
.bias_regs = pinmux_bias_regs,
|
||||
.ioctrl_regs = pinmux_ioctrl_regs,
|
||||
|
||||
|
|
|
|||
|
|
@ -19,14 +19,24 @@
|
|||
|
||||
#include "sh_pfc.h"
|
||||
|
||||
#define CPU_ALL_GP(fn, sfx) \
|
||||
PORT_GP_9(0, fn, sfx), \
|
||||
PORT_GP_32(1, fn, sfx), \
|
||||
PORT_GP_32(2, fn, sfx), \
|
||||
PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_32(4, fn, sfx), \
|
||||
PORT_GP_21(5, fn, sfx), \
|
||||
PORT_GP_14(6, fn, sfx)
|
||||
#define CPU_ALL_GP(fn, sfx) \
|
||||
PORT_GP_CFG_9(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_21(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_14(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
|
||||
|
||||
#define CPU_ALL_NOGP(fn) \
|
||||
PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
|
||||
PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
|
||||
|
||||
/*
|
||||
* F_() : just information
|
||||
|
|
@ -933,8 +943,17 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A),
|
||||
};
|
||||
|
||||
/*
|
||||
* Pins not associated with a GPIO port.
|
||||
*/
|
||||
enum {
|
||||
GP_ASSIGN_LAST(),
|
||||
NOGP_ALL(),
|
||||
};
|
||||
|
||||
static const struct sh_pfc_pin pinmux_pins[] = {
|
||||
PINMUX_GPIO_GP_ALL(),
|
||||
PINMUX_NOGP_ALL(),
|
||||
};
|
||||
|
||||
/* - AUDIO CLOCK ------------------------------------------------------------- */
|
||||
|
|
@ -1240,31 +1259,23 @@ static const unsigned int i2c3_b_mux[] = {
|
|||
SCL3_B_MARK, SDA3_B_MARK,
|
||||
};
|
||||
|
||||
/* - MLB+ ------------------------------------------------------------------- */
|
||||
static const unsigned int mlb_3pin_pins[] = {
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7),
|
||||
};
|
||||
static const unsigned int mlb_3pin_mux[] = {
|
||||
MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
|
||||
};
|
||||
|
||||
/* - MMC ------------------------------------------------------------------- */
|
||||
static const unsigned int mmc_data1_pins[] = {
|
||||
/* D0 */
|
||||
RCAR_GP_PIN(3, 2),
|
||||
};
|
||||
static const unsigned int mmc_data1_mux[] = {
|
||||
MMC_D0_MARK,
|
||||
};
|
||||
static const unsigned int mmc_data4_pins[] = {
|
||||
/* D[0:3] */
|
||||
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
};
|
||||
static const unsigned int mmc_data4_mux[] = {
|
||||
MMC_D0_MARK, MMC_D1_MARK,
|
||||
MMC_D2_MARK, MMC_D3_MARK,
|
||||
};
|
||||
static const unsigned int mmc_data8_pins[] = {
|
||||
static const unsigned int mmc_data_pins[] = {
|
||||
/* D[0:7] */
|
||||
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
};
|
||||
static const unsigned int mmc_data8_mux[] = {
|
||||
static const unsigned int mmc_data_mux[] = {
|
||||
MMC_D0_MARK, MMC_D1_MARK,
|
||||
MMC_D2_MARK, MMC_D3_MARK,
|
||||
MMC_D4_MARK, MMC_D5_MARK,
|
||||
|
|
@ -1673,6 +1684,68 @@ static const unsigned int pwm3_c_mux[] = {
|
|||
PWM3_C_MARK,
|
||||
};
|
||||
|
||||
/* - QSPI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int qspi0_ctrl_pins[] = {
|
||||
/* QSPI0_SPCLK, QSPI0_SSL */
|
||||
RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
|
||||
};
|
||||
static const unsigned int qspi0_ctrl_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
|
||||
};
|
||||
/* - QSPI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int qspi1_ctrl_pins[] = {
|
||||
/* QSPI1_SPCLK, QSPI1_SSL */
|
||||
RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 11),
|
||||
};
|
||||
static const unsigned int qspi1_ctrl_mux[] = {
|
||||
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
|
||||
/* - RPC -------------------------------------------------------------------- */
|
||||
static const unsigned int rpc_clk_pins[] = {
|
||||
/* Octal-SPI flash: C/SCLK */
|
||||
/* HyperFlash: CK, CK# */
|
||||
RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 6),
|
||||
};
|
||||
static const unsigned int rpc_clk_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
|
||||
};
|
||||
static const unsigned int rpc_ctrl_pins[] = {
|
||||
/* Octal-SPI flash: S#/CS, DQS */
|
||||
/* HyperFlash: CS#, RDS */
|
||||
RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 11),
|
||||
};
|
||||
static const unsigned int rpc_ctrl_mux[] = {
|
||||
QSPI0_SSL_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
static const unsigned int rpc_data_pins[] = {
|
||||
/* DQ[0:7] */
|
||||
RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
|
||||
RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
|
||||
RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 8),
|
||||
RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 10),
|
||||
};
|
||||
static const unsigned int rpc_data_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
|
||||
};
|
||||
static const unsigned int rpc_reset_pins[] = {
|
||||
/* RPC_RESET# */
|
||||
RCAR_GP_PIN(6, 12),
|
||||
};
|
||||
static const unsigned int rpc_reset_mux[] = {
|
||||
RPC_RESET_N_MARK,
|
||||
};
|
||||
static const unsigned int rpc_int_pins[] = {
|
||||
/* RPC_INT# */
|
||||
RCAR_GP_PIN(6, 13),
|
||||
};
|
||||
static const unsigned int rpc_int_mux[] = {
|
||||
RPC_INT_N_MARK,
|
||||
};
|
||||
|
||||
/* - SCIF0 ------------------------------------------------------------------ */
|
||||
static const unsigned int scif0_data_a_pins[] = {
|
||||
/* RX, TX */
|
||||
|
|
@ -1933,37 +2006,33 @@ static const unsigned int vin4_data18_mux[] = {
|
|||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
static const union vin_data vin4_data_pins = {
|
||||
.data24 = {
|
||||
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
|
||||
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
|
||||
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
|
||||
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
|
||||
RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
|
||||
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
|
||||
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
|
||||
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
|
||||
RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
|
||||
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
|
||||
RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
|
||||
RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
|
||||
},
|
||||
static const unsigned int vin4_data_pins[] = {
|
||||
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
|
||||
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
|
||||
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
|
||||
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
|
||||
RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
|
||||
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
|
||||
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
|
||||
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
|
||||
RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
|
||||
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
|
||||
RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
|
||||
RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
|
||||
};
|
||||
static const union vin_data vin4_data_mux = {
|
||||
.data24 = {
|
||||
VI4_DATA0_MARK, VI4_DATA1_MARK,
|
||||
VI4_DATA2_MARK, VI4_DATA3_MARK,
|
||||
VI4_DATA4_MARK, VI4_DATA5_MARK,
|
||||
VI4_DATA6_MARK, VI4_DATA7_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
},
|
||||
static const unsigned int vin4_data_mux[] = {
|
||||
VI4_DATA0_MARK, VI4_DATA1_MARK,
|
||||
VI4_DATA2_MARK, VI4_DATA3_MARK,
|
||||
VI4_DATA4_MARK, VI4_DATA5_MARK,
|
||||
VI4_DATA6_MARK, VI4_DATA7_MARK,
|
||||
VI4_DATA8_MARK, VI4_DATA9_MARK,
|
||||
VI4_DATA10_MARK, VI4_DATA11_MARK,
|
||||
VI4_DATA12_MARK, VI4_DATA13_MARK,
|
||||
VI4_DATA14_MARK, VI4_DATA15_MARK,
|
||||
VI4_DATA16_MARK, VI4_DATA17_MARK,
|
||||
VI4_DATA18_MARK, VI4_DATA19_MARK,
|
||||
VI4_DATA20_MARK, VI4_DATA21_MARK,
|
||||
VI4_DATA22_MARK, VI4_DATA23_MARK,
|
||||
};
|
||||
static const unsigned int vin4_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
|
|
@ -2032,9 +2101,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(i2c2_b),
|
||||
SH_PFC_PIN_GROUP(i2c3_a),
|
||||
SH_PFC_PIN_GROUP(i2c3_b),
|
||||
SH_PFC_PIN_GROUP(mmc_data1),
|
||||
SH_PFC_PIN_GROUP(mmc_data4),
|
||||
SH_PFC_PIN_GROUP(mmc_data8),
|
||||
SH_PFC_PIN_GROUP(mlb_3pin),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 1),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 4),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 8),
|
||||
SH_PFC_PIN_GROUP(mmc_ctrl),
|
||||
SH_PFC_PIN_GROUP(msiof0_clk),
|
||||
SH_PFC_PIN_GROUP(msiof0_sync),
|
||||
|
|
@ -2079,6 +2149,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(pwm3_a),
|
||||
SH_PFC_PIN_GROUP(pwm3_b),
|
||||
SH_PFC_PIN_GROUP(pwm3_c),
|
||||
SH_PFC_PIN_GROUP(qspi0_ctrl),
|
||||
SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
|
||||
SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
|
||||
SH_PFC_PIN_GROUP(qspi1_ctrl),
|
||||
SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
|
||||
SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
|
||||
BUS_DATA_PIN_GROUP(rpc_clk, 1),
|
||||
BUS_DATA_PIN_GROUP(rpc_clk, 2),
|
||||
SH_PFC_PIN_GROUP(rpc_ctrl),
|
||||
SH_PFC_PIN_GROUP(rpc_data),
|
||||
SH_PFC_PIN_GROUP(rpc_reset),
|
||||
SH_PFC_PIN_GROUP(rpc_int),
|
||||
SH_PFC_PIN_GROUP(scif0_data_a),
|
||||
SH_PFC_PIN_GROUP(scif0_clk_a),
|
||||
SH_PFC_PIN_GROUP(scif0_data_b),
|
||||
|
|
@ -2111,13 +2193,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(ssi4_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(ssi4_data_b),
|
||||
SH_PFC_PIN_GROUP(usb0),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 8),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 16),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 8),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 10),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 12),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 16),
|
||||
SH_PFC_PIN_GROUP(vin4_data18),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 20),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 24),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 20),
|
||||
BUS_DATA_PIN_GROUP(vin4_data, 24),
|
||||
SH_PFC_PIN_GROUP(vin4_sync),
|
||||
SH_PFC_PIN_GROUP(vin4_field),
|
||||
SH_PFC_PIN_GROUP(vin4_clkenb),
|
||||
|
|
@ -2193,6 +2275,10 @@ static const char * const i2c3_groups[] = {
|
|||
"i2c3_b",
|
||||
};
|
||||
|
||||
static const char * const mlb_3pin_groups[] = {
|
||||
"mlb_3pin",
|
||||
};
|
||||
|
||||
static const char * const mmc_groups[] = {
|
||||
"mmc_data1",
|
||||
"mmc_data4",
|
||||
|
|
@ -2200,6 +2286,49 @@ static const char * const mmc_groups[] = {
|
|||
"mmc_ctrl",
|
||||
};
|
||||
|
||||
static const char * const msiof0_groups[] = {
|
||||
"msiof0_clk",
|
||||
"msiof0_sync",
|
||||
"msiof0_ss1",
|
||||
"msiof0_ss2",
|
||||
"msiof0_txd",
|
||||
"msiof0_rxd",
|
||||
};
|
||||
|
||||
static const char * const msiof1_groups[] = {
|
||||
"msiof1_clk",
|
||||
"msiof1_sync",
|
||||
"msiof1_ss1",
|
||||
"msiof1_ss2",
|
||||
"msiof1_txd",
|
||||
"msiof1_rxd",
|
||||
};
|
||||
|
||||
static const char * const msiof2_groups[] = {
|
||||
"msiof2_clk",
|
||||
"msiof2_sync_a",
|
||||
"msiof2_sync_b",
|
||||
"msiof2_ss1",
|
||||
"msiof2_ss2",
|
||||
"msiof2_txd",
|
||||
"msiof2_rxd",
|
||||
};
|
||||
|
||||
static const char * const msiof3_groups[] = {
|
||||
"msiof3_clk_a",
|
||||
"msiof3_sync_a",
|
||||
"msiof3_ss1_a",
|
||||
"msiof3_ss2_a",
|
||||
"msiof3_txd_a",
|
||||
"msiof3_rxd_a",
|
||||
"msiof3_clk_b",
|
||||
"msiof3_sync_b",
|
||||
"msiof3_ss1_b",
|
||||
"msiof3_ss2_b",
|
||||
"msiof3_txd_b",
|
||||
"msiof3_rxd_b",
|
||||
};
|
||||
|
||||
static const char * const pwm0_groups[] = {
|
||||
"pwm0_a",
|
||||
"pwm0_b",
|
||||
|
|
@ -2224,6 +2353,27 @@ static const char * const pwm3_groups[] = {
|
|||
"pwm3_c",
|
||||
};
|
||||
|
||||
static const char * const qspi0_groups[] = {
|
||||
"qspi0_ctrl",
|
||||
"qspi0_data2",
|
||||
"qspi0_data4",
|
||||
};
|
||||
|
||||
static const char * const qspi1_groups[] = {
|
||||
"qspi1_ctrl",
|
||||
"qspi1_data2",
|
||||
"qspi1_data4",
|
||||
};
|
||||
|
||||
static const char * const rpc_groups[] = {
|
||||
"rpc_clk1",
|
||||
"rpc_clk2",
|
||||
"rpc_ctrl",
|
||||
"rpc_data",
|
||||
"rpc_reset",
|
||||
"rpc_int",
|
||||
};
|
||||
|
||||
static const char * const scif0_groups[] = {
|
||||
"scif0_data_a",
|
||||
"scif0_clk_a",
|
||||
|
|
@ -2297,49 +2447,6 @@ static const char * const vin4_groups[] = {
|
|||
"vin4_clk",
|
||||
};
|
||||
|
||||
static const char * const msiof0_groups[] = {
|
||||
"msiof0_clk",
|
||||
"msiof0_sync",
|
||||
"msiof0_ss1",
|
||||
"msiof0_ss2",
|
||||
"msiof0_txd",
|
||||
"msiof0_rxd",
|
||||
};
|
||||
|
||||
static const char * const msiof1_groups[] = {
|
||||
"msiof1_clk",
|
||||
"msiof1_sync",
|
||||
"msiof1_ss1",
|
||||
"msiof1_ss2",
|
||||
"msiof1_txd",
|
||||
"msiof1_rxd",
|
||||
};
|
||||
|
||||
static const char * const msiof2_groups[] = {
|
||||
"msiof2_clk",
|
||||
"msiof2_sync_a",
|
||||
"msiof2_sync_b",
|
||||
"msiof2_ss1",
|
||||
"msiof2_ss2",
|
||||
"msiof2_txd",
|
||||
"msiof2_rxd",
|
||||
};
|
||||
|
||||
static const char * const msiof3_groups[] = {
|
||||
"msiof3_clk_a",
|
||||
"msiof3_sync_a",
|
||||
"msiof3_ss1_a",
|
||||
"msiof3_ss2_a",
|
||||
"msiof3_txd_a",
|
||||
"msiof3_rxd_a",
|
||||
"msiof3_clk_b",
|
||||
"msiof3_sync_b",
|
||||
"msiof3_ss1_b",
|
||||
"msiof3_ss2_b",
|
||||
"msiof3_txd_b",
|
||||
"msiof3_rxd_b",
|
||||
};
|
||||
|
||||
static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(audio_clk),
|
||||
SH_PFC_FUNCTION(avb0),
|
||||
|
|
@ -2353,6 +2460,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
|||
SH_PFC_FUNCTION(i2c1),
|
||||
SH_PFC_FUNCTION(i2c2),
|
||||
SH_PFC_FUNCTION(i2c3),
|
||||
SH_PFC_FUNCTION(mlb_3pin),
|
||||
SH_PFC_FUNCTION(mmc),
|
||||
SH_PFC_FUNCTION(msiof0),
|
||||
SH_PFC_FUNCTION(msiof1),
|
||||
|
|
@ -2362,6 +2470,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
|||
SH_PFC_FUNCTION(pwm1),
|
||||
SH_PFC_FUNCTION(pwm2),
|
||||
SH_PFC_FUNCTION(pwm3),
|
||||
SH_PFC_FUNCTION(qspi0),
|
||||
SH_PFC_FUNCTION(qspi1),
|
||||
SH_PFC_FUNCTION(rpc),
|
||||
SH_PFC_FUNCTION(scif0),
|
||||
SH_PFC_FUNCTION(scif1),
|
||||
SH_PFC_FUNCTION(scif2),
|
||||
|
|
@ -2377,30 +2488,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
|||
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
#define F_(x, y) FN_##y
|
||||
#define FM(x) FN_##x
|
||||
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
|
||||
GROUP(-23, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP0_31_9 RESERVED */
|
||||
GP_0_8_FN, GPSR0_8,
|
||||
GP_0_7_FN, GPSR0_7,
|
||||
GP_0_6_FN, GPSR0_6,
|
||||
|
|
@ -2479,29 +2570,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_2_1_FN, GPSR2_1,
|
||||
GP_2_0_FN, GPSR2_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
|
||||
GROUP(-22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP3_31_10 RESERVED */
|
||||
GP_3_9_FN, GPSR3_9,
|
||||
GP_3_8_FN, GPSR3_8,
|
||||
GP_3_7_FN, GPSR3_7,
|
||||
|
|
@ -2547,18 +2619,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_4_1_FN, GPSR4_1,
|
||||
GP_4_0_FN, GPSR4_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
|
||||
GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP5_31_21 RESERVED */
|
||||
GP_5_20_FN, GPSR5_20,
|
||||
GP_5_19_FN, GPSR5_19,
|
||||
GP_5_18_FN, GPSR5_18,
|
||||
|
|
@ -2581,25 +2646,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_5_1_FN, GPSR5_1,
|
||||
GP_5_0_FN, GPSR5_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR6", 0xe6060118, 32,
|
||||
GROUP(-18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1),
|
||||
GROUP(
|
||||
/* GP6_31_14 RESERVED */
|
||||
GP_6_13_FN, GPSR6_13,
|
||||
GP_6_12_FN, GPSR6_12,
|
||||
GP_6_11_FN, GPSR6_11,
|
||||
|
|
@ -2750,13 +2801,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
IP12_7_4
|
||||
IP12_3_0 ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
|
||||
/* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP13_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("IPSR13", 0xe6060234, 32,
|
||||
GROUP(-24, 4, 4),
|
||||
GROUP(
|
||||
/* IP13_31_8 RESERVED */
|
||||
IP13_7_4
|
||||
IP13_3_0 ))
|
||||
},
|
||||
|
|
@ -2766,11 +2814,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
#define F_(x, y) x,
|
||||
#define FM(x) FN_##x,
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
|
||||
GROUP(1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1,
|
||||
1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(-1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, -1,
|
||||
1, 1, 1, 1, 1, 1, -4, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* RESERVED 31 */
|
||||
0, 0,
|
||||
MOD_SEL0_30
|
||||
MOD_SEL0_29
|
||||
MOD_SEL0_28
|
||||
|
|
@ -2782,7 +2829,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL0_20_19
|
||||
MOD_SEL0_18_17
|
||||
/* RESERVED 16 */
|
||||
0, 0,
|
||||
MOD_SEL0_15
|
||||
MOD_SEL0_14
|
||||
MOD_SEL0_13
|
||||
|
|
@ -2790,7 +2836,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL0_11
|
||||
MOD_SEL0_10
|
||||
/* RESERVED 9, 8, 7, 6 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
MOD_SEL0_5
|
||||
MOD_SEL0_4
|
||||
MOD_SEL0_3
|
||||
|
|
@ -2799,7 +2844,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL0_0 ))
|
||||
},
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
|
||||
GROUP(1, 1, 1, 1, 1, 1, 2, 4, 4, 4, 4, 4, 4),
|
||||
GROUP(1, 1, 1, 1, 1, 1, -26),
|
||||
GROUP(
|
||||
MOD_SEL1_31
|
||||
MOD_SEL1_30
|
||||
|
|
@ -2807,25 +2852,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL1_28
|
||||
MOD_SEL1_27
|
||||
MOD_SEL1_26
|
||||
/* RESERVED 25, 24 */
|
||||
0, 0, 0, 0,
|
||||
/* RESERVED 23, 22, 21, 20 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 19, 18, 17, 16 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 15, 14, 13, 12 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 11, 10, 9, 8 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 7, 6, 5, 4 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 3, 2, 1, 0 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
|
||||
/* RESERVED 25-0 */ ))
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
|
||||
static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = -EINVAL;
|
||||
|
||||
|
|
@ -2837,6 +2869,214 @@ static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *po
|
|||
return bit;
|
||||
}
|
||||
|
||||
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
|
||||
[ 0] = RCAR_GP_PIN(1, 9), /* DU_DG1 */
|
||||
[ 1] = RCAR_GP_PIN(1, 8), /* DU_DG0 */
|
||||
[ 2] = RCAR_GP_PIN(1, 7), /* DU_DB7 */
|
||||
[ 3] = RCAR_GP_PIN(1, 6), /* DU_DB6 */
|
||||
[ 4] = RCAR_GP_PIN(1, 5), /* DU_DB5 */
|
||||
[ 5] = RCAR_GP_PIN(1, 4), /* DU_DB4 */
|
||||
[ 6] = RCAR_GP_PIN(1, 3), /* DU_DB3 */
|
||||
[ 7] = RCAR_GP_PIN(1, 2), /* DU_DB2 */
|
||||
[ 8] = RCAR_GP_PIN(1, 1), /* DU_DB1 */
|
||||
[ 9] = RCAR_GP_PIN(1, 0), /* DU_DB0 */
|
||||
[10] = PIN_MLB_REF, /* MLB_REF */
|
||||
[11] = RCAR_GP_PIN(0, 8), /* MLB_SIG */
|
||||
[12] = RCAR_GP_PIN(0, 7), /* MLB_DAT */
|
||||
[13] = RCAR_GP_PIN(0, 6), /* MLB_CLK */
|
||||
[14] = RCAR_GP_PIN(0, 5), /* MSIOF2_RXD */
|
||||
[15] = RCAR_GP_PIN(0, 4), /* MSIOF2_TXD */
|
||||
[16] = RCAR_GP_PIN(0, 3), /* MSIOF2_SCK */
|
||||
[17] = RCAR_GP_PIN(0, 2), /* IRQ0_A */
|
||||
[18] = RCAR_GP_PIN(0, 1), /* USB0_OVC */
|
||||
[19] = RCAR_GP_PIN(0, 0), /* USB0_PWEN */
|
||||
[20] = PIN_PRESETOUT_N, /* PRESETOUT# */
|
||||
[21] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
|
||||
[22] = PIN_FSCLKST_N, /* FSCLKST# */
|
||||
[23] = SH_PFC_PIN_NONE,
|
||||
[24] = SH_PFC_PIN_NONE,
|
||||
[25] = SH_PFC_PIN_NONE,
|
||||
[26] = SH_PFC_PIN_NONE,
|
||||
[27] = SH_PFC_PIN_NONE,
|
||||
[28] = PIN_TDI, /* TDI */
|
||||
[29] = PIN_TMS, /* TMS */
|
||||
[30] = PIN_TCK, /* TCK */
|
||||
[31] = PIN_TRST_N, /* TRST# */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
|
||||
[ 0] = RCAR_GP_PIN(2, 9), /* VI4_DATA8 */
|
||||
[ 1] = RCAR_GP_PIN(2, 8), /* VI4_DATA7 */
|
||||
[ 2] = RCAR_GP_PIN(2, 7), /* VI4_DATA6 */
|
||||
[ 3] = RCAR_GP_PIN(2, 6), /* VI4_DATA5 */
|
||||
[ 4] = RCAR_GP_PIN(2, 5), /* VI4_DATA4 */
|
||||
[ 5] = RCAR_GP_PIN(2, 4), /* VI4_DATA3 */
|
||||
[ 6] = RCAR_GP_PIN(2, 3), /* VI4_DATA2 */
|
||||
[ 7] = RCAR_GP_PIN(2, 2), /* VI4_DATA1 */
|
||||
[ 8] = RCAR_GP_PIN(2, 1), /* VI4_DATA0 */
|
||||
[ 9] = RCAR_GP_PIN(2, 0), /* VI4_CLK */
|
||||
[10] = RCAR_GP_PIN(1, 31), /* QPOLB */
|
||||
[11] = RCAR_GP_PIN(1, 30), /* QPOLA */
|
||||
[12] = RCAR_GP_PIN(1, 29), /* DU_CDE */
|
||||
[13] = RCAR_GP_PIN(1, 28), /* DU_DISP/CDE */
|
||||
[14] = RCAR_GP_PIN(1, 27), /* DU_DISP */
|
||||
[15] = RCAR_GP_PIN(1, 26), /* DU_VSYNC */
|
||||
[16] = RCAR_GP_PIN(1, 25), /* DU_HSYNC */
|
||||
[17] = RCAR_GP_PIN(1, 24), /* DU_DOTCLKOUT0 */
|
||||
[18] = RCAR_GP_PIN(1, 23), /* DU_DR7 */
|
||||
[19] = RCAR_GP_PIN(1, 22), /* DU_DR6 */
|
||||
[20] = RCAR_GP_PIN(1, 21), /* DU_DR5 */
|
||||
[21] = RCAR_GP_PIN(1, 20), /* DU_DR4 */
|
||||
[22] = RCAR_GP_PIN(1, 19), /* DU_DR3 */
|
||||
[23] = RCAR_GP_PIN(1, 18), /* DU_DR2 */
|
||||
[24] = RCAR_GP_PIN(1, 17), /* DU_DR1 */
|
||||
[25] = RCAR_GP_PIN(1, 16), /* DU_DR0 */
|
||||
[26] = RCAR_GP_PIN(1, 15), /* DU_DG7 */
|
||||
[27] = RCAR_GP_PIN(1, 14), /* DU_DG6 */
|
||||
[28] = RCAR_GP_PIN(1, 13), /* DU_DG5 */
|
||||
[29] = RCAR_GP_PIN(1, 12), /* DU_DG4 */
|
||||
[30] = RCAR_GP_PIN(1, 11), /* DU_DG3 */
|
||||
[31] = RCAR_GP_PIN(1, 10), /* DU_DG2 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
|
||||
[ 0] = RCAR_GP_PIN(3, 8), /* NFDATA6 */
|
||||
[ 1] = RCAR_GP_PIN(3, 7), /* NFDATA5 */
|
||||
[ 2] = RCAR_GP_PIN(3, 6), /* NFDATA4 */
|
||||
[ 3] = RCAR_GP_PIN(3, 5), /* NFDATA3 */
|
||||
[ 4] = RCAR_GP_PIN(3, 4), /* NFDATA2 */
|
||||
[ 5] = RCAR_GP_PIN(3, 3), /* NFDATA1 */
|
||||
[ 6] = RCAR_GP_PIN(3, 2), /* NFDATA0 */
|
||||
[ 7] = RCAR_GP_PIN(3, 1), /* NFWE# (PUEN) / NFRE# (PUD) */
|
||||
[ 8] = RCAR_GP_PIN(3, 0), /* NFRE# (PUEN) / NFWE# (PUD) */
|
||||
[ 9] = RCAR_GP_PIN(4, 0), /* NFRB# */
|
||||
[10] = RCAR_GP_PIN(2, 31), /* NFCE# */
|
||||
[11] = RCAR_GP_PIN(2, 30), /* NFCLE */
|
||||
[12] = RCAR_GP_PIN(2, 29), /* NFALE */
|
||||
[13] = RCAR_GP_PIN(2, 28), /* VI4_CLKENB */
|
||||
[14] = RCAR_GP_PIN(2, 27), /* VI4_FIELD */
|
||||
[15] = RCAR_GP_PIN(2, 26), /* VI4_HSYNC# */
|
||||
[16] = RCAR_GP_PIN(2, 25), /* VI4_VSYNC# */
|
||||
[17] = RCAR_GP_PIN(2, 24), /* VI4_DATA23 */
|
||||
[18] = RCAR_GP_PIN(2, 23), /* VI4_DATA22 */
|
||||
[19] = RCAR_GP_PIN(2, 22), /* VI4_DATA21 */
|
||||
[20] = RCAR_GP_PIN(2, 21), /* VI4_DATA20 */
|
||||
[21] = RCAR_GP_PIN(2, 20), /* VI4_DATA19 */
|
||||
[22] = RCAR_GP_PIN(2, 19), /* VI4_DATA18 */
|
||||
[23] = RCAR_GP_PIN(2, 18), /* VI4_DATA17 */
|
||||
[24] = RCAR_GP_PIN(2, 17), /* VI4_DATA16 */
|
||||
[25] = RCAR_GP_PIN(2, 16), /* VI4_DATA15 */
|
||||
[26] = RCAR_GP_PIN(2, 15), /* VI4_DATA14 */
|
||||
[27] = RCAR_GP_PIN(2, 14), /* VI4_DATA13 */
|
||||
[28] = RCAR_GP_PIN(2, 13), /* VI4_DATA12 */
|
||||
[29] = RCAR_GP_PIN(2, 12), /* VI4_DATA11 */
|
||||
[30] = RCAR_GP_PIN(2, 11), /* VI4_DATA10 */
|
||||
[31] = RCAR_GP_PIN(2, 10), /* VI4_DATA9 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
|
||||
[ 0] = RCAR_GP_PIN(4, 31), /* CAN0_RX_A */
|
||||
[ 1] = RCAR_GP_PIN(5, 2), /* CAN_CLK */
|
||||
[ 2] = RCAR_GP_PIN(5, 1), /* TPU0TO1_A */
|
||||
[ 3] = RCAR_GP_PIN(5, 0), /* TPU0TO0_A */
|
||||
[ 4] = RCAR_GP_PIN(4, 27), /* TX2 */
|
||||
[ 5] = RCAR_GP_PIN(4, 26), /* RX2 */
|
||||
[ 6] = RCAR_GP_PIN(4, 25), /* SCK2 */
|
||||
[ 7] = RCAR_GP_PIN(4, 24), /* TX1_A */
|
||||
[ 8] = RCAR_GP_PIN(4, 23), /* RX1_A */
|
||||
[ 9] = RCAR_GP_PIN(4, 22), /* SCK1_A */
|
||||
[10] = RCAR_GP_PIN(4, 21), /* TX0_A */
|
||||
[11] = RCAR_GP_PIN(4, 20), /* RX0_A */
|
||||
[12] = RCAR_GP_PIN(4, 19), /* SCK0_A */
|
||||
[13] = RCAR_GP_PIN(4, 18), /* MSIOF1_RXD */
|
||||
[14] = RCAR_GP_PIN(4, 17), /* MSIOF1_TXD */
|
||||
[15] = RCAR_GP_PIN(4, 16), /* MSIOF1_SCK */
|
||||
[16] = RCAR_GP_PIN(4, 15), /* MSIOF0_RXD */
|
||||
[17] = RCAR_GP_PIN(4, 14), /* MSIOF0_TXD */
|
||||
[18] = RCAR_GP_PIN(4, 13), /* MSIOF0_SYNC */
|
||||
[19] = RCAR_GP_PIN(4, 12), /* MSIOF0_SCK */
|
||||
[20] = RCAR_GP_PIN(4, 11), /* SDA1 */
|
||||
[21] = RCAR_GP_PIN(4, 10), /* SCL1 */
|
||||
[22] = RCAR_GP_PIN(4, 9), /* SDA0 */
|
||||
[23] = RCAR_GP_PIN(4, 8), /* SCL0 */
|
||||
[24] = RCAR_GP_PIN(4, 7), /* SSI_WS4_A */
|
||||
[25] = RCAR_GP_PIN(4, 6), /* SSI_SDATA4_A */
|
||||
[26] = RCAR_GP_PIN(4, 5), /* SSI_SCK4_A */
|
||||
[27] = RCAR_GP_PIN(4, 4), /* SSI_WS34 */
|
||||
[28] = RCAR_GP_PIN(4, 3), /* SSI_SDATA3 */
|
||||
[29] = RCAR_GP_PIN(4, 2), /* SSI_SCK34 */
|
||||
[30] = RCAR_GP_PIN(4, 1), /* AUDIO_CLKA */
|
||||
[31] = RCAR_GP_PIN(3, 9), /* NFDATA7 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
|
||||
[ 0] = RCAR_GP_PIN(6, 10), /* QSPI1_IO3 */
|
||||
[ 1] = RCAR_GP_PIN(6, 9), /* QSPI1_IO2 */
|
||||
[ 2] = RCAR_GP_PIN(6, 8), /* QSPI1_MISO_IO1 */
|
||||
[ 3] = RCAR_GP_PIN(6, 7), /* QSPI1_MOSI_IO0 */
|
||||
[ 4] = RCAR_GP_PIN(6, 6), /* QSPI1_SPCLK */
|
||||
[ 5] = RCAR_GP_PIN(6, 5), /* QSPI0_SSL */
|
||||
[ 6] = RCAR_GP_PIN(6, 4), /* QSPI0_IO3 */
|
||||
[ 7] = RCAR_GP_PIN(6, 3), /* QSPI0_IO2 */
|
||||
[ 8] = RCAR_GP_PIN(6, 2), /* QSPI0_MISO_IO1 */
|
||||
[ 9] = RCAR_GP_PIN(6, 1), /* QSPI0_MOSI_IO0 */
|
||||
[10] = RCAR_GP_PIN(6, 0), /* QSPI0_SPCLK */
|
||||
[11] = RCAR_GP_PIN(5, 20), /* AVB0_LINK */
|
||||
[12] = RCAR_GP_PIN(5, 19), /* AVB0_PHY_INT */
|
||||
[13] = RCAR_GP_PIN(5, 18), /* AVB0_MAGIC */
|
||||
[14] = RCAR_GP_PIN(5, 17), /* AVB0_MDC */
|
||||
[15] = RCAR_GP_PIN(5, 16), /* AVB0_MDIO */
|
||||
[16] = RCAR_GP_PIN(5, 15), /* AVB0_TXCREFCLK */
|
||||
[17] = RCAR_GP_PIN(5, 14), /* AVB0_TD3 */
|
||||
[18] = RCAR_GP_PIN(5, 13), /* AVB0_TD2 */
|
||||
[19] = RCAR_GP_PIN(5, 12), /* AVB0_TD1 */
|
||||
[20] = RCAR_GP_PIN(5, 11), /* AVB0_TD0 */
|
||||
[21] = RCAR_GP_PIN(5, 10), /* AVB0_TXC */
|
||||
[22] = RCAR_GP_PIN(5, 9), /* AVB0_TX_CTL */
|
||||
[23] = RCAR_GP_PIN(5, 8), /* AVB0_RD3 */
|
||||
[24] = RCAR_GP_PIN(5, 7), /* AVB0_RD2 */
|
||||
[25] = RCAR_GP_PIN(5, 6), /* AVB0_RD1 */
|
||||
[26] = RCAR_GP_PIN(5, 5), /* AVB0_RD0 */
|
||||
[27] = RCAR_GP_PIN(5, 4), /* AVB0_RXC */
|
||||
[28] = RCAR_GP_PIN(5, 3), /* AVB0_RX_CTL */
|
||||
[29] = RCAR_GP_PIN(4, 30), /* CAN1_TX_A */
|
||||
[30] = RCAR_GP_PIN(4, 29), /* CAN1_RX_A */
|
||||
[31] = RCAR_GP_PIN(4, 28), /* CAN0_TX_A */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD4", 0xe6060454) {
|
||||
[ 0] = SH_PFC_PIN_NONE,
|
||||
[ 1] = SH_PFC_PIN_NONE,
|
||||
[ 2] = SH_PFC_PIN_NONE,
|
||||
[ 3] = SH_PFC_PIN_NONE,
|
||||
[ 4] = SH_PFC_PIN_NONE,
|
||||
[ 5] = SH_PFC_PIN_NONE,
|
||||
[ 6] = SH_PFC_PIN_NONE,
|
||||
[ 7] = SH_PFC_PIN_NONE,
|
||||
[ 8] = SH_PFC_PIN_NONE,
|
||||
[ 9] = SH_PFC_PIN_NONE,
|
||||
[10] = SH_PFC_PIN_NONE,
|
||||
[11] = SH_PFC_PIN_NONE,
|
||||
[12] = SH_PFC_PIN_NONE,
|
||||
[13] = SH_PFC_PIN_NONE,
|
||||
[14] = SH_PFC_PIN_NONE,
|
||||
[15] = SH_PFC_PIN_NONE,
|
||||
[16] = SH_PFC_PIN_NONE,
|
||||
[17] = SH_PFC_PIN_NONE,
|
||||
[18] = SH_PFC_PIN_NONE,
|
||||
[19] = SH_PFC_PIN_NONE,
|
||||
[20] = SH_PFC_PIN_NONE,
|
||||
[21] = SH_PFC_PIN_NONE,
|
||||
[22] = SH_PFC_PIN_NONE,
|
||||
[23] = SH_PFC_PIN_NONE,
|
||||
[24] = SH_PFC_PIN_NONE,
|
||||
[25] = SH_PFC_PIN_NONE,
|
||||
[26] = SH_PFC_PIN_NONE,
|
||||
[27] = SH_PFC_PIN_NONE,
|
||||
[28] = SH_PFC_PIN_NONE,
|
||||
[29] = RCAR_GP_PIN(6, 13), /* RPC_INT# */
|
||||
[30] = RCAR_GP_PIN(6, 12), /* RPC_RESET# */
|
||||
[31] = RCAR_GP_PIN(6, 11), /* QSPI1_SSL */
|
||||
} },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
enum ioctrl_regs {
|
||||
TDSELCTRL,
|
||||
};
|
||||
|
|
@ -2846,13 +3086,88 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
|||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
|
||||
static const struct pinmux_bias_reg *
|
||||
r8a77995_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int *puen_bit, unsigned int *pud_bit)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
unsigned int bit;
|
||||
|
||||
reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit);
|
||||
if (!reg)
|
||||
return reg;
|
||||
|
||||
*puen_bit = bit;
|
||||
|
||||
/* NFWE# and NFRE# use different bit positions in PUD2 */
|
||||
switch (pin) {
|
||||
case RCAR_GP_PIN(3, 0): /* NFRE# */
|
||||
*pud_bit = 7;
|
||||
break;
|
||||
|
||||
case RCAR_GP_PIN(3, 1): /* NFWE# */
|
||||
*pud_bit = 8;
|
||||
break;
|
||||
|
||||
default:
|
||||
*pud_bit = bit;
|
||||
break;
|
||||
}
|
||||
|
||||
return reg;
|
||||
}
|
||||
|
||||
static unsigned int r8a77995_pinmux_get_bias(struct sh_pfc *pfc,
|
||||
unsigned int pin)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
unsigned int puen_bit, pud_bit;
|
||||
|
||||
reg = r8a77995_pin_to_bias_reg(pfc, pin, &puen_bit, &pud_bit);
|
||||
if (!reg)
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
|
||||
if (!(sh_pfc_read(pfc, reg->puen) & BIT(puen_bit)))
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
else if (sh_pfc_read(pfc, reg->pud) & BIT(pud_bit))
|
||||
return PIN_CONFIG_BIAS_PULL_UP;
|
||||
else
|
||||
return PIN_CONFIG_BIAS_PULL_DOWN;
|
||||
}
|
||||
|
||||
static void r8a77995_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
unsigned int puen_bit, pud_bit;
|
||||
u32 enable, updown;
|
||||
|
||||
reg = r8a77995_pin_to_bias_reg(pfc, pin, &puen_bit, &pud_bit);
|
||||
if (!reg)
|
||||
return;
|
||||
|
||||
enable = sh_pfc_read(pfc, reg->puen) & ~BIT(puen_bit);
|
||||
if (bias != PIN_CONFIG_BIAS_DISABLE) {
|
||||
enable |= BIT(puen_bit);
|
||||
|
||||
updown = sh_pfc_read(pfc, reg->pud) & ~BIT(pud_bit);
|
||||
if (bias == PIN_CONFIG_BIAS_PULL_UP)
|
||||
updown |= BIT(pud_bit);
|
||||
|
||||
sh_pfc_write(pfc, reg->pud, updown);
|
||||
}
|
||||
sh_pfc_write(pfc, reg->puen, enable);
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a77995_pfc_ops = {
|
||||
.pin_to_pocctrl = r8a77995_pin_to_pocctrl,
|
||||
.get_bias = r8a77995_pinmux_get_bias,
|
||||
.set_bias = r8a77995_pinmux_set_bias,
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info r8a77995_pinmux_info = {
|
||||
.name = "r8a77995_pfc",
|
||||
.ops = &r8a77995_pinmux_ops,
|
||||
.ops = &r8a77995_pfc_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
|
@ -2865,6 +3180,7 @@ const struct sh_pfc_soc_info r8a77995_pinmux_info = {
|
|||
.nr_functions = ARRAY_SIZE(pinmux_functions),
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.bias_regs = pinmux_bias_regs,
|
||||
.ioctrl_regs = pinmux_ioctrl_regs,
|
||||
|
||||
.pinmux_data = pinmux_data,
|
||||
|
|
|
|||
|
|
@ -392,7 +392,6 @@
|
|||
#define IP3SR1_19_16 FM(GP1_28) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP3SR1_23_20 FM(GP1_29) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP3SR1_27_24 FM(GP1_30) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP3SR1_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
||||
/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
|
||||
#define IP0SR2_3_0 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
|
@ -423,11 +422,8 @@
|
|||
#define IP2SR2_31_28 FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(EX_WAIT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
||||
/* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
|
||||
#define IP0SR3_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP0SR3_7_4 FM(CANFD0_TX) FM(FXR_TXDA_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP0SR3_11_8 FM(CANFD0_RX) FM(RXDA_EXTFXR_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP0SR3_15_12 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP0SR3_19_16 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP0SR3_23_20 FM(CANFD2_TX) FM(TPU0TO2) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP0SR3_27_24 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP0SR3_31_28 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
|
@ -438,8 +434,6 @@
|
|||
#define IP1SR3_15_12 FM(CANFD5_TX) F_(0, 0) F_(0, 0) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1SR3_19_16 FM(CANFD5_RX) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1SR3_23_20 FM(CANFD6_TX) F_(0, 0) F_(0, 0) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1SR3_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1SR3_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
||||
/* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
|
||||
#define IP0SR4_3_0 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
|
@ -460,14 +454,10 @@
|
|||
#define IP1SR4_27_24 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1SR4_31_28 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
/* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
|
||||
#define IP2SR4_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2SR4_7_4 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2SR4_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2SR4_15_12 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2SR4_19_16 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2SR4_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2SR4_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2SR4_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
||||
/* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
|
||||
#define IP0SR5_3_0 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
|
@ -488,14 +478,10 @@
|
|||
#define IP1SR5_27_24 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP1SR5_31_28 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
/* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
|
||||
#define IP2SR5_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2SR5_7_4 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2SR5_11_8 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2SR5_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2SR5_19_16 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2SR5_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2SR5_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2SR5_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
||||
#define PINMUX_GPSR \
|
||||
\
|
||||
|
|
@ -540,7 +526,7 @@ FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2
|
|||
FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \
|
||||
FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 FM(IP3SR1_23_20) IP3SR1_23_20 \
|
||||
FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 FM(IP3SR1_27_24) IP3SR1_27_24 \
|
||||
FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 FM(IP3SR1_31_28) IP3SR1_31_28 \
|
||||
FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 \
|
||||
\
|
||||
FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 FM(IP2SR2_3_0) IP2SR2_3_0 \
|
||||
FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \
|
||||
|
|
@ -551,51 +537,51 @@ FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 FM(IP2SR2_23_20) IP2
|
|||
FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 FM(IP2SR2_27_24) IP2SR2_27_24 \
|
||||
FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 FM(IP2SR2_31_28) IP2SR2_31_28 \
|
||||
\
|
||||
FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 \
|
||||
FM(IP1SR3_3_0) IP1SR3_3_0 \
|
||||
FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 \
|
||||
FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 \
|
||||
FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 \
|
||||
FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 \
|
||||
FM(IP1SR3_15_12) IP1SR3_15_12 \
|
||||
FM(IP1SR3_19_16) IP1SR3_19_16 \
|
||||
FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 \
|
||||
FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 \
|
||||
FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 \
|
||||
FM(IP0SR3_27_24) IP0SR3_27_24 \
|
||||
FM(IP0SR3_31_28) IP0SR3_31_28 \
|
||||
\
|
||||
FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP2SR4_3_0) IP2SR4_3_0 \
|
||||
FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 \
|
||||
FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 FM(IP2SR4_7_4) IP2SR4_7_4 \
|
||||
FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 FM(IP2SR4_11_8) IP2SR4_11_8 \
|
||||
FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 FM(IP2SR4_15_12) IP2SR4_15_12 \
|
||||
FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 FM(IP2SR4_19_16) IP2SR4_19_16 \
|
||||
FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \
|
||||
FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 FM(IP2SR4_27_24) IP2SR4_27_24 \
|
||||
FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \
|
||||
FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 \
|
||||
FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 \
|
||||
FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 \
|
||||
\
|
||||
FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \
|
||||
FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 \
|
||||
FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \
|
||||
FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \
|
||||
FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \
|
||||
FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \
|
||||
FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 FM(IP2SR5_23_20) IP2SR5_23_20 \
|
||||
FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 FM(IP2SR5_27_24) IP2SR5_27_24 \
|
||||
FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 FM(IP2SR5_31_28) IP2SR5_31_28
|
||||
FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 \
|
||||
FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 \
|
||||
FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28
|
||||
|
||||
/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
|
||||
#define MOD_SEL2_14_15 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3)
|
||||
#define MOD_SEL2_12_13 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3)
|
||||
#define MOD_SEL2_10_11 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3)
|
||||
#define MOD_SEL2_8_9 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3)
|
||||
#define MOD_SEL2_6_7 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3)
|
||||
#define MOD_SEL2_4_5 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3)
|
||||
#define MOD_SEL2_2_3 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3)
|
||||
#define MOD_SEL2_15_14 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3)
|
||||
#define MOD_SEL2_13_12 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3)
|
||||
#define MOD_SEL2_11_10 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3)
|
||||
#define MOD_SEL2_9_8 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3)
|
||||
#define MOD_SEL2_7_6 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3)
|
||||
#define MOD_SEL2_5_4 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3)
|
||||
#define MOD_SEL2_3_2 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3)
|
||||
|
||||
#define PINMUX_MOD_SELS \
|
||||
\
|
||||
MOD_SEL2_14_15 \
|
||||
MOD_SEL2_12_13 \
|
||||
MOD_SEL2_10_11 \
|
||||
MOD_SEL2_8_9 \
|
||||
MOD_SEL2_6_7 \
|
||||
MOD_SEL2_4_5 \
|
||||
MOD_SEL2_2_3
|
||||
MOD_SEL2_15_14 \
|
||||
MOD_SEL2_13_12 \
|
||||
MOD_SEL2_11_10 \
|
||||
MOD_SEL2_9_8 \
|
||||
MOD_SEL2_7_6 \
|
||||
MOD_SEL2_5_4 \
|
||||
MOD_SEL2_3_2
|
||||
|
||||
#define PINMUX_PHYS \
|
||||
FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \
|
||||
|
|
@ -632,7 +618,36 @@ enum {
|
|||
};
|
||||
|
||||
static const u16 pinmux_data[] = {
|
||||
/* Using GP_2_[2-15] requires disabling I2C in MOD_SEL2 */
|
||||
#define GP_2_2_FN GP_2_2_FN, FN_SEL_I2C0_0
|
||||
#define GP_2_3_FN GP_2_3_FN, FN_SEL_I2C0_0
|
||||
#define GP_2_4_FN GP_2_4_FN, FN_SEL_I2C1_0
|
||||
#define GP_2_5_FN GP_2_5_FN, FN_SEL_I2C1_0
|
||||
#define GP_2_6_FN GP_2_6_FN, FN_SEL_I2C2_0
|
||||
#define GP_2_7_FN GP_2_7_FN, FN_SEL_I2C2_0
|
||||
#define GP_2_8_FN GP_2_8_FN, FN_SEL_I2C3_0
|
||||
#define GP_2_9_FN GP_2_9_FN, FN_SEL_I2C3_0
|
||||
#define GP_2_10_FN GP_2_10_FN, FN_SEL_I2C4_0
|
||||
#define GP_2_11_FN GP_2_11_FN, FN_SEL_I2C4_0
|
||||
#define GP_2_12_FN GP_2_12_FN, FN_SEL_I2C5_0
|
||||
#define GP_2_13_FN GP_2_13_FN, FN_SEL_I2C5_0
|
||||
#define GP_2_14_FN GP_2_14_FN, FN_SEL_I2C6_0
|
||||
#define GP_2_15_FN GP_2_15_FN, FN_SEL_I2C6_0
|
||||
PINMUX_DATA_GP_ALL(),
|
||||
#undef GP_2_2_FN
|
||||
#undef GP_2_3_FN
|
||||
#undef GP_2_4_FN
|
||||
#undef GP_2_5_FN
|
||||
#undef GP_2_6_FN
|
||||
#undef GP_2_7_FN
|
||||
#undef GP_2_8_FN
|
||||
#undef GP_2_9_FN
|
||||
#undef GP_2_10_FN
|
||||
#undef GP_2_11_FN
|
||||
#undef GP_2_12_FN
|
||||
#undef GP_2_13_FN
|
||||
#undef GP_2_14_FN
|
||||
#undef GP_2_15_FN
|
||||
|
||||
PINMUX_SINGLE(MMC_D7),
|
||||
PINMUX_SINGLE(MMC_D6),
|
||||
|
|
@ -2012,30 +2027,14 @@ static const unsigned int intc_ex_irq5_mux[] = {
|
|||
};
|
||||
|
||||
/* - MMC -------------------------------------------------------------------- */
|
||||
static const unsigned int mmc_data1_pins[] = {
|
||||
/* MMC_SD_D0 */
|
||||
RCAR_GP_PIN(0, 19),
|
||||
};
|
||||
static const unsigned int mmc_data1_mux[] = {
|
||||
MMC_SD_D0_MARK,
|
||||
};
|
||||
static const unsigned int mmc_data4_pins[] = {
|
||||
/* MMC_SD_D[0:3] */
|
||||
RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
|
||||
RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
|
||||
};
|
||||
static const unsigned int mmc_data4_mux[] = {
|
||||
MMC_SD_D0_MARK, MMC_SD_D1_MARK,
|
||||
MMC_SD_D2_MARK, MMC_SD_D3_MARK,
|
||||
};
|
||||
static const unsigned int mmc_data8_pins[] = {
|
||||
static const unsigned int mmc_data_pins[] = {
|
||||
/* MMC_SD_D[0:3], MMC_D[4:7] */
|
||||
RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
|
||||
RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
|
||||
RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
|
||||
RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 27),
|
||||
};
|
||||
static const unsigned int mmc_data8_mux[] = {
|
||||
static const unsigned int mmc_data_mux[] = {
|
||||
MMC_SD_D0_MARK, MMC_SD_D1_MARK,
|
||||
MMC_SD_D2_MARK, MMC_SD_D3_MARK,
|
||||
MMC_D4_MARK, MMC_D5_MARK,
|
||||
|
|
@ -2387,19 +2386,12 @@ static const unsigned int qspi0_ctrl_pins[] = {
|
|||
static const unsigned int qspi0_ctrl_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data2_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1 */
|
||||
RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
|
||||
};
|
||||
static const unsigned int qspi0_data2_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data4_pins[] = {
|
||||
static const unsigned int qspi0_data_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
|
||||
RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
|
||||
RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
|
||||
};
|
||||
static const unsigned int qspi0_data4_mux[] = {
|
||||
static const unsigned int qspi0_data_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
QSPI0_IO2_MARK, QSPI0_IO3_MARK
|
||||
};
|
||||
|
|
@ -2412,19 +2404,12 @@ static const unsigned int qspi1_ctrl_pins[] = {
|
|||
static const unsigned int qspi1_ctrl_mux[] = {
|
||||
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data2_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1 */
|
||||
RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
|
||||
};
|
||||
static const unsigned int qspi1_data2_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data4_pins[] = {
|
||||
static const unsigned int qspi1_data_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
|
||||
RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
|
||||
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
|
||||
};
|
||||
static const unsigned int qspi1_data4_mux[] = {
|
||||
static const unsigned int qspi1_data_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
QSPI1_IO2_MARK, QSPI1_IO3_MARK
|
||||
};
|
||||
|
|
@ -2718,9 +2703,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(intc_ex_irq4),
|
||||
SH_PFC_PIN_GROUP(intc_ex_irq5),
|
||||
|
||||
SH_PFC_PIN_GROUP(mmc_data1),
|
||||
SH_PFC_PIN_GROUP(mmc_data4),
|
||||
SH_PFC_PIN_GROUP(mmc_data8),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 1),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 4),
|
||||
BUS_DATA_PIN_GROUP(mmc_data, 8),
|
||||
SH_PFC_PIN_GROUP(mmc_ctrl),
|
||||
SH_PFC_PIN_GROUP(mmc_cd),
|
||||
SH_PFC_PIN_GROUP(mmc_wp),
|
||||
|
|
@ -2770,11 +2755,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(pwm4),
|
||||
|
||||
SH_PFC_PIN_GROUP(qspi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi0_data2),
|
||||
SH_PFC_PIN_GROUP(qspi0_data4),
|
||||
BUS_DATA_PIN_GROUP(qspi0_data, 2),
|
||||
BUS_DATA_PIN_GROUP(qspi0_data, 4),
|
||||
SH_PFC_PIN_GROUP(qspi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi1_data2),
|
||||
SH_PFC_PIN_GROUP(qspi1_data4),
|
||||
BUS_DATA_PIN_GROUP(qspi1_data, 2),
|
||||
BUS_DATA_PIN_GROUP(qspi1_data, 4),
|
||||
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
SH_PFC_PIN_GROUP(scif0_clk),
|
||||
|
|
@ -3256,14 +3241,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_1_1_FN, GPSR1_1,
|
||||
GP_1_0_FN, GPSR1_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR2", 0xe6050840, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6050840, 32,
|
||||
GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP2_31_25 RESERVED */
|
||||
GP_2_24_FN, GPSR2_24,
|
||||
GP_2_23_FN, GPSR2_23,
|
||||
GP_2_22_FN, GPSR2_22,
|
||||
|
|
@ -3290,22 +3272,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_2_1_FN, GPSR2_1,
|
||||
GP_2_0_FN, GPSR2_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR3", 0xe6058840, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR3", 0xe6058840, 32,
|
||||
GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP3_31_17 RESERVED */
|
||||
GP_3_16_FN, GPSR3_16,
|
||||
GP_3_15_FN, GPSR3_15,
|
||||
GP_3_14_FN, GPSR3_14,
|
||||
|
|
@ -3358,18 +3329,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_4_1_FN, GPSR4_1,
|
||||
GP_4_0_FN, GPSR4_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR5", 0xe6060840, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR5", 0xe6060840, 32,
|
||||
GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP5_31_21 RESERVED */
|
||||
GP_5_20_FN, GPSR5_20,
|
||||
GP_5_19_FN, GPSR5_19,
|
||||
GP_5_18_FN, GPSR5_18,
|
||||
|
|
@ -3392,18 +3356,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_5_1_FN, GPSR5_1,
|
||||
GP_5_0_FN, GPSR5_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR6", 0xe6068040, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR6", 0xe6068040, 32,
|
||||
GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP6_31_21 RESERVED */
|
||||
GP_6_20_FN, GPSR6_20,
|
||||
GP_6_19_FN, GPSR6_19,
|
||||
GP_6_18_FN, GPSR6_18,
|
||||
|
|
@ -3426,18 +3383,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_6_1_FN, GPSR6_1,
|
||||
GP_6_0_FN, GPSR6_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR7", 0xe6068840, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR7", 0xe6068840, 32,
|
||||
GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP7_31_21 RESERVED */
|
||||
GP_7_20_FN, GPSR7_20,
|
||||
GP_7_19_FN, GPSR7_19,
|
||||
GP_7_18_FN, GPSR7_18,
|
||||
|
|
@ -3460,18 +3410,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_7_1_FN, GPSR7_1,
|
||||
GP_7_0_FN, GPSR7_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR8", 0xe6069040, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR8", 0xe6069040, 32,
|
||||
GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP8_31_21 RESERVED */
|
||||
GP_8_20_FN, GPSR8_20,
|
||||
GP_8_19_FN, GPSR8_19,
|
||||
GP_8_18_FN, GPSR8_18,
|
||||
|
|
@ -3494,18 +3437,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_8_1_FN, GPSR8_1,
|
||||
GP_8_0_FN, GPSR8_0, ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("GPSR9", 0xe6069840, 32, 1, GROUP(
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
0, 0,
|
||||
{ PINMUX_CFG_REG_VAR("GPSR9", 0xe6069840, 32,
|
||||
GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
|
||||
GROUP(
|
||||
/* GP9_31_21 RESERVED */
|
||||
GP_9_20_FN, GPSR9_20,
|
||||
GP_9_19_FN, GPSR9_19,
|
||||
GP_9_18_FN, GPSR9_18,
|
||||
|
|
@ -3563,8 +3499,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
IP2SR1_7_4
|
||||
IP2SR1_3_0))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IP3SR1", 0xe605006c, 32, 4, GROUP(
|
||||
IP3SR1_31_28
|
||||
{ PINMUX_CFG_REG_VAR("IP3SR1", 0xe605006c, 32,
|
||||
GROUP(-4, 4, 4, 4, 4, 4, 4, 4),
|
||||
GROUP(
|
||||
/* IP3SR1_31_28 RESERVED */
|
||||
IP3SR1_27_24
|
||||
IP3SR1_23_20
|
||||
IP3SR1_19_16
|
||||
|
|
@ -3603,19 +3541,21 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
IP2SR2_7_4
|
||||
IP2SR2_3_0))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IP0SR3", 0xe6058860, 32, 4, GROUP(
|
||||
{ PINMUX_CFG_REG_VAR("IP0SR3", 0xe6058860, 32,
|
||||
GROUP(4, 4, 4, -8, 4, 4, -4),
|
||||
GROUP(
|
||||
IP0SR3_31_28
|
||||
IP0SR3_27_24
|
||||
IP0SR3_23_20
|
||||
IP0SR3_19_16
|
||||
IP0SR3_15_12
|
||||
/* IP0SR3_19_12 RESERVED */
|
||||
IP0SR3_11_8
|
||||
IP0SR3_7_4
|
||||
IP0SR3_3_0))
|
||||
/* IP0SR3_3_0 RESERVED */ ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IP1SR3", 0xe6058864, 32, 4, GROUP(
|
||||
IP1SR3_31_28
|
||||
IP1SR3_27_24
|
||||
{ PINMUX_CFG_REG_VAR("IP1SR3", 0xe6058864, 32,
|
||||
GROUP(-8, 4, 4, 4, 4, 4, 4),
|
||||
GROUP(
|
||||
/* IP1SR3_31_24 RESERVED */
|
||||
IP1SR3_23_20
|
||||
IP1SR3_19_16
|
||||
IP1SR3_15_12
|
||||
|
|
@ -3643,15 +3583,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
IP1SR4_7_4
|
||||
IP1SR4_3_0))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IP2SR4", 0xe6060068, 32, 4, GROUP(
|
||||
IP2SR4_31_28
|
||||
IP2SR4_27_24
|
||||
IP2SR4_23_20
|
||||
{ PINMUX_CFG_REG_VAR("IP2SR4", 0xe6060068, 32,
|
||||
GROUP(-12, 4, 4, 4, 4, -4),
|
||||
GROUP(
|
||||
/* IP2SR4_31_20 RESERVED */
|
||||
IP2SR4_19_16
|
||||
IP2SR4_15_12
|
||||
IP2SR4_11_8
|
||||
IP2SR4_7_4
|
||||
IP2SR4_3_0))
|
||||
/* IP2SR4_3_0 RESERVED */ ))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IP0SR5", 0xe6060860, 32, 4, GROUP(
|
||||
IP0SR5_31_28
|
||||
|
|
@ -3673,15 +3613,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
IP1SR5_7_4
|
||||
IP1SR5_3_0))
|
||||
},
|
||||
{ PINMUX_CFG_REG("IP2SR5", 0xe6060868, 32, 4, GROUP(
|
||||
IP2SR5_31_28
|
||||
IP2SR5_27_24
|
||||
IP2SR5_23_20
|
||||
{ PINMUX_CFG_REG_VAR("IP2SR5", 0xe6060868, 32,
|
||||
GROUP(-12, 4, 4, 4, 4, -4),
|
||||
GROUP(
|
||||
/* IP2SR5_31_20 RESERVED */
|
||||
IP2SR5_19_16
|
||||
IP2SR5_15_12
|
||||
IP2SR5_11_8
|
||||
IP2SR5_7_4
|
||||
IP2SR5_3_0))
|
||||
/* IP2SR5_3_0 RESERVED */ ))
|
||||
},
|
||||
#undef F_
|
||||
#undef FM
|
||||
|
|
@ -3689,25 +3629,17 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
#define F_(x, y) x,
|
||||
#define FM(x) FN_##x,
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6050900, 32,
|
||||
GROUP(4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 1, 1),
|
||||
GROUP(-16, 2, 2, 2, 2, 2, 2, 2, -2),
|
||||
GROUP(
|
||||
/* RESERVED 31, 30, 29, 28 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 27, 26, 25, 24 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 23, 22, 21, 20 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* RESERVED 19, 18, 17, 16 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
MOD_SEL2_14_15
|
||||
MOD_SEL2_12_13
|
||||
MOD_SEL2_10_11
|
||||
MOD_SEL2_8_9
|
||||
MOD_SEL2_6_7
|
||||
MOD_SEL2_4_5
|
||||
MOD_SEL2_2_3
|
||||
0, 0,
|
||||
0, 0, ))
|
||||
/* RESERVED 31-16 */
|
||||
MOD_SEL2_15_14
|
||||
MOD_SEL2_13_12
|
||||
MOD_SEL2_11_10
|
||||
MOD_SEL2_9_8
|
||||
MOD_SEL2_7_6
|
||||
MOD_SEL2_5_4
|
||||
MOD_SEL2_3_2
|
||||
/* RESERVED 1-0 */ ))
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
|
@ -3838,7 +3770,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ RCAR_GP_PIN(3, 12), 16, 3 }, /* CANFD5_RX */
|
||||
{ RCAR_GP_PIN(3, 11), 12, 3 }, /* CANFD5_TX */
|
||||
{ RCAR_GP_PIN(3, 10), 8, 3 }, /* CANFD4_RX */
|
||||
{ RCAR_GP_PIN(3, 9), 4, 3 }, /* CANFD4_TX*/
|
||||
{ RCAR_GP_PIN(3, 9), 4, 3 }, /* CANFD4_TX */
|
||||
{ RCAR_GP_PIN(3, 8), 0, 3 }, /* CANFD3_RX */
|
||||
} },
|
||||
{ PINMUX_DRIVE_REG("DRV2CTRL3", 0xe6058888) {
|
||||
|
|
@ -4044,8 +3976,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
|||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int r8a779a0_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
|
||||
u32 *pocctrl)
|
||||
static int r8a779a0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = pin & 0x1f;
|
||||
|
||||
|
|
@ -4308,7 +4239,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[11] = RCAR_GP_PIN(6, 11), /* AVB2_TD3 */
|
||||
[12] = RCAR_GP_PIN(6, 12), /* AVB2_TXCREFCLK */
|
||||
[13] = RCAR_GP_PIN(6, 13), /* AVB2_MDIO */
|
||||
[14] = RCAR_GP_PIN(6, 14), /* AVB2_MDC*/
|
||||
[14] = RCAR_GP_PIN(6, 14), /* AVB2_MDC */
|
||||
[15] = RCAR_GP_PIN(6, 15), /* AVB2_MAGIC */
|
||||
[16] = RCAR_GP_PIN(6, 16), /* AVB2_PHY_INT */
|
||||
[17] = RCAR_GP_PIN(6, 17), /* AVB2_LINK */
|
||||
|
|
@ -4432,56 +4363,15 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static unsigned int r8a779a0_pinmux_get_bias(struct sh_pfc *pfc,
|
||||
unsigned int pin)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
unsigned int bit;
|
||||
|
||||
reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
|
||||
if (!reg)
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
|
||||
if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
|
||||
return PIN_CONFIG_BIAS_PULL_UP;
|
||||
else
|
||||
return PIN_CONFIG_BIAS_PULL_DOWN;
|
||||
}
|
||||
|
||||
static void r8a779a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
u32 enable, updown;
|
||||
unsigned int bit;
|
||||
|
||||
reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
|
||||
if (!reg)
|
||||
return;
|
||||
|
||||
enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
|
||||
if (bias != PIN_CONFIG_BIAS_DISABLE)
|
||||
enable |= BIT(bit);
|
||||
|
||||
updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
|
||||
if (bias == PIN_CONFIG_BIAS_PULL_UP)
|
||||
updown |= BIT(bit);
|
||||
|
||||
sh_pfc_write(pfc, reg->pud, updown);
|
||||
sh_pfc_write(pfc, reg->puen, enable);
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations pinmux_ops = {
|
||||
static const struct sh_pfc_soc_operations r8a779a0_pfc_ops = {
|
||||
.pin_to_pocctrl = r8a779a0_pin_to_pocctrl,
|
||||
.get_bias = r8a779a0_pinmux_get_bias,
|
||||
.set_bias = r8a779a0_pinmux_set_bias,
|
||||
.get_bias = rcar_pinmux_get_bias,
|
||||
.set_bias = rcar_pinmux_set_bias,
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info r8a779a0_pinmux_info = {
|
||||
.name = "r8a779a0_pfc",
|
||||
.ops = &pinmux_ops,
|
||||
.ops = &r8a779a0_pfc_ops,
|
||||
.unlock_reg = 0x1ff, /* PMMRn mask */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
|
|
|||
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Add table
Reference in a new issue