Commit graph

86229 commits

Author SHA1 Message Date
Ashok Reddy Soma
cfb82f7c12 mtd: nand: Mark reserved blocks
Reserved blocks are used for storing bad block tables. With "nand bad"
command, these reserved blocks are shown as bad blocks. This is leading
to confusion when compared with Linux bad blocks. Hence, display
"bbt reserved" when printing reserved blocks with "nand bad" command.

To acheive this, return 2 which represents reserved from nand_isbad_bbt()
instead of 1 in case of reserved blocks and catch it in cmd/nand.c.

"nand bad" command display's hexadecimal numbers, so add "0x" prefix.

Example log will show up as below.

ZynqMP> nand bad

Device 0 bad blocks:
  0x00400000
  0x16800000
  0x16c00000
  0x17000000
  0x3d800000
  0x3e400000
  0xe8400000
  0xff000000	 (bbt reserved)
  0xff400000	 (bbt reserved)
  0xff800000	 (bbt reserved)
  0xffc00000	 (bbt reserved)
  0x116800000
  0x116c00000
  0x1ff000000	 (bbt reserved)
  0x1ff400000	 (bbt reserved)
  0x1ff800000	 (bbt reserved)
  0x1ffc00000	 (bbt reserved)

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-By: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-02-27 16:28:30 +01:00
Tom Rini
2a433a5b53 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-02-27 09:11:57 -05:00
Tom Rini
fffc18d178 Merge branch '2023-02-24-include-nx51-components-in-docker-for-testing' into next
- Merge in changes to our Dockerfile so that we build and download ahead
  of time all of the components required to run the nx51 test scripts.
  This will both speed up the specific job and address failures in Azure
  where the ipk files fail to download.
2023-02-25 12:44:30 -05:00
Pali Rohár
ce0f745c36 CI: Update test/nokia_rx51_test.sh to use prebuilt images
Now that the Dockerfile creates images which have the binaries we
require included, have CI make symlinks for them and update the existing
script to support this.

Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-24 11:54:44 -05:00
Heinrich Schuchardt
ed319bad22 Dockerfile: build qemu for Nokia n900
Using a pre-built QEMU saves a lot of time when testing.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-02-24 11:54:44 -05:00
Heinrich Schuchardt
75b031ee4a Dockerfile: download binaries for Nokia RX-51
Downloading files for a test may fail if the server is offline.
It is preferable to provide the files in our Docker image.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-24 11:54:44 -05:00
Tom Rini
0024e7f72b Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-tegra 2023-02-23 17:40:18 -05:00
Tom Rini
0b58258a33 Merge branch '2023-02-23-assorted-fixes'
- btrfs bugfix, silence a bunch of gcc-12.2 linker warnings finally,
  relax one of the trace test time requirements (so CI doesn't fail due
  to test being slightly slow, but still correct), and correct env on
  MMC and checking for where GPT can be
2023-02-23 17:30:49 -05:00
Svyatoslav Ryhel
5a8fe1ee81 ARM: tegra20: implement BCT patching
This function allows updating bootloader from u-boot
on production devices without need in host PC.

Be aware! It works only with re-crypt BCT.

Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Signed-off-by: Ramin Khonsari <raminterex@yahoo.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Ramin Khonsari
327ff8e0a4 ARM: tegra30: implement BCT patching
This function allows updating bootloader from u-boot
on production devices without need in host PC.

Be aware! It works only with re-crypted BCT.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Ramin Khonsari <raminterex@yahoo.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
bab087802a ARM: tegra: crypto: extend crypto functional
Add support for encryption, decryption and signinig with
non-zero key saving backward compatibility.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
8ed2bd1d1b ARM: tegra: expose crypto module for all Tegra SoCs
Move crypto module from T20 only into common Tegra dir.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
5668c75ce9 board: tegra30: switch to updated pre-dm i2c write
Configure PMIC voltages for early stages using updated
early i2c write.

Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
e7184debf4 board: tegra124: switch to updated pre-dm i2c write
Configure PMIC for early stages using updated i2c write.

Tested-by: Thierry Reding <treding@nvidia.com> # Jetson TK1 T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
4213d52b33 ARM: tegra: create common pre-dm i2c write
This implementation allows pwr i2c writing on early SPL
stages when DM is not yet setup.

Such writing is needed to configure main voltages of PMIC
on early SPL for bootloader to boot properly.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
1a7ce63c08 ARM: tegra: add late init support
Late init function allows passing values like identifiers and
perform device specific configurations of pre-boot stage.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Maxim Schwalm
b1de4d7c6e ARM: tegra: provide default USB gadget setup
All Nvidia boards use the same manufacturer, vendor ID and product ID
for the gadgets. Make them the defaults to remove some boilerplate from
the defconfigs.

Inspired by commit e02687bda9 ("sunxi: provide default USB gadget
setup") which did the same for Allwinner boards.

Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:37 -07:00
Svyatoslav Ryhel
09ca4d8028 spi: tegra20_slink: accept any word length
Original t20 slink could work with commands only
fully divisible by 8. This patch removes such
restriction, so commands of any bitlength now
can be passed and processed.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Svyatoslav Ryhel
23d24df34c ARM: tegra: Fix Tegra PWM parent clock
Default parent clock for the PWM on Tegra is a 32kHz clock and
is unable to support the requested PWM period.

Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by
updating the parent clock for the PWM to be the PLL_P.

This commit is equivalent to Linux kernel commit:
https://lore.kernel.org/all/20221010100046.6477-1-jonathanh@nvidia.com/

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # ASUS TF201 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Svyatoslav Ryhel
678157e212 ARM: tegra30: add PLLD to pll setup
On T30 unlike T20 dsi panels are wider used on devices
and PLLD is used as DISP1 parent more often, so lets
enable it as well for this cases.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF700T T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Svyatoslav Ryhel
a81d792479 ARM: tegra: clock: add clock_decode_pair helper
Get periph clock id and its parent from device tree.
This works by looking up the peripheral's 'clocks' node and
reading out the second and fourth cells, which are the
peripheral and PLL clock numbers.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Svyatoslav Ryhel
65e02744ec ARM: tegra: clock: add clk_id_to_pll_id helper
This function allows to convert a device tree clock ID to PLL ID.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Svyatoslav Ryhel
2fafac30ef ARM: t20/t30: swap host1x and disp1 clock parents
According to mainline clock tables and TRM HOST1X
parent is PLLC, while DISP1 usually uses PLLP as
parent clock.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Svyatoslav Ryhel
fca18a2643 tegra30: clock: add EXTPERIPH
This mappings were missing for some reason.

Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23 12:55:36 -07:00
Marek Vasut
5b4acb0ff7 env: mmc: Apply GPT only on eMMC user HW partition
Apply the GPT U-Boot environment GUID type look up only on eMMC user
HW partition, do not apply the look up on eMMC boot HW partitions as
mmc_offset_try_partition() assumes either SD partitions or eMMC user
HW partition.

This fixes environment operation on systems where CONFIG_SYS_MMC_ENV_PART
is non-zero and CONFIG_SYS_REDUNDAND_ENVIRONMENT is set.

Fixes: 80105d8fd5 ("env: mmc: select GPT env partition by type guid")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-02-23 13:32:20 -05:00
Simon Glass
c1d266a781 trace: Relax test requirements
We expect the profile and bootstage to agree on timing, but when
running on slow machines there can be a larger descrepency. Increase the
tolerance to fix this.

Fixes: 9cea4797ae ("trace: Add a test")
Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-23 13:29:20 -05:00
Tom Rini
d85bc196cb x86: Pass -z execstack for EFI payload flags
To match how we link EFI executables elsewhere, and to silence a linker
warning, pass -z execstack here as well.

Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-02-23 13:29:20 -05:00
Tom Rini
57450d8661 Makefile: Link with -z noexectack
When moving to gcc-12.2 we started trying to quiet some of the new
linker warnings, that are not relevant to us. However, a
misunderstanding of the mechanics at play meant that I intentionally
omitted passing -z noexecstack to the linker, when we do need to. Add
this flag and in turn remove warnings from the linker.

Fixes: 1e1c51f8ac ("Makefile: link with --no-warn-rwx-segments")
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-23 13:29:19 -05:00
Qu Wenruo
511a1303c9 fs: btrfs: limit the mapped length to the original length
[BUG]
There is a bug report that btrfs driver caused hang during file read:

  This breaks btrfs on the HiFive Unmatched.

  => pci enum
  PCIE-0: Link up (Gen1-x8, Bus0)
  => nvme scan
  => load nvme 0:2 0x8c000000 /boot/dtb/sifive/hifive-unmatched-a00.dtb
  [hangs]

[CAUSE]
The reporter provided some debug output:

  read_extent_data: cur=615817216, orig_len=16384, cur_len=16384
  read_extent_data: btrfs_map_block: cur_len=479944704; ret=0
  read_extent_data: ret=0
  read_extent_data: cur=615833600, orig_len=4096, cur_len=4096
  read_extent_data: btrfs_map_block: cur_len=479928320; ret=0

Note the second and the last line, the @cur_len is 450+MiB, which is
almost a chunk size.

And inside __btrfs_map_block(), we limits the returned value to stripe
length, but that's depending on the chunk type:

	if (map->type & (BTRFS_BLOCK_GROUP_RAID0 | BTRFS_BLOCK_GROUP_RAID1 |
			 BTRFS_BLOCK_GROUP_RAID1C3 | BTRFS_BLOCK_GROUP_RAID1C4 |
			 BTRFS_BLOCK_GROUP_RAID5 | BTRFS_BLOCK_GROUP_RAID6 |
			 BTRFS_BLOCK_GROUP_RAID10 |
			 BTRFS_BLOCK_GROUP_DUP)) {
		/* we limit the length of each bio to what fits in a stripe */
		*length = min_t(u64, ce->size - offset,
			      map->stripe_len - stripe_offset);
	} else {
		*length = ce->size - offset;
	}

This means, if the chunk is SINGLE profile, then we don't limit the
returned length at all, and even for other profiles, we can still return
a length much larger than the requested one.

[FIX]
Properly clamp the returned length, preventing it from returning a much
larger range than expected.

Reported-by: Andreas Schwab <schwab@linux-m68k.org>
Signed-off-by: Qu Wenruo <wqu@suse.com>
2023-02-23 13:29:19 -05:00
Marek Vasut
b684ec8efe usb: dwc3-uniphier: Select PHY
Make sure the PHY subsystem is activated for the uniphier DWC3 glue
logic, as it depends on PHY implementation there.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-02-23 11:33:00 -05:00
Tom Rini
97b92f7d17 Merge branch 'next' of git://source.denx.de/u-boot-usb into next
- dwc3-generic rework and then switch uniphier to it
2023-02-22 18:21:48 -05:00
Kunihiko Hayashi
aeb8b59f2f uniphier_defconfig: Disable USB_XHCI_DWC3
Replacing with dwc3-generic, no need USB_XHCI_DWC3 anymore.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Kunihiko Hayashi
ec01e0ba2c usb: dwc3-uniphier: Use dwc3-generic instead of xhci-dwc3
dwc3-uniphier depends on xhci-dwc3 framework, however, it is preferable
to use dwc3-generic.

This driver calls the exported dwc3-generic functions and redefine
the SoC-dependent operations to fit dwc3-generic.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Kunihiko Hayashi
7a888de4b5 phy: socionext: Add UniPhier USB3 PHY driver
Add USB3 PHY driver support to control clocks and resets needed to enable
PHY. The phy_ops->init() and exit() control PHY clocks and resets only,
and clocks and resets for the controller and the parent logic are enabled
in advance.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Kunihiko Hayashi
26dd38af85 clk: uniphier: Add missing USB SS-PHY clocks
The USB SS-PHY needs its own clock, however, some clocks don't have
clock gates. Define missing clock entries for the PHY as reference
clock.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Kunihiko Hayashi
1c866de57b reset: uniphier: Add USB glue reset support
Add reset control support in USB glue logic. This needs to control
the external clocks and resets for the logic before accessing the
glue logic.

The USB dm tree when using dwc3-generic is the following:

   USB glue
     +-- controller       (need controller-reset)
     +-- controller-reset (need syscon-reset)
     +-- phy

The controller needs to deassert "controller-reset" in USB glue before
the controller registers are accessed. The glue needs to deassert
"syscon-reset" before the glue registers are accessed.

The glue itself doesn't have "syscon-reset", so the controller-reset
controls "syscon-reset" instead.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Kunihiko Hayashi
211a066876 usb: dwc3-generic: Add the size of regs property to glue structure
Add the size of regs property to the glue structure to correctly
specify the register region to map.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Kunihiko Hayashi
ef2313b8a2 usb: dwc3-generic: Export glue structures and functions
In order to allow external SoC-dependent glue drivers to use dwc3-generic
functions, push the glue structures and export the functions to a header
file.

The exported structures and functions are:

- struct dwc3_glue_data
- struct dwc3_glue_ops
- dwc3_glue_bind()
- dwc3_glue_probe()
- dwc3_glue_remove()

The SoC-dependent glue drivers can only define their own wrapper driver
and specify these functions. The drivers can also add their own compatible
strings and configure functions.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Kunihiko Hayashi
7c71c684ce usb: dwc3-generic: Add clock initialization in child DT node
Same as the reset cotnrol, should add a clock initialization in child DT
node, if the glue node doesn't have any clocks.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Kunihiko Hayashi
f7b7c72133 usb: dwc3-generic: Allow different controller DT node pattern
The most of devicetree has the following USB node structure.
The controller node is placed as a child node of the glue node.
Current dwc3-generic driver works on this premise.

    glue {
        /* glue node */
	usb {
            /* controller node */
	};
    };

However, UniPhier original devicetree has the following USB node structure.
The controller node is separately placed from the glue node.

    usb {
        /* controller node */
    };
    glue {
        /* glue node */
    };

In dwc_glue_bind(), this patch provides .glue_get_ctrl_dev() callback to
get such a controller node and binds the driver related to the node.

If this callback isn't defined, dwc_glue_bind() looks for the controller
nodes from the child nodes, as before.

Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Marek Vasut
c6583354b7 usb: dwc3: Look up reference clock DT phandle in both controller DT nodes
There are currently four disparate placement possibilities of DWC3
reference clock phandle in SoC DTs:
- in top level glue node, with generic subnode without clock (ZynqMP)
- in top level generic node, with no subnode (i.MX8MQ)
- in generic subnode, with other clock in top level node (i.MX8MP)
- in both top level node and generic subnode (Rockchip)

Cover all the possibilities here by looking into both nodes, start
with the top level node as that seems to be used in majority of DTs
to reference the clock.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2023-02-22 19:40:11 +01:00
Tom Rini
8c39999acb Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-usb
- DWC3 bugfix
2023-02-22 13:36:29 -05:00
Tom Rini
504feed905 Merge https://source.denx.de/u-boot/custodians/u-boot-socfpga
- chameleonv3 updates
2023-02-22 09:28:03 -05:00
Paweł Anikiel
52b8fca717 chameleonv3: Convert CONFIG_SPL_MAX_SIZE to Kconfig
This file was missed during the conversion process. Add the symbol to
defconfig.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22 00:28:39 +01:00
Paweł Anikiel
48c172c2f8 arm: dts: chameleonv3: Add 270-2 variant
Add devicetree for chameleonv3 with the 270-2I2-D11E variant of the
Mercury+ AA1 module

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22 00:28:39 +01:00
Paweł Anikiel
9c107ab42b arm: dts: chameleonv3: Rename chameleonv3.dts to .dtsi
This file is included by the different chameleonv3 variants. Change the
name to .dtsi.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22 00:28:39 +01:00
Paweł Anikiel
1d222089f0 arm: dts: chameleonv3: Override chameleonv3 bitstream names
Set the bitstream name per Chameleon variant. This allows the same
boot filesystem with all bitstream variants to be used on different
boards.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22 00:28:39 +01:00
Paweł Anikiel
0f3c8fe392 socfpga: chameleonv3: Move environment to a text file
Move the environment to an easily editable text file in the boot
partition

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22 00:28:39 +01:00
Paweł Anikiel
8f1b333457 socfpga: chameleonv3: Enable ext4 in SPL
Allow SPL to boot from an ext4 filesystem.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22 00:28:39 +01:00
Venkatesh Yadav Abbarapu
237d1f60b1 usb: dwc3: Use the devm_gpiod_get_optional() API for reset gpio
As the "reset-gpios" property is optional, don't return the
error and just skip the gpio reset sequence.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
2023-02-22 00:28:05 +01:00