Commit graph

281 commits

Author SHA1 Message Date
Claudiu Beznea
068d4c0a11 pinctrl: at91: add slewrate support for SAM9X60
Add slew rate support for SAM9X60 pin controller.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2019-04-09 09:28:50 +03:00
Claudiu Beznea
be6e24054d pinctrl: at91: add compatibles for SAM9X60 pin controller
Add compatibles for SAM9X60 pin controller.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2019-04-09 09:28:50 +03:00
Claudiu Beznea
1a6a82882e pinctrl: at91: add drive strength support for SAM9X60
Add drive strength support for SAM9X60 pin controller.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2019-04-09 09:28:50 +03:00
Claudiu Beznea
04d4ec9c57 pinctrl: at91: add option to use drive strength bits
SAM9X60 uses high and low drive strengths. To implement this, in
at91_pinctrl_mux_ops::set_drivestrength we need bit numbers of
drive strengths (1 for low, 2 for high), thus change the code to
allow the usage of drive strength bit numbers.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2019-04-09 09:28:50 +03:00
David Wu
502980914b pinctrl: rockchip: Add 32bit writing function for rk3288 gpio0 pinctrl
There are no higher 16 writing corresponding bits for pmu_gpio0's
iomux/drive/pull at rk3288, need to read the value from register
firstly. Add the flag to distinguish it from normal registers.

Signed-off-by: David Wu <david.wu@rock-chips.com>
2019-03-29 09:24:44 +01:00
Peng Fan
78814467a0 pinctrl: add imx8m driver
Add i.mx8m pinctrl driver.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-03-13 09:14:35 +01:00
Hiroyuki Yokoyama
65eef78cdb pinctrl: renesas: r8a77990: Reivse USB ID pin name
Since the datasheet Rev.1.00 has an error about the USB ID pin name,
this patch revises it.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04 01:46:05 +01:00
Hiroyuki Yokoyama
bf93f24c30 pinctrl: renesas: r8a77990: Fix MOD_SEL0 bit3 when using TX0
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50,
the MOD_SEL0 bit3 is set to 0 when TX0_A pin function is selected,
and the MOD_SEL0 bit3 is set to 1 when TX0_B pin function is
selected.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04 01:46:05 +01:00
Hiroyuki Yokoyama
4892e8301b pinctrl: renesas: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N
According to the R-Car Gen3 Hardware Manual Rev.1.50, the MOD_SEL0
bit16 is set to 0 when NFALE_A and NFRB_N_A pin functions are
selected.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04 01:46:05 +01:00
Hiroyuki Yokoyama
ef083ecf90 pinctrl: renesas: r8a77990: Fix MOD_SEL0 bit2 when using RX2,TX2 and SCK2
According to the R-Car Gen3 Hardware Manual Rev 1.50, the MOD_SEL0
bit2 is set when RX2_{A,B}, TX2_{A,B} and SCK2_A pin functions are
selected.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04 01:46:05 +01:00
Hiroyuki Yokoyama
8b5e96d80a pinctrl: renesas: r8a77990: Fix rename RTSx_N_TANS_x to RTSx_N_x
This patch fixes the allocation name "RTSx_N_TANS_x" of IPSR /
 MOD_SEL0/1 of r8a77990 to "RTSx_N_x". This information was
confirmed in the R-Car Gen3 Hardware Manual Rev.1.50.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04 01:46:05 +01:00
Hiroyuki Yokoyama
0b9af5883b pinctrl: renesas: Fix r8a779{6,65} rename sel_ndfc to sel_ndf
This patch fixes the allocation name "sel_ndfc" of MOD_SEL2[22]
of r8a7796 / r8a77965 to "sel_ndf". This information was confirmed
in the R-Car Gen3 Hardware Manual Rev.1.50.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04 01:46:05 +01:00
Hiroyuki Yokoyama
6eff90c3a5 pinctrl: renesas: Remove r8a779{5,6,65} CC5_OSCOUT of IP17
This patch removes CC5_OSCOUT assignment of IP17[3:0] of r8a7795
 / r8a7796 / r8a77965. This information was confirmed in the R-Car
Gen3 Hardware Manual Rev.1.50.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04 01:46:05 +01:00
Hiroyuki Yokoyama
6098f41e23 pinctrl: renesas: Fix r8a779{5,6,65} rename sel_adg_ to sel_adg
This patch fixes to the correct names, and "_" is not include after
"adg" for r8a7795/r8a7796/r8a77965. This information was confirmed
in the R-Car Gen3 Hardware Manual Rev.1.50.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04 01:46:05 +01:00
Hiroyuki Yokoyama
9e4b529c5f pinctrl: renesas: Fix r8a779{5,6,65} assign to GP7_03/02 of GPSR7
This patch is change the bit assignment of "HDMI1_CEC" to "GP7_03",
and "HDMI0_CEC" to "GP7_02". This information was confirmed in the
R-Car Gen3 Hardware Manual Rev.1.50.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04 01:46:05 +01:00
Marek Vasut
7fef459c3c pinctrl: renesas: Drop def_bool per SoC
Drop per SoC def_bool on each driver, since this is now implied by
SoC Kconfig option instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25 16:07:41 +01:00
Philipp Tomsich
5a127325f0 pinctrl: Kconfig: fix missing include of rockchip/Kconfig
After the merge of the new, generic pinctrl-code, the include for
rockchip/Kconfig was missing.  Add it here, so we can select the
pinctrl-driver for SPL.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:14 +01:00
Philipp Tomsich
efc4677171 pinctrl: Kconfig: sort includes alphabetically
To make adding new subdirectories easier, let's enforce alphabetical
ordering of the includes of Kconfig files in the respective
subdirectories.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:14 +01:00
David Wu
96f73e0d24 pinctrl: rockchip: Clean the unused rockchip pinctrl drivers
If we used the pinctrl-rockchip driver, these code is not needed,
so remove them.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:11 +01:00
David Wu
e7ae4cf27a pinctrl: rockchip: Add common rockchip pinctrl driver
Use this driver to fit all Rockchip SOCs and to support
the desired pinctrl configuration via DTS.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:11 +01:00
Simon Glass
3dbfe5ae61 rockchip: rk3288: Add i2s pinctrl and clock support
Add support for setting pinctrl and clock for I2S on rk3288. This allows
the sound driver to operate. These settings were created by rkmux.py

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:10 +01:00
Tom Rini
748ad078ee For 2019.04
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Merge tag 'u-boot-imx-20190129' of git://git.denx.de/u-boot-imx

For 2019.04
2019-01-30 07:22:12 -05:00
Jerome Brunet
c4c726c26b pinctrl: meson: add pinconf support
Adding pinconf support is necessary to enable boot from SPI
without breaking the eMMC. When booting from SPI, the ROM code
leave pull downs on the eMMC pad.

We need to set pinconf provided in DT to solve this

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: added missing comma in pinctrl-meson-axg-pmx.c]
2019-01-29 11:19:15 +01:00
Ye Li
11a1c27eb4 pinctrl: imx: Fix select input issue
The pinctrl supports to set any bit in input register on iMX6 if
the MSB of input value is 0xff. But the driver uses signed int for
input value, so when executing the codes below, it won't meet.
Because this is arithmetic right shift.

    if (input_val >> 24 == 0xff)

Fix the issue by changing the input_val, config_val and mux_mode to u32.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Horatiu Vultur
5c31ce36e3 pinctrl: mscc: Add gpio and pinctrl for Serval SoC family.
The Serval SoC family has 32 pins. Currently there is no
support for Serval in Linux kernel.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-23 18:28:09 +01:00
Horatiu Vultur
177c07f829 pinctrl: mscc: Add gpio and pinctrl for Servalt SoC family.
The Servalt SoC family has 36 pins. Currently there is not support
for Servalt pinctrl in Linux kernel.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-23 18:27:26 +01:00
Chris Packham
cb4d1bbe51 pinctrl: Kconfig: spelling fixes
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-18 09:16:15 -05:00
Horatiu Vultur
051de9b3eb pinctrl: mscc: Add gpio and pinctrl for Jaguar2 SOC family
The Jaguar2 SOC family has 63 gpio pins therefore I extended mscc-common
to support new numbe of pins and remove any platform dependency from
mscc-common.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-16 13:56:43 +01:00
Lukasz Majewski
b6a6238f04 Revert "dm: pinctrl: Prevent (re-)configuring pins when already done before relocation"
This reverts commit a7f4b4b344.

As reported by Alex Kiernan the above optimization introduces a
regression in the below use case where:

1. Device has defined 'u-boot,dm-spl' property (@ eMMC DTS node)

2. The device downloads its MLO/SPL via UART (not eMMC - the eMMC pinmux
pins are NOT probed/configured in MLO/SPL).

3. The loaded via UART MLO/SPL wants to load Linux from eMMC. In this case
the DM core and pinctrl uclass checks 'u-boot,dm-spl' and don't
configure pins (as it thinks that those were initialized in MLO/SPL).

As we are very close to release - please revert this commit.

Reported-by: Alex Kiernan <alex.kiernan@gmail.com>
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-11 10:03:42 -05:00
Philipp Tomsich
33502f371d rockchip: rk3399: fix missing braces in full pinctrl
Braces around the error-case for rk3399_pinctrl_set_pin_pupd lead to
an unconditional (and unintended) return from the function without it
ever setting pin-configurations.

Fix it.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-06 15:26:31 +01:00
Christoph Muellner
8188c83cfa rockchip: rk3399: Add Kconfig option for full pinctrl driver
This patch adds a Kconfig option to enable the full pinctrl driver
for the RK3399. This flag needs to be enabed in order to get the
features of the full pinctrl driver compiled in (i.e. a .set_state()
callback).

Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-02 22:39:12 +01:00
Christoph Muellner
600888110d rockchip: rk3399: Add improved pinctrl driver.
The current pinctrl driver for the RK3399 has a range of qulity issues.
E.g. it only implements the .set_state_simple() callback, it
does not parse the available pinctrl information from the DTS
(instead uses hardcoded values), is not flexible enough to cover
devices without 'interrupt' field in the DTS (e.g. PWM),
is not written generic enough to make code reusable among other
rockchip SoCs...

This patch addresses these issues by reimplementing the whole driver
from scratch using the .set_state() callback.
The new implementation covers all featurese of the old code
(i.e. it supports pinmuxing and pullup/pulldown configuration).

This patch has been tested on a RK3399-Q7 SoM (Puma).

Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-02 22:39:04 +01:00
Christoph Muellner
5ff7768892 dm: pinctrl: Add pinctrl_decode_pin_config_dm().
pinctrl_decode_pin_config_dm() is basically a feature-equivalent
implementation of pinctrl_decode_pin_config(), which operates
on struct udevice devices and uses the dev_read_*() API.

Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-02 22:38:44 +01:00
Tom Rini
522e035441 imx for 2019.01
- introduce support for i.MX8M
 - fix size limit for Vhybrid / pico boards
 - several board fixes
 - w1 driver for MX2x / MX5x
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Merge tag 'u-boot-imx-20190101' of git://www.denx.de/git/u-boot-imx

imx for 2019.01

- introduce support for i.MX8M
- fix size limit for Vhybrid / pico boards
- several board fixes
- w1 driver for MX2x / MX5x
2019-01-01 10:01:00 -05:00
Lukasz Majewski
f0b73d9707 ARM: vybrid: Provide pinctrl driver for Vybrid (vf610)
This implementation comply with other iMX devices pinctrl drivers already
available in U-boot.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-01-01 14:12:18 +01:00
Lukasz Majewski
a7f4b4b344 dm: pinctrl: Prevent (re-)configuring pins when already done before relocation
This commit prevents from re-configuring pins if those were configured
before relocation.

Some pins - like UART or DDR must be setup before relocation
(as they have 'u-boot,dm-pre-reloc' property set in DTS). Without this
change, those pins are re-configured after relocation (pre_reloc_only = 0,
so we do not "continue").
Such behavior may be a problem for DDR PAD configuration, as they might
be already leveled/tuned with original setup).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2018-12-26 21:21:07 -05:00
Gregory CLEMENT
53bdae2418 pinctrl: mscc: Add gpio and pinctrl driver for MSCC MIPS SoCs (VcoreIII based)
This driver supports the pin and gpio controller found in the Ocelot and
Luton SoCs.

The driver was inspired from the pinctrl driver in Linux, but was
simplified and was modified to allow supporting an other SoCs (Luton).

For Ocelot and Luton the controller is the same, only the pins to program
differ.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
[changed to only descend into mscc/ dependent on CONFIG_PINCTRL_MSCC]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19 15:23:01 +01:00
Tom Rini
10d3e90f46 Two fixes for the Amlogic Pinctrl driver :
- bad usage of clrsetbits_le32
 - bad pin definition for AXG Family
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Merge tag 'u-boot-amlogic-20181207' of git://git.denx.de/u-boot-amlogic

Two fixes for the Amlogic Pinctrl driver :
- bad usage of clrsetbits_le32
- bad pin definition for AXG Family
2018-12-07 19:01:09 -05:00
Patrice Chotard
530b63c228 pinctrl: stm32: Update stm32_pinctrl_get_gpio_dev()
Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must
be updated.

stm32_pinctrl_get_gpio_dev() returns from a given pin selectors
the corresponding bank gpio device and the gpio_offset inside this
gpio bank.

Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-07 08:13:48 -05:00
Patrice Chotard
043550415b pinctrl: stm32: Move gpio_dev list filling outside probe()
Move gpio_dev list filling outside probe() to speed-up U-boot
boot sequence execution. This list is populated only when needed.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-07 08:13:47 -05:00
Carlo Caione
139ebe9eb9 pinctrl: meson: axg: Fix GPIO pin offsets
The pin number (first and last) in the bank definition is missing the
pin base offset shifting. This is causing a miscalculation when
retrieving the register and pin offsets in the GPIO driver causing the
'gpio' command to drive the wrong pins / GPIOs in the second GPIO chip
(the AO bank is driven correctly because the shifting is already 0).

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-12-07 11:01:09 +01:00
Benjamin Gaignard
075b0185b6 pinctrl: stm32: make pinctrl use hwspinlock
Protect configuration registers with a hardware spinlock.

If a hwspinlock is defined in the device-tree node used it
to be sure that none of the others processors on the SoC could
change the configuration at the same time.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-06 23:26:33 -05:00
Carlo Caione
fb19c7bade pinctrl: meson: Fix GPIO direction registers access
The macros used to set the direction of the GPIO pins are misused,
resulting in a wrong behavior when trying to read the GPIO input level
from U-Boot.

A better macro is also used when setting the output direction.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-12-05 10:39:17 +01:00
Tom Rini
93e72ac472 Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
 - net: designware: add meson meson compatibles
 - Amlogic Meson cleanup for AXG SoC support
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Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogic

Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
- net: designware: add meson meson compatibles
- Amlogic Meson cleanup for AXG SoC support
2018-11-29 15:16:58 -05:00
Ryder Lee
59a8fef342 pinctrl: MediaTek: add pinctrl driver for MT7623 SoC
This patch adds pinctrl support for MT7623 SoC. And most of the
structures are used to hold the hardware configuration for each
pin.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Tested-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28 23:04:52 -05:00
Ryder Lee
01aa9d1d54 pinctrl: MediaTek: add pinctrl driver for MT7629 SoC
This patch adds pinctrl support for MT7629 SoC. The IO core found on
the SoC has the registers for pinctrl, pinconf and gpio mixed up in
the same register range.  Hence the driver also implements the gpio
functionality through UCLASS_GPIO.

This also creates a common file as there might be other chips that use
the same binding and driver, then being a little more abstract could
help in the long run.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28 23:04:52 -05:00
Jerome Brunet
8587839f19 pinctrl: meson: add axg support
This adds support for the Amlogic AXG SoC pinctrl and GPIO controller
using a specific set of pinctrl functions which differs from the GX SoCs.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Jerome Brunet
2f9a38b50f pinctrl: meson: select generic pinctrl
Meson pinctrl needs generic pinctrl, rather than depending on it
select it

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Jerome Brunet
7c9dcfed50 pinctrl: meson: rework gx pmx function
In preparation of supporting the new Amlogix AGX SoCs, we need to move
the Amlogic GX pinmux functions out of the common code to be able to
add a different set of SoC specific pinmux functions for AXG.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Patrice Chotard
21e23aaff6 pinctrl: sandbox: Add get_pin_muxing ops support
Add get_pin_mux ops support to display the pin muxing
description of the sandbox_pins[]

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-16 16:51:57 -05:00