Commit graph

2798 commits

Author SHA1 Message Date
Tom Rini
d5dbc661c3 i.MX
----
 
 - mx7ulp : fix  WDOG
 - imx8 : Phytec
 - USB3 support for i.MX8
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277
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Merge tag 'u-boot-imx-20210717' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

i.MX
----

- mx7ulp : fix  WDOG
- imx8 : Phytec
- USB3 support for i.MX8

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277
2021-07-17 10:52:21 -04:00
Simon Glass
9d9bec216d sandbox: net: Ensure host name is always a valid string
At present if ifname is exactly IFNAMSIZ characters then it will result
in an unterminated string. Fix this by using strlcpy() instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 316358)
Acked-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-15 18:42:05 -04:00
Tim Harvey
668e205098 net: add support for KSZ9477/KSZ9897/KSZ9567 GbE switch
The Microchip KSZ9477/KSZ9897/KSZ9567 7-Port Gigabit Ethernet Switches
support SGMII/RGMII/MII/RMII with register access via SPI, I2C, or MDIO.

This driver currently supports I2C register access but SPI or MDIO register
access can be easily added at a later time.

Tagging is not implemented and instead the active port is tracked to
avoid needing a tag to store port information.

This was tested with the imx8mm-venice-gw7901 board which has a
KSZ9897S switch with an IMX8MM FEC MAC master connected via RGMII_ID.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-10 18:12:42 +02:00
Tim Harvey
87550a814e net: fec: add set_promisc function
Enabling promiscuous mode is necessary if FEC is the master of a DSA
switch driver where each port has their own MAC address.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-10 18:12:41 +02:00
Tim Harvey
69c81d6546 net: fec: set phy_of_node properly for fixed-link phy
If the FEC is connected to a fixed-link (upstream switch port for
example) the phy_of_node should be set to the fixed-link node
so that speed and other properties can be found properly.

In addition fix a typo in the debug string.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-10 18:12:41 +02:00
Tim Harvey
b247fa7b17 net: fec: use device sequence vs index when fetching fec
When using uclass_get_device* to get the FEC device we need to use
device sequence instead of index into UCLASS_ETH. In systems where for
example a I2C based DSA switch exists it will probe before the FEC
master and its ports will be registered first and have the first
indexes yet the FEC's sequence comes from the device-tree alias.

Take for example the imx8mm-venice-gw7901 board which has an i2c based
DSA switch:

u-boot=> net list
eth1 : lan1 00:0d:8d:aa:00:2f
eth2 : lan2 00:0d:8d:aa:00:30
eth3 : lan3 00:0d:8d:aa:00:31
eth4 : lan4 00:0d:8d:aa:00:32
eth0 : ethernet@30be0000 00:0d:8d:aa:00:2e active

Thus in this case uclass_get_device(UCLASS_ETH, 0, &dev) returns lan1
which is wrong but uclass_get_device_seq(UCLASS_ETH, 0, &dev) returns
ethernet@30be000 which is correct.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-10 18:12:41 +02:00
Tom Rini
ec6b37cef4 ppc: Remove T4160RDB board
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM.  Remove it.  As this is the last
ARCH_T4160 platform, remove that support as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 19:52:24 -04:00
Tom Rini
6c3d99335c ppc: Remove T1023RBD boards and T1024RDB_SECURE_BOOT
These boards have not been converted to CONFIG_DM_PCI by the deadline
and is also missing conversion to CONFIG_DM.  Remove them.  As this is
the only ARCH_T1023 platform left, remove that support as well.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 19:52:23 -04:00
Tom Rini
9b7993bba9 m68k: Remove M5475x boards
These board has not been converted to CONFIG_DM_PCI by the deadline.
Remove them.  As this is the last of the mcf547x_8x family of boards,
remove that support as well.

Cc: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 19:52:22 -04:00
Patrick Delaunay
036e3622bf net: dwc_eth_qos: cosmetic: remove unused define EQOS_DESCRIPTOR_ALIGN
Remove the define EQOS_DESCRIPTOR_ALIGN unused since the
commit 6f1e668d96 ("net: dwc_eth_qos: Pad descriptors to cacheline size")

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06 05:22:41 +03:00
Vladimir Oltean
c442850768 net: enetc: propagate the return code from phy_startup() to eth_ops::start
Make sure that errors in the PHY driver .startup() method, such as no
link, are propagated and not ignored.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06 05:22:41 +03:00
Vladimir Oltean
71346a8486 net: enetc: force the RGMII MAC speed/duplex instead of using in-band signaling
The RGMII spec supports optional in-band status reporting for the speed
and duplex negotiated on the copper side, and the ENETC driver enables
this feature by default.

However, this does not work when the PHY does not implement the in-band
reporting, or when there is a MAC-to-MAC connection described using a
fixed-link. In that case, it would be better to disable the feature in
the ENETC MAC and always force the speed and duplex to the values that
were negotiated and retrieved over MDIO once the autoneg is finished.
Since this works always, we just do it unconditionally and drop the
in-band code.

Note that because we need to wait for the autoneg to complete, we need
to move enetc_setup_mac_iface() after phy_startup() returns, and then
pass the phydev pointer all the way to enetc_init_rgmii().

The same considerations have led to a similar Linux driver patch as well:
https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c76a97218dcbb2cb7cec1404ace43ef96c87d874

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06 05:22:41 +03:00
Vladimir Oltean
cd8817ac73 net: enetc: require a PHY device when probing
Given that even a fixed-link has an associated phy_device, there is no
reason to operate in a mode when dm_eth_phy_connect fails.

Remove the driver checks for a NULL priv->phy and just return -ENODEV
when that happens.

Copyright updated according to corporate requirements.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06 05:22:41 +03:00
Andre Przywara
c08d4d792a net: smc911x: Determine bus width at runtime
The SMC911x Ethernet MACs can be integrated using a 16 or 32-bit bus.
The driver needs to know about this choice, which is the reason for us
having a Kconfig symbol for that.

Now this bus width is already described using a devicetree property, and
since the driver is DM compliant and is using the DT now, we should query
this at runtime. We leave the Kconfig choice around, in case the DT is
missing this property.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06 05:22:41 +03:00
Andre Przywara
f26c9d7fed net: smc911x: Drop redundant CONFIG_SMC911X_16_BIT Kconfig symbol
The SMC911x Ethernet driver needs to know which accessor functions it
can use to access the MMIO registers. For that reason we have a Kconfig
choice between 16 and 32-bit bus width.

Since it's only those two options that we (and the Linux kernel)
support, and there does not seem to be any evidence of another bus
width anywhere, limit the Kconfig construct to a simple symbol.

This simplifies the code and allows a later rework to be much easier.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06 05:22:41 +03:00
Radu Pirea (NXP OSS)
3ef2050a6a phy: add nxp tja1103 phy driver
Add nxp tja1103 phy driver.

Signed-off-by: Radu Pirea (NXP OSS) <radu-nicolae.pirea@oss.nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06 05:22:41 +03:00
Tom Rini
6b69f15fd6 Xilinx changes for v2021.10
clk:
 - Add driver for Xilinx Clocking Wizard IP
 
 fdt:
 - Also record architecture in /fit-images
 
 net:
 - Fix plat/priv data handling in axi emac
 - Add support for 10G/25G speeds
 
 pca953x:
 - Add missing dependency on i2c
 
 serial:
 - Fix dependencies for DEBUG uart for pl010/pl011
 - Add setconfig option for cadence serial driver
 
 watchdog:
 - Add cadence wdt expire now function
 
 zynq:
 - Update DT bindings to reflect the latest state and descriptions
 
 zynqmp:
 - Update DT bindings to reflect the latest state and descriptions
 - SPL: Add support for ECC DRAM initialization
 - Fix R5 core 1 handling logic
 - Enable firmware driver for mini configurations
 - Enable secure boot, regulators, wdt
 - Add support xck devices and 67dr
 - Add psu init for sm/smk-k26 SOMs
 - Add handling for MMC seq number via mmc_get_env_dev()
 - Handle reserved memory locations
 - Add support for u-boot.itb generation for secure OS
 - Handle BL32 handoffs for secure OS
 - Add support for 64bit addresses for u-boot.its generation
 - Change eeprom handling via nvmem aliases
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Merge tag 'xilinx-for-v2021.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2021.10

clk:
- Add driver for Xilinx Clocking Wizard IP

fdt:
- Also record architecture in /fit-images

net:
- Fix plat/priv data handling in axi emac
- Add support for 10G/25G speeds

pca953x:
- Add missing dependency on i2c

serial:
- Fix dependencies for DEBUG uart for pl010/pl011
- Add setconfig option for cadence serial driver

watchdog:
- Add cadence wdt expire now function

zynq:
- Update DT bindings to reflect the latest state and descriptions

zynqmp:
- Update DT bindings to reflect the latest state and descriptions
- SPL: Add support for ECC DRAM initialization
- Fix R5 core 1 handling logic
- Enable firmware driver for mini configurations
- Enable secure boot, regulators, wdt
- Add support xck devices and 67dr
- Add psu init for sm/smk-k26 SOMs
- Add handling for MMC seq number via mmc_get_env_dev()
- Handle reserved memory locations
- Add support for u-boot.itb generation for secure OS
- Handle BL32 handoffs for secure OS
- Add support for 64bit addresses for u-boot.its generation
- Change eeprom handling via nvmem aliases
2021-07-01 08:57:23 -04:00
Tom Rini
6d0453d889 Prepare v2021.07-rc5
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Merge tag 'v2021.07-rc5' into next

Prepare v2021.07-rc5

# gpg: Signature made Mon 28 Jun 2021 03:39:36 PM EDT
# gpg:                using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C
# gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate]

# Conflicts:
#	configs/am64x_evm_r5_defconfig
2021-06-28 16:22:13 -04:00
Ashok Reddy Soma
53b2af18ca net: xilinx: axi_emac: Add support for 10G/25G AXI ethernet
Add support for 10G/25G (XXV) high speed ethernet. This Makes use of
the exiting AXI DMA, similar to 1G.

Signed-off-by: Alessandro Temil <atemil@waymo.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-28 09:08:20 +02:00
Ashok Reddy Soma
215f2064c3 net: xilinx: axi_emac: Cleanup of of_to_plat()
There are lot of accesses to priv data in of_to_plat(), which is incorrect.
Create a platform data structure and use it in of_to_plat(), then copy all
platform data to priv data in probe.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-28 09:08:20 +02:00
Tim Harvey
54c321f9de net: octeontx: smi: use dt live tree API
clean up octeontx_smi_probe by using the live-tree API.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-06-18 11:29:17 +03:00
Heinrich Schuchardt
02036d90ec net: sun8i-emac: fix MDIO frequency
Commit 4f0278dac5 ("net: sun8i-emac: Lower MDIO frequency") leads to
network failure on the OrangePi PC.

    => dhcp
    sun8i_emac_eth_start: Timeout

According to the commit message the change of the MDIO frequency is only
required for external PHYs.

Fixes: 4f0278dac5 ("net: sun8i-emac: Lower MDIO frequency")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-06-18 11:29:17 +03:00
Jassi Brar
eab447b2b5 net: synquacer: Add netsec driver
Add SynQuacer's NETSEC GbE controller driver.
Since this driver will load the firmware from SPI NOR flash,
this depends on CONFIG_SYNQUACER_SPI=y.

Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-06-18 11:29:17 +03:00
Daniil Stas
f024e0b208 net: dwc_eth_qos: Revert some changes of commit 3a97da12ee
Revert some changes of commit 3a97da12ee ("net: dwc_eth_qos: add dwc
eqos for imx support") that were probably added by mistake.

One of these changes can lead to received data corruption (enabling
FUP and FEP bits). Another causes invalid register rxq_ctrl0 settings
for some platforms. And another makes some writes at unknown memory
location.

Fixes: 3a97da12ee ("net: dwc_eth_qos: add dwc eqos for imx support")
Signed-off-by: Daniil Stas <daniil.stas@posteo.net>
Cc: Ye Li <ye.li@nxp.com>
Cc: Fugang Duan <fugang.duan@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>

Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-06-18 11:29:17 +03:00
Daniil Stas
07292f8e51 net: dwc_eth_qos: Fix needless phy auto-negotiation restarts
Disabling clk_ck clock leads to link up status loss in phy, which
leads to auto-negotiation restart before each network command
execution.

This issue is especially big for PXE boot protocol because of
auto-negotiation restarts before each configuration filename trial.

To avoid this issue don't disable clk_ck clock after it was enabled.

Signed-off-by: Daniil Stas <daniil.stas@posteo.net>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>

Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-06-18 11:29:17 +03:00
Tim Harvey
7001863596 net: e1000: do not attempt to set hwaddr for i210 without FLASH
commit f1bcad22dd ("net: e1000: add support for writing to EEPROM")
adds support for storing hwaddr in EEPROM however i210 devices do not
support this and thus results in errors such as:
Warning: e1000#0 failed to set MAC address'

Check if a flash device is present and if not return -ENOSYS indicating
this is not supported.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-06-18 11:29:17 +03:00
Hou Zhiqiang
3e1848778c Fix a memory leak issue in the RX port initialization.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-06-18 11:29:17 +03:00
Aleksandar Gerasimovski
50dae8eb3a net: tsec: add option to set device max-speed via dts
Current tsec adapter sets adapter gigabit capabilities by default, and in
reality this must not always be the case.
It is possible that tsec adapter is used for 100Mbps connection, and in
this case setting 1000Mbps capabilities can lead to some side effects such
longer autoneg process.

In our ls102x designs this problem leads to long autoneg times (> 4 sec)
in case board rgmii link is 100Mbps capable only.
Limiting the rgmii link capabilities provides faster and smoother
link establishment.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17 11:46:11 +05:30
Chaitanya Sakinam
ff64e9a9f0 armv8: ls1012a: Pass PPFE firmware to Linux through FDT
Read Linux PPFE firmware from flash partition and pass it to Linux through
FDT entry. So that we can avoid placing PPFE firmware in Linux rootfs.
(FDT may increase at max by 64KB)

Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
Signed-off-by: Anji J <anji.jagarlmudi@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17 11:46:11 +05:30
Sean Anderson
6e33eba59f clk: Allow force setting clock defaults before relocation
Since 291da96b8e ("clk: Allow clock defaults to be set during re-reloc
state for SPL only") it has been impossible to set clock defaults before
relocation. This is annoying on boards without SPL, since there is no way
to set clock defaults before U-Boot proper. In particular, the aisram rate
must be changed before relocation on the K210, since U-Boot will hang if we
try and change the rate while we are using aisram.

To get around this, extend the stage parameter to allow force setting
defaults, even if they would be otherwise postponed for later. A device
tree property was decided against because of the concerns in the original
commit thread about the overhead of repeatedly parsing the device tree.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-17 09:40:57 +08:00
Mian Yousaf Kaukab
864c3dbc0a ls1012a: net: pfe: remove pfe stop from bootcmd
When using bootefi to boot a EFI binary, u-boot is supposed to
provide networking service for EFI application. Currently, 'pfe stop'
command is called from bootcmd before running bootefi. As a result
network stops working for EFI applications and console is flooded with
"Rx pkt not on expected port" messages.

Implement board_quiesce_devices() for ls1012a boards and call
pfe_command_stop() from it instead of calling 'pfe stop' from
*_bootcmd and bootcmd.

Tested-by: Anji Jagarlmudi <anji.jagarlmudi@nxp.com>
Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
[Fixed checkpatch space error]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-16 18:14:08 +05:30
Patrick Delaunay
0d1ab576f2 net: luton: remove address translation after ofnode_read_resource
Removed call of ofnode_translate_address() after ofnode_read_resource
in luton_switch.c:luton_probe(); it is unnecessary since
the commit feb7ac457c ("dm: core: Add address translation in
fdt_get_resource").

Fixes: feb7ac457c ("dm: core: Add address translation in fdt_get_resource")
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reported-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-06-05 07:35:47 -06:00
Tom Rini
aee18604e2 net: Remove ne2000 driver
With the last user of this driver removed, remove the driver.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-05-25 12:40:16 -04:00
Marcin Wojtas
d24efc621c net: mvpp2: add explicit sgmii-2500 support
Until now the mvpp2 driver used an extra 'phy-speed'
DT property in order to differentiate between the
SGMII and SGMII @2.5GHz. As there is a dedicated
PHY_INTERFACE_MODE_SGMII_2500 flag to mark the latter
start using it and drop the custom flag.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Tested-by: Nadav Haklai <nadavh@marvell.com>

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-05-20 13:03:35 +02:00
Stefan Chulski
27844000ef net: mvpp2: allow MDIO registration for fixed links
Currently, there are 2 valid cases for interface, PHY
and mdio relation:
  - If an interface has PHY handler, it'll call
    mdio_mii_bus_get_from_phy(), which will register
    MDIO bus.
  - If we want to use fixed-link for an interface,
    PHY handle is not defined in the DTS, and no
    MDIO is registered.

There is a third case, for some boards (with switch),
the MDIO is used for switch configuration, but the interface
itself uses fixed link. This patch allows this option by
checking if fixed-link subnode is defined, in this case,
MDIO bus is registers, but the PHY address is set to
PHY_MAX_ADDR for this interface, so this interface will
not try to access the PHY later on.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-20 13:03:31 +02:00
Ben Peled
d757c859c7 net: mvpp2: fix missing switch case break
Signed-off-by: Ben Peled <bpeled@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-05-20 13:03:30 +02:00
Ben Peled
cf51a0d5fc net: mvpp2: remove unused define MVPP22_SMI_PHY_ADDR_REG
Signed-off-by: Ben Peled <bpeled@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-05-20 13:03:30 +02:00
Ben Peled
7589be8d38 net: mvpp2: AN Bypass in 1000 and 2500 basex mode
Signed-off-by: Ben Peled <bpeled@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-20 13:03:30 +02:00
Stefan Chulski
08f462dd1e net: mvpp2: Fix 2.5G GMII_SPEED configurations
GMII_SPEED should be enabled for 2.5G speed

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Yan Markman <ymarkman@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-20 13:03:30 +02:00
Marcin Wojtas
be45eb5064 net: mvpp2: remove redundant SMI address configuration
Because the mvpp2 driver now relies on the PHYLIB and
the external MDIO driver, configuring low level
SMI bus settings is redundant.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-05-20 13:03:30 +02:00
Stefan Chulski
8299abc5ff net: mvpp2: add 1000BaseX and 2500BaseX ppv2 support
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-05-20 13:03:30 +02:00
Stefan Chulski
8d3aa376a9 net: mvpp2: add CP115 port1 10G/5G SFI support
1. Differ between Port1 RGMII and SFI modes in Netcomplex config.
2. Remove XPCS config from SFI mode.
   Port1 doesn't XPCS domain, XPCS config should be removed.
   Access to Port1 XPCS can cause stall.
3. Add Port1 MPCS configurations.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-20 13:03:30 +02:00
Neil Armstrong
4c2eb955cf net: designware: meson8b: add g12a compatible
Add support for the Meson G12A dwmac glue compatible needed after Linux 5.12 sync.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-05-14 17:46:50 +02:00
Neil Armstrong
81d0edafd9 net: dwmac_meson8b: do not set TX delay in TXID & RXID
When the PHY interface is set as TXID & RXID, the delays should be taken from DT,
but first they should not be hardcoded since the PHY driver will set them.

Fixes: 798424e857 ("net: designware: add Amlogic Meson8b & later glue driver")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-05-14 17:43:09 +02:00
Tom Rini
ea184cbff9 Merge tag 'ti-v2021.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-ti
- Initial support for AM64 EVM and SK
- K3 DDR driver unification for J7 and AM64 platforms.
- Minor fixes for TI clock driver
2021-05-12 10:07:21 -04:00
Vignesh Raghavendra
845e1060d3 net: ti: am65-cpsw-nuss: Add a new compatible for AM64
Add a new compatible to support AM64 SoC

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12 16:36:39 +05:30
Vignesh Raghavendra
2411e85b99 net: ti: am65-cpsw-nuss: Don't cache disabled port ID
Currently driver may end up caching disabled port ID as active
interface. Fix this by bailing out earlier in case port is marked
disabled in the DT.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12 16:36:38 +05:30
Vignesh Raghavendra
8441d49e60 net: ti: am65-cpsw-nuss: Prepare to support non primary ext port
CPSW NUSS IP on K3 SoCs can have more than one external port (upto 8)
Therefore increase AM65_CPSW_CPSWNU_MAX_PORTS to 9 (8 ext + 1 Root port)
as preparation to allow any one of the 8 ports to be used as ethernet
interface in U-Boot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12 16:36:38 +05:30
Sean Anderson
cd4359194b net: fec: Only unregister MII bus if we registered it
If we fail to probe for whatever reason, we cannot unregister/free the
MII bus unless we registered it with fec_get_miibus. This fixes FECs
sharing an MDIO bus from destroying it, preventing the other FEC from
using it.

Fixes: 6a895d039b ("net: Update eQos driver and FEC driver to use eth phy interfaces")
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-05-02 12:46:54 +02:00
Sean Anderson
eccd132974 net: fec: Don't use disabled phys
If a phy is disabled, don't use it. This matches Linux's behavior.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-05-02 12:46:54 +02:00