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net: xilinx: axi_emac: Add support for 10G/25G AXI ethernet
Add support for 10G/25G (XXV) high speed ethernet. This Makes use of the exiting AXI DMA, similar to 1G. Signed-off-by: Alessandro Temil <atemil@waymo.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Ashok Reddy Soma
Michal Simek
parent
215f2064c3
commit
53b2af18ca
1 changed files with 119 additions and 45 deletions
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@ -1,5 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2021 Waymo LLC
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* Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2011 PetaLogix
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* Copyright (C) 2010 Xilinx, Inc. All rights reserved.
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@ -73,9 +74,22 @@ DECLARE_GLOBAL_DATA_PTR;
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#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
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#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
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#define DMAALIGN 128
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/* Bitmasks for XXV Ethernet MAC */
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#define XXV_TC_TX_MASK 0x00000001
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#define XXV_TC_FCS_MASK 0x00000002
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#define XXV_RCW1_RX_MASK 0x00000001
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#define XXV_RCW1_FCS_MASK 0x00000002
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#define DMAALIGN 128
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#define XXV_MIN_PKT_SIZE 60
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static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
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static u8 txminframe[XXV_MIN_PKT_SIZE] __attribute((aligned(DMAALIGN)));
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enum emac_variant {
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EMAC_1G = 0,
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EMAC_10G_25G = 1,
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};
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/* Reflect dma offsets */
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struct axidma_reg {
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@ -95,6 +109,7 @@ struct axidma_plat {
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int phyaddr;
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u8 eth_hasnobuf;
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int phy_of_handle;
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enum emac_variant mactype;
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};
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/* Private driver structures */
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@ -108,6 +123,7 @@ struct axidma_priv {
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struct mii_dev *bus;
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u8 eth_hasnobuf;
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int phy_of_handle;
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enum emac_variant mactype;
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};
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/* BD descriptors */
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@ -154,6 +170,14 @@ struct axi_regs {
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u32 uaw1; /* 0x704: Unicast address word 1 */
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};
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struct xxv_axi_regs {
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u32 gt_reset; /* 0x0 */
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u32 reserved[2];
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u32 tc; /* 0xC: Tx Configuration */
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u32 reserved2;
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u32 rcw1; /* 0x14: Rx Configuration Word 1 */
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};
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/* Use MII register 1 (MII status register) to detect PHY */
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#define PHY_DETECT_REG 1
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@ -385,6 +409,18 @@ static void axiemac_stop(struct udevice *dev)
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debug("axiemac: Halted\n");
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}
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static int xxv_axi_ethernet_init(struct axidma_priv *priv)
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{
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struct xxv_axi_regs *regs = (struct xxv_axi_regs *)priv->iobase;
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writel(readl(®s->rcw1) | XXV_RCW1_FCS_MASK, ®s->rcw1);
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writel(readl(®s->tc) | XXV_TC_FCS_MASK, ®s->tc);
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writel(readl(®s->tc) | XXV_TC_TX_MASK, ®s->tc);
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writel(readl(®s->rcw1) | XXV_RCW1_RX_MASK, ®s->rcw1);
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return 0;
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}
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static int axi_ethernet_init(struct axidma_priv *priv)
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{
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struct axi_regs *regs = priv->iobase;
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@ -440,6 +476,9 @@ static int axiemac_write_hwaddr(struct udevice *dev)
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struct axidma_priv *priv = dev_get_priv(dev);
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struct axi_regs *regs = priv->iobase;
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if (priv->mactype != EMAC_1G)
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return 0;
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/* Set the MAC address */
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int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
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(pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
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@ -477,7 +516,6 @@ static void axi_dma_init(struct axidma_priv *priv)
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static int axiemac_start(struct udevice *dev)
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{
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struct axidma_priv *priv = dev_get_priv(dev);
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struct axi_regs *regs = priv->iobase;
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u32 temp;
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debug("axiemac: Init started\n");
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@ -490,8 +528,13 @@ static int axiemac_start(struct udevice *dev)
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axi_dma_init(priv);
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/* Initialize AxiEthernet hardware. */
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if (axi_ethernet_init(priv))
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return -1;
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if (priv->mactype == EMAC_1G) {
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if (axi_ethernet_init(priv))
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return -1;
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} else {
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if (xxv_axi_ethernet_init(priv))
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return -1;
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}
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/* Disable all RX interrupts before RxBD space setup */
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temp = readl(&priv->dmarx->control);
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@ -525,15 +568,25 @@ static int axiemac_start(struct udevice *dev)
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/* Rx BD is ready - start */
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axienet_dma_write(&rx_bd, &priv->dmarx->tail);
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/* Enable TX */
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writel(XAE_TC_TX_MASK, ®s->tc);
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/* Enable RX */
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writel(XAE_RCW1_RX_MASK, ®s->rcw1);
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if (priv->mactype == EMAC_1G) {
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struct axi_regs *regs = priv->iobase;
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/* Enable TX */
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writel(XAE_TC_TX_MASK, ®s->tc);
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/* Enable RX */
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writel(XAE_RCW1_RX_MASK, ®s->rcw1);
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/* PHY setup */
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if (!setup_phy(dev)) {
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axiemac_stop(dev);
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return -1;
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/* PHY setup */
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if (!setup_phy(dev)) {
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axiemac_stop(dev);
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return -1;
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}
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} else {
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struct xxv_axi_regs *regs = (struct xxv_axi_regs *)priv->iobase;
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/* Enable TX */
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writel(readl(®s->tc) | XXV_TC_TX_MASK, ®s->tc);
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/* Enable RX */
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writel(readl(®s->rcw1) | XXV_RCW1_RX_MASK, ®s->rcw1);
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}
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debug("axiemac: Init complete\n");
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@ -548,6 +601,14 @@ static int axiemac_send(struct udevice *dev, void *ptr, int len)
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if (len > PKTSIZE_ALIGN)
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len = PKTSIZE_ALIGN;
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/* If size is less than min packet size, pad to min size */
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if (priv->mactype == EMAC_10G_25G && len < XXV_MIN_PKT_SIZE) {
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memset(txminframe, 0, XXV_MIN_PKT_SIZE);
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memcpy(txminframe, ptr, len);
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len = XXV_MIN_PKT_SIZE;
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ptr = txminframe;
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}
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/* Flush packet to main memory to be trasfered by DMA */
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flush_cache((phys_addr_t)ptr, len);
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@ -632,7 +693,7 @@ static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
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temp = readl(&priv->dmarx->control);
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temp &= ~XAXIDMA_IRQ_ALL_MASK;
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writel(temp, &priv->dmarx->control);
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if (!priv->eth_hasnobuf)
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if (!priv->eth_hasnobuf && priv->mactype == EMAC_1G)
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length = rx_bd.app4 & 0xFFFF; /* max length mask */
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else
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length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
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@ -709,21 +770,25 @@ static int axi_emac_probe(struct udevice *dev)
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priv->dmatx = plat->dmatx;
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/* RX channel offset is 0x30 */
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priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30);
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priv->eth_hasnobuf = plat->eth_hasnobuf;
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priv->phyaddr = plat->phyaddr;
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priv->phy_of_handle = plat->phy_of_handle;
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priv->interface = pdata->phy_interface;
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priv->mactype = plat->mactype;
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priv->bus = mdio_alloc();
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priv->bus->read = axiemac_miiphy_read;
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priv->bus->write = axiemac_miiphy_write;
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priv->bus->priv = priv;
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if (priv->mactype == EMAC_1G) {
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priv->eth_hasnobuf = plat->eth_hasnobuf;
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priv->phyaddr = plat->phyaddr;
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priv->phy_of_handle = plat->phy_of_handle;
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priv->interface = pdata->phy_interface;
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ret = mdio_register_seq(priv->bus, dev_seq(dev));
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if (ret)
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return ret;
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priv->bus = mdio_alloc();
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priv->bus->read = axiemac_miiphy_read;
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priv->bus->write = axiemac_miiphy_write;
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priv->bus->priv = priv;
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axiemac_phy_init(dev);
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ret = mdio_register_seq(priv->bus, dev_seq(dev));
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if (ret)
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return ret;
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axiemac_phy_init(dev);
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}
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return 0;
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}
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@ -732,9 +797,11 @@ static int axi_emac_remove(struct udevice *dev)
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{
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struct axidma_priv *priv = dev_get_priv(dev);
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free(priv->phydev);
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mdio_unregister(priv->bus);
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mdio_free(priv->bus);
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if (priv->mactype == EMAC_1G) {
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free(priv->phydev);
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mdio_unregister(priv->bus);
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mdio_free(priv->bus);
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}
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return 0;
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}
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@ -757,6 +824,7 @@ static int axi_emac_of_to_plat(struct udevice *dev)
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const char *phy_mode;
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pdata->iobase = dev_read_addr(dev);
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plat->mactype = dev_get_driver_data(dev);
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offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
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"axistream-connected");
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@ -771,25 +839,30 @@ static int axi_emac_of_to_plat(struct udevice *dev)
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return -EINVAL;
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}
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plat->phyaddr = -1;
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if (plat->mactype == EMAC_1G) {
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plat->phyaddr = -1;
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offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
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if (offset > 0) {
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plat->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
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plat->phy_of_handle = offset;
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offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
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"phy-handle");
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if (offset > 0) {
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plat->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
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"reg", -1);
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plat->phy_of_handle = offset;
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}
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phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
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if (phy_mode)
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pdata->phy_interface = phy_get_interface_by_name(phy_mode);
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if (pdata->phy_interface == -1) {
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printf("%s: Invalid PHY interface '%s'\n", __func__,
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phy_mode);
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return -EINVAL;
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}
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plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
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"xlnx,eth-hasnobuf");
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}
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phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
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if (phy_mode)
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pdata->phy_interface = phy_get_interface_by_name(phy_mode);
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if (pdata->phy_interface == -1) {
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printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
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return -EINVAL;
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}
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plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
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"xlnx,eth-hasnobuf");
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printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)pdata->iobase,
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plat->phyaddr, phy_string_for_interface(pdata->phy_interface));
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@ -797,7 +870,8 @@ static int axi_emac_of_to_plat(struct udevice *dev)
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}
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static const struct udevice_id axi_emac_ids[] = {
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{ .compatible = "xlnx,axi-ethernet-1.00.a" },
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{ .compatible = "xlnx,axi-ethernet-1.00.a", .data = (uintptr_t)EMAC_1G },
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{ .compatible = "xlnx,xxv-ethernet-1.0", .data = (uintptr_t)EMAC_10G_25G },
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{ }
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};
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