This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:
- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines
Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.
Signed-off-by: Stefan Roese <sr@denx.de>
It was brought to our attention that U-Boot contains code derived from the
IBM OpenBIOS source code originally provided with some of the older PowerPC
4xx development boards. As a result, the original license of this code has
been carried in the various files for a number of years in the U-Boot project.
IBM is dual-licensing the IBM code contributions already present in U-Boot
under either the terms of the GNU General Public License version 2, or the
original code license already present.
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and
L2 cache DCRs from ppc440.h to this new header.
Also converted these DCR defines from lowercase to uppercase and
modified referencing modules to use them.
Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The definitions of bits in SDR_CFG are incorrect, and not used within
U-Boot. Therefore, they can be removed.
The naming of the sdr_ddrdl/sdr_cfg registers do not follow conventions,
and are unused, so they can be removed too.
A definition for SDR0_DDRCFG is added.
Signed-off-by: Steven A. Falco <sfalco@harris.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The Arches Evaluation board is based on the AMCC 460GT SoC chip.
This board is a dual processor board with each processor providing
independent resources for Rapid IO, Gigabit Ethernet, and serial
communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR
FLASH, UART, EEPROM and temperature sensor, along with a shared debug
port. The two 460GT's will communicate with each other via shared
memory, Gigabit Ethernet and x1 PCI-Express.
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
PPC405EX and PPC460EX/GT/SX
- Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX
processors
- Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared
across processors (405 and 440/460)
- Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX
processors
- Add register bit definitions for Memory Queue Configuration registers
Signed-off-by: Prodyut Hazarika <phazarika@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This 2nd patch now removes all UIC mask bit definition. They should be
generated from the vectors by using the UIC_MASK() macro from now on.
This way only the vectors need to get defined for new PPC's.
Also only the really used interrupt vectors are now defined. This makes
definitions for new PPC versions easier and less error prone.
Another part of this patch is that the 4xx emac driver got a little
cleanup, since now the usage of the interrupts is clearer.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch removes all EBC related defines from the PPC4xx headers
ppc405.h and ppc440.h and introduces a new header
include/asm-ppc/ppc4xx-ebc.h
with all those defines.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch implements a fix provided by AMCC so that the lockup upon
simultanious traffic on AHB USB OTG, USB 2.0 and SATA doesn't occur
anymore:
Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and clear SDR0_AHB_CFG[A2P_PROT2]
(bit 25) for a new 460EX errata regarding concurrent use of AHB USB OTG,
USB 2.0 host and SATA.
This errata is not officially available yet. I'll update the comment
to add the errata number later.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch removes all SDRAM related defines from the PPC4xx headers
ppc405.h and ppc440.h. This is needed since now some 405 PPC's use
the same SDRAM controller as 440 systems do (like 405EX and 440SP).
It also introduces new defines for the equipped SDRAM controller based on
which PPC variant is used. There new defines are:
used on 405GR/CR/EP and some Xilinx Virtex boards.
used on 440GP/GX/EP/GR.
used on 440EPx/GRx.
used on 405EX/r/440SP/SPe/460EX/GT.
Signed-off-by: Stefan Roese <sr@denx.de>
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).
Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Use the GPT0_MASKx registers as the temporary storage for watch-dog
timer POST test instead of GPT0_COMPx. The latter
(GPT0_COMP1..GPT0_COMP5) are used for the log-buffer header.
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
This patch adds support for the AMCC Glacier 460GT eval board.
The main difference to the Canyonlands board are listed here:
- 4 ethernet ports instead of 2
- no SATA port
- no USB port
Currently EMAC2+3 are not working. This will be fixed in a later
release.
Signed-off-by: Stefan Roese <sr@denx.de>
To enable this, alternative, configuration the U-Boot board configuration
file for lwmon5 includes the definitions of alternative addresses for header
(CONFIG_ALT_LH_ADDR) and buffer (CONFIG_ALT_LB_ADDR).
The Linux shall be configured with the CONFIG_ALT_LB_LOCATION option set,
and has the BOARD_ALT_LH_ADDR and BOARD_ALT_LB_ADDR constants defined in the
lwmon5 board-specific header (arch/ppc/platforms/4xx/lwmon5.h).
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
This patch configures the LWMON5 port to use d-cache as init-ram and
the unused GPT0_COMP6 as POST WORD storage.
Signed-off-by: Stefan Roese <sr@denx.de>
On Katmai the complete auto-calibration somehow doesn't seem to
produce the best results, meaning optimal values for RQFD/RFFD.
This was discovered by GDA using a high bandwidth scope,
analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
so now on Katmai "only" RFFD is auto-calibrated.
This patch also adds RDCC calibration as mentioned on page 7 of
the AMCC PowerPC440SP/SPe DDR2 application note:
"DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds the Denali SDRAM controller definitions to "ppc440.h".
It also fixes two typos in the definitions, so the board-specific
"sdram.h" files containing these definitions are also fixed to avoid
compiler warnings.
Signed-off-by: Larry Johnson <lrj@acm.org>
This patch enables the hardware-fix for the PCI/DMA errata's 19+22 by
setting the FIXD bit in the SDR0_MFR register. Here a description of the
symptoms:
Problem Description
------------------------------
If a DMA is performed between memory and PCI with the DMA 1 Controller
using prefetch, and as a result uses a special purpose buffer selected by
the PCIXn Bridge Options 1 Register (PCIXn_BRDGOPT1[RBP7] - bits 31-29),
the first part of the transfer sequence is performed twice. The
PPC440SPe PCI Controller requests more data than was needed such that in
the case of enforce memory protection, a host CPU exception can occur.
No data is corrupted, because data transfer is stopped in the PCI
Controller. Prefetch enable is specified by setting DMA Configuration
Register (I2O0_DMAx_CFG[DXEPD] - bit 31) to 0.
Behavior that may be observed in a running system
---------------------------------------------------------------------------
1. DMA performance is decreased because of the double access on the PCI bus
interface.
2. If an illegal access to some address on the PCI bus is detected at the
system level, a machine check or similar system error may occur.
Workarounds Available
----------------------------------
1. Do not program prefetch. Note that a prefetch command cannot be programmed
without selecting a special purpose buffer.
2. To avoid crossing a physical boundary of the PCI slave device, add 512
bytes of address to the PCI address range.
This patch was originally provided by Pravin M. Bathija <pbathija@amcc.com>
from AMCC and slighly changed.
Signed-off-by: Pravin M. Bathija <pbathija@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
- Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE
- Cleanup of the 4xx GPIO functions
- Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h
Signed-off-by: Stefan Roese <sr@denx.de>
This patch moves some common 4xx macros and the PPC405_SYS_INFO/
PPC440_SYS_INFO structure into the common ppc4xx.h header.
Lot's of other macros are good candidates to be consolidated this way
in the future.
Signed-off-by: Stefan Roese <sr@denx.de>
- Clear ECC status regs after ECC POST test
- Set dcbz for ECC generation with caches enabled as default
- Code cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
- Introduced dedicated switches for building 440 and 405 images required
for 440-specific machine instructions like 'rfmci' etc.
- Exception vectors moved to the proper location (_start moved away from
the critical exception handler space, which it occupied)
- CriticalInput now serviced (with default handler)
- MachineCheck properly serviced (added a dedicated handler and return
subroutine)
- Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused,
unhandled and those not relevant for 4xx were eliminated)
- Eliminated Linux leftovers, removed dead code
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Now 405EZ ports also show upon bootup from which boot device
they are configured to boot:
U-Boot 1.2.0-gd3832e8f-dirty (Apr 18 2007 - 07:47:05)
CPU: AMCC PowerPC 405EZ Rev. A at 199.999 MHz (PLB=133, OPB=66, EBC=66 MHz)
Bootstrap Option E - Boot ROM Location EBC (32 bits)
16 kB I-Cache 16 kB D-Cache
Board: Acadia - AMCC PPC405EZ Evaluation Board
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds some 4xx GPIO functions. It also moves some of the
common code and defines into a common 4xx GPIO header file.
Signed-off-by: Stefan Roese <sr@denx.de>
As provided by the AMCC applications team, this patch optimizes the
DDR2 setup for 166MHz bus speed. The values provided are also save
to use on a "normal" 133MHz PLB bus system. Only the refresh counter
setup has to be adjusted as done in this patch.
For this the NAND booting version had to include the "speed.c" file
from the cpu/ppc4xx directory. With this addition the NAND SPL image
will just fit into the 4kbytes of program space. gcc version 4.x as
provided with ELDK 4.x is needed to generate this optimized code.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch updates the recently added Katmai board support. The biggest
change is the support of ECC DIMM modules in the 440SP(e) SPD DDR2
driver.
Please note, that still some problems are left with some memory
configurations. See the driver for more details.
Signed-off-by: Stefan Roese <sr@denx.de>
