The eth_device.name field length is limited by NAMESIZE,
which is 16 defined in include/net.h. Unfortunately, two
of the names in lan91c96.c are beyond that.
Signed-off-by: YanJun Yang <yangyj.ee@gmail.com>
This adds support for for the PCA9535/PCA9539 family of gpio devices which
have 16 output pins.
To let the driver know which devices are 16-pin it is necessary to define
CONFIG_SYS_I2C_PCA953X_WIDTH in your board config file. This is used to
create an array of {chip, ngpio} tuples that are used to determine the
width of a particular chip. For backwards compatibility it is assumed that
any chip not defined in CONFIG_SYS_I2C_PCA953X_WIDTH has 8 pins.
Acked-by: Peter Tyser <ptyser@xes-inc.com>
Tested-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
The include/miiphy.h header duplicates a lot of things from linux/mii.h.
So punt all the things that overlap to keep the API simple and to make
merging between U-Boot and Linux simpler.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The flash_verbose logic is only used by the CFI MTD layer, so if we aren't
using that, disable the logic completely.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The serial of ap325rxa has it of two kinds, and the setting of
the clock is different.
Because there was a problem by function to judge serial kind,
this revised it.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
I copied the setting of CPU from Linux kernel and commonized it.
By this, we can communalize a kernel and information.
And added the serial setting of many CPU's.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
It can be optimised out by the compiler otherwise resulting
in obscure errors like a board not booting.
This has been documented in README since 2006 when these were
first fixed up for GCC 4.x.
Signed-off-by: John Rigby <john.rigby@linaro.org>
Fix some additional places.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-By: Albert ARIBAUD <albert.aribaud@free.fr>
The current code use all the voltage range support by the host
controller to do the validation. This will cause problem when
the host supports Low Voltage Range. Change the validation
voltage to be based on board setup.
Signed-off-by: Li Yang <leoli@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The max clock of MMC is 52MHz
Signed-off-by: Jerry Huang <Changm-Ming.Huang@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
After booting the u-boot, and first using some SD card (such as Sandisk 2G SD
card), because the field 'clock' of struct mmc is zero, this will cause
the read transfer is always active and SDHC DATA line is always active,
therefore, driver can't handle the next command.
Therefore, we use mmc_set_clock to setup both the data structure and HW
to the initial clock speed of 400000Hz.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This is part of the timer cleanup effort.
In the future we only use get_timer() in its intended way to
program timeout loops.
reset_timer() shall not be used anymore.
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
Fix clock divider for COM57H5M10XRC display.
The previous setting caused flicker.
Tested on Qong (EVBLite with COM57H5M10XRC).
Signed-off-by: Stefano Babic <sbabic@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
PT7C4338 chip is being manufactured by Pericom Technology Inc.
It is a serial real-time clock which provides:
1)Low-power clock/calendar.
2)Programmable square-wave output.
It has 56 bytes of nonvolatile RAM.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
While we're here, cut out the useless id defines too.
Signed-off-by: Wojtek Skulski <skulski@pas.rochester.edu>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This patch adds the possibility to (optinally) write to the
flash configuration register. The Intel style CFI chips support
such a register that can be used to configure the operation
mode to a non-default value.
This method will be used by the t3corp board, which needs to
configure the DS617 Xilinx flash for async read mode.
Signed-off-by: Stefan Roese <sr@denx.de>
The function sector_erased() is modified to not use pointer
access, but to use the correct accessor functions. This fixes a
problem on the t3corp board with the Xilinx DS617 flash chips. Here
a board specific accessor function is needed to read from flash
in 32bit mode. This patch enables such an operation mode.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds some calls to set the flash chip in the read-status-
register- or read-id-mode before the corresponding register is
read back. This problem was detected while porting the common CFI
driver to support the Xilinx DS617 flash chips.
Signed-off-by: Stefan Roese <sr@denx.de>
ARMADA 100 SoCs has NS16550 compatible UART peripheral
This patch enables the same for ARMADA100 platforms
Signed-off-by: Mahavir Jain <mjain@marvell.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
On some processors this ier register configuration is different
for ex. Marvell Armada100
This patch introduce CONFIG_SYS_NS16550_IER macro support to
unconditionally initialize this register.
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Most of the Marvell SoCs has Multi Function Pin (MFP) configuration registers
For ex. ARMADA100.
These registers are programmed to expose the specific functionality
associated with respective SoC Pins
This driver provides configuration APIs,
using them, configuration need to be done in board specific code
for ex- following code configures MFPs 107 and 108 for UART_TX/RX functionality
int board_early_init_f(void)
{
u32 mfp_cfg[] = {
/* Console on UART1 */
MFP107_UART1_RXD,
MFP108_UART1_TXD,
MFP_EOC /*End of configureation*/
};
/* configure MFP's */
mfp_config(mfp_cfg);
return 0;
}
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
eSDHC host controller reset results in clearing of snoop bit also.
This patch sets the SNOOP bit after the completion of host controller reset.
Without this patch mmc reads are not consistent.
Signed-off-by: P.V.Suresh <pala@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
According to Freescale reference manuals (eg section "13.4.4.2
Programming the UPMs" of the P4080 Reference Manual):
"Since the result of any update to the MxMR/MDR register must be in
effect before the dummy read or write to the UPM region, a write to
MxMR/MDR should be followed immediately by a read of MxMR/MDR."
The UPM on a custom P4080-based board did not work without performing
a read of MxMR/MDR after a write.
Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The following commit:
commit 46e91674fb
Author: Peter Tyser <ptyser@xes-inc.com>
Date: Tue Nov 3 17:52:07 2009 -0600
tsec: Force TBI PHY to 1000Mbps full duplex in SGMII mode
Removed setting Auto-Neg by default, however this is believed to be
proper default configuration for initialization of the TBI interface.
Instead we explicitly set CONFIG_TSEC_TBICR_SETTINGS for the
XPedite5370 & XPedite5500 boards that use a Broadcomm PHY which require
Auto-Neg to be disabled to function properly.
This addresses a breakage on the P2020 DS & MPC8572 DS boards when used
with an SGMII riser card. We also remove setting
CONFIG_TSEC_TBICR_SETTINGS on the P1_P2_RDB family of boards as now the
default setting is sufficient for them.
Additionally, we clean up the code a bit to remove an unnecessary second
define.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Peter Tyser <ptyser@xes-inc.com>
Tested-by: Peter Tyser <ptyser@xes-inc.com>
CC: Ruslan N. Araslanov <byaaka@yandex.ru>
Signed-off-by: Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Add battery charging support twl6030 driver.
Add support for battery voltage and current measurements.
Add command to get battery status and start/stop battery charging from USB.
Signed-off-by: Balaji T K <balajitk@ti.com>
Tested-by: Steve Sakoman <steve.sakoman@linaro.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The attached patch fixes wrong timing default values and adds the
possibility to specify board specific timing value in the board config file.
Signed-off-by: David Mueller <d.mueller@elsoft.ch>
Since the driver is used not only on Freescale boards,
we move it to a common place for video drivers as
suggested by Wolfgang. The patch also cleans up the
top level Makefile.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Use C structs for registers, and use readl/writel instead of custom
accessors.
Acked-by: Michael Brandt <michael.brandt@stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Currently the hardware was left in an undefined state in case Spartan3
serial load failed. This patch adds Xilinx_abort_fn to give the board
a possibility to clean up in this case.
Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de>
This patch is a port of the work by Sudhakar Rajeshekhara in commit
ab3effbcad8851cc65dc5241a01c064d2030a3b2 of
git://arago-project.org/git/people/sandeep/u-boot-davinci.git.
The da850 UI board has on it an RMII PHY which can be used if the MDC line
to the MII PHY on the baseboard is disabled and the RMII PHY is enabled by
configuring the values of some GPIO pins on the IO expander of the UI board.
This patch implements disabling that line via GPIO2[6], configuring the UI
board's IO expander and setting only the pinmux settings that are needed for
RMII operation.
Tested on da850evm by adding a define for CONFIG_DRIVER_TI_EMAC_USE_RMII.
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
CC: Sandeep Paulraj <s-paulraj@ti.com>
CC: Ben Warren <biggerbadderben@gmail.com>
CC: Mike Frysinger <vapier@gentoo.org>
CC: Sughosh Ganu <urwithsughosh@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
commit ec50a8e389
"cfi_flash: handle 'chip size exceeds address window' situation"
added 3rd argument to flash_get_size() but didn't fix all the
function calls from the board specific code. Many boards have
their own flash_get_size() definitions in the board code and
use them there, but some boards (e.g. tqm834x, tqm85xx, pdm360ng)
use flash_get_size() from the cfi_flash.c driver.
The bug shows up if the value of the "max_size" argument (which
is not defined when calling the function with two arguments)
happens to be less than "info->size". In this case on the
affected boards we end up with a bank of reduced size and
in the worst case might even be not able to update U-Boot or
to boot the kernel from flash:
=> fli
Bank # 1: CFI conformant FLASH (32 x 16) Size: 0 kB in 1 Sectors
AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E
Erase timeout: 4096 ms, write timeout: 1 ms
Buffer write timeout: 3 ms, buffer size: 64 bytes
Sector Start Addresses:
F0000000 RO
Bank # 2: CFI conformant FLASH (32 x 16) Size: 128 MB in 512 Sectors
AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E
Erase timeout: 4096 ms, write timeout: 1 ms
Buffer write timeout: 3 ms, buffer size: 64 bytes
Sector Start Addresses:
F8000000 F8040000 F8080000 F80C0000 F8100000
F8140000 F8180000 F81C0000 F8200000 F8240000
...
E.g., updating U-Boot is not possible now:
=> protect off ${u-boot_addr} +${u-boot_size}
Error: end address (0xf007ffff) not in flash!
Bad address format
=> era ${u-boot_addr} +${u-boot_size}
Error: end address (0xf007ffff) not in flash!
Bad address format
This patch removes the 3rd argument of flash_get_size() again
and sets "max_size" in the function itself instead of passing
it as a function argument.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
This is needed for the canyonlands_nand build target. Without it
the resulting image won't fit into 4k.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Acked-by: Stefan Roese <sr@denx.de>
Get rid of compiler warning:
e1000.c: In function 'e1000_transmit':
e1000.c:5028: warning: passing argument 1 of 'virt_to_phys' discards qualifiers from pointer target type
Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Calling usb_dev_init() from within the EHCI host driver is wrong.
The EHCI host driver should have no dependency/interconnection to the
USB device driver.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
This patch fixes a problem noticed on lwmon5 (PPC440EPx) using the
common EHCI driver, when "usb reset" is issued multiple times.
Upon the 2nd (and further) "usb reset" command, the command fails
with the following messages:
=> usb reset
(Re)start USB...
USB: Register 1111 NbrPorts 1
USB EHCI 1.00
scanning bus for devices... 5 USB Device(s) found
scanning bus for storage devices... 2 Storage Device(s) found
=> usb reset
(Re)start USB...
USB: EHCI fail to reset
Error, couldn't init Lowlevel part
This patch fixes this problem. Now "usb reset" can be called multiple
times.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
This watchdog reset call is needed here, otherwise the lwmon5 board
(PPC440EPx based) will reset upon the "usb reset" command.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
Checking the status field of the qTD token in the current code
do not take into acount cases where endpoint stall (halted) bit
is set together with XactErr status bit. As a result clearing
stall on an endpoint won't be done if this status bit was also
set. Check for halted bit and report USB_ST_STALLED status
if the host controller also indicates endpoit stall condition.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
The patch is to support getting FEC MAC address from fuse bank.
Signed-off-by: Jason Liu <r64343@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Having a loop with a counter is no timing guarentee for timing
accuracy or compiler optimizations. For e.g. the same loop counter
which runs when the MPU is running at 600MHz will timeout in around
half the time when running at 1GHz. or the example where GCC 4.5
compiles with different optimization compared to GCC 4.4. use timer
to keep track of time elapse and we use an emperical number - 1sec
for a worst case timeout. This should never happen, and is adequate
imaginary condition for us to fail with timeout.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Previously with archive libraries fdt.o was compiled and included in
qe.a and then discarded by the linker. With partial linking this
results in unresolved symbols, which this commit fixes.
This commit also cleans up a now-useless conditional in fdt.c.
Signed-off-by: Sebastien Carlier <sebastien.carlier@gmail.com>
Tested-by: Wolfgang Denk <wd@denx.de>
Before this commit, weak symbols were not overridden by non-weak symbols
found in archive libraries when linking with recent versions of
binutils. As stated in the System V ABI, "the link editor does not
extract archive members to resolve undefined weak symbols".
This commit changes all Makefiles to use partial linking (ld -r) instead
of creating library archives, which forces all symbols to participate in
linking, allowing non-weak symbols to override weak symbols as intended.
This approach is also used by Linux, from which the gmake function
cmd_link_o_target (defined in config.mk and used in all Makefiles) is
inspired.
The name of each former library archive is preserved except for
extensions which change from ".a" to ".o". This commit updates
references accordingly where needed, in particular in some linker
scripts.
This commit reveals board configurations that exclude some features but
include source files that depend these disabled features in the build,
resulting in undefined symbols. Known such cases include:
- disabling CMD_NET but not CMD_NFS;
- enabling CONFIG_OF_LIBFDT but not CONFIG_QE.
Signed-off-by: Sebastien Carlier <sebastien.carlier@gmail.com>
When CONFIG_PCI_SCAN_SHOW is defined U-Boot prints out PCI devices as
they are found during bootup, eg:
PCIE1: connected as Root Complex
01:00.0 - 10b5:8518 - Bridge device
02:01.0 - 10b5:8518 - Bridge device
03:00.0 - 10b5:8112 - Bridge device
04:01.0 - 8086:1010 - Network controller
04:01.1 - 8086:1010 - Network controller
02:02.0 - 10b5:8518 - Bridge device
02:03.0 - 10b5:8518 - Bridge device
06:00.0 - 10b5:8518 - Bridge device
07:00.0 - 10b5:8518 - Bridge device
08:00.0 - 1957:0040 - Processor
07:01.0 - 10b5:8518 - Bridge device
09:00.0 - 10b5:8112 - Bridge device
07:02.0 - 10b5:8518 - Bridge device
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
0d:00.0 - 1957:0040 - Processor
PCIE2: Bus 0c - 0d
This information is useful, but its difficult to determine the PCI bus
topology. To things clearer, we can use indention to make it more
obvious how the PCI bus is organized. For the example above, the
updated output with this change is:
PCIE1: connected as Root Complex
01:00.0 - 10b5:8518 - Bridge device
02:01.0 - 10b5:8518 - Bridge device
03:00.0 - 10b5:8112 - Bridge device
04:01.0 - 8086:1010 - Network controller
04:01.1 - 8086:1010 - Network controller
02:02.0 - 10b5:8518 - Bridge device
02:03.0 - 10b5:8518 - Bridge device
06:00.0 - 10b5:8518 - Bridge device
07:00.0 - 10b5:8518 - Bridge device
08:00.0 - 1957:0040 - Processor
07:01.0 - 10b5:8518 - Bridge device
09:00.0 - 10b5:8112 - Bridge device
07:02.0 - 10b5:8518 - Bridge device
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
0d:00.0 - 1957:0040 - Processor
PCIE2: Bus 0c - 0d
In the examples above, an MPC8640 is connected to a PEX8518 PCIe switch
(01:00 and 02:0x), which is connected to another PEX8518 PCIe switch
(06:00 and 07:0x), which then connects to a MPC8572 processor (08:00).
Also, the MPC8640's PEX8518 PCIe switch is connected to a PCI ethernet
card (04:01) via a PEX8112 PCIe-to-PCI bridge (03:00).
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
This change does the following:
- Removes the printing of the PCI interrupt line value. This is
normally set to 0 by U-Boot on bootup and is rarely used during
everyday operation.
- Prints out the PCI function number of a device. Previously a device
with multiple functions would be printed identically 2 times, which is
generally confusing. For example, on an Intel 2 port gigabit Ethernet
card the following was displayed:
...
04 01 8086 1010 0200 00
04 01 8086 1010 0200 00
...
- Prints a text description of each device's PCI class instead of the
raw PCI class code. The textual description makes it much easier to
determine what devices are installed on a PCI bus.
- Changes the general formatting of the PCI device output.
Previous output:
PCIE1: connected as Root Complex
04 01 8086 1010 0200 00
04 01 8086 1010 0200 00
03 00 10b5 8112 0604 00
02 01 10b5 8518 0604 00
02 02 10b5 8518 0604 00
08 00 1957 0040 0b20 00
07 00 10b5 8518 0604 00
09 00 10b5 8112 0604 00
07 01 10b5 8518 0604 00
07 02 10b5 8518 0604 00
06 00 10b5 8518 0604 00
02 03 10b5 8518 0604 00
01 00 10b5 8518 0604 00
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
0d 00 1957 0040 0b20 00
PCIE2: Bus 0c - 0d
Updated output:
PCIE1: connected as Root Complex
04:01.0 - 8086:1010 - Network controller
04:01.1 - 8086:1010 - Network controller
03:00.0 - 10b5:8112 - Bridge device
02:01.0 - 10b5:8518 - Bridge device
02:02.0 - 10b5:8518 - Bridge device
08:00.0 - 1957:0040 - Processor
07:00.0 - 10b5:8518 - Bridge device
09:00.0 - 10b5:8112 - Bridge device
07:01.0 - 10b5:8518 - Bridge device
07:02.0 - 10b5:8518 - Bridge device
06:00.0 - 10b5:8518 - Bridge device
02:03.0 - 10b5:8518 - Bridge device
01:00.0 - 10b5:8518 - Bridge device
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
0d:00.0 - 1957:0040 - Processor
PCIE2: Bus 0c - 0d
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Previously fsl_pci_init_port() always assumed that a port was a PCIe
port and would incorrectly print messages for a PCI port such as the
following on bootup:
PCI1: 32 bit, 33 MHz, sync, host, arbiter
Scanning PCI bus 00
PCIE1 on bus 00 - 00
This change corrects the output of fsl_pci_init_port():
PCI1: 32 bit, 33 MHz, sync, host, arbiter
Scanning PCI bus 00
PCI1 on bus 00 - 00
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
nic and hw structures are allocated via malloc i.e. return memory
is not zero initialized. Because of this few structure member like
"function pointers" are initialized with garbage values.
It may cause problem. for eg. during eth_initialize, dev->write_hwaddr
is used.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fixed typo.
Signed-off-by: Wolfgang Denk <wd@denx.de>
uli526x driver does not have write_hwaddr function.
However, eth stuff executes write_hwaddr function
because eth_device structure has not been initialized.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Ben Warren <biggerbadderben@gmail.com>
tsi108_eth driver does not have write_hwaddr function.
However, eth stuff executes write_hwaddr function
because eth_device structure has not been initialized.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Ben Warren <biggerbadderben@gmail.com>
pcnet driver does not have write_hwaddr function.
However, eth stuff executes write_hwaddr function
because eth_device structure has not been initialized.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Ben Warren <biggerbadderben@gmail.com>
ns8382x driver does not have write_hwaddr function.
However, eth stuff executes write_hwaddr function
because eth_device structure has not been initialized.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Ben Warren <biggerbadderben@gmail.com>
natsemi driver does not have write_hwaddr function.
However, eth stuff executes write_hwaddr function
because eth_device structure has not been initialized.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Ben Warren <biggerbadderben@gmail.com>
This prevents access to the member of eth_device which is not initialized.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Ben Warren <biggerbadderben@gmail.com>
eepro100 driver does not have write_hwaddr function.
However, eth stuff executes write_hwaddr function
because eth_device structure has not been initialized.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Ben Warren <biggerbadderben@gmail.com>
dc2114x driver does not have write_hwaddr function.
However, eth stuff executes write_hwaddr function
because eth_device structure has not been initialized.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Ben Warren <biggerbadderben@gmail.com>
rtl8139 driver does not have write_hwaddr function.
However, eth stuff executes write_hwaddr function
because eth_device structure has not been initialized.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Ben Warren <biggerbadderben@gmail.com>
rtl8169 does not have write_hwaddr function.
However, eth stuff executes write_hwaddr function
because eth_device structure has not been initialized.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Ben Warren <biggerbadderben@gmail.com>
Supports most types that support Read-Id and the FM25H20.
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This patch adds multi-block read support for the generic MMC
driver. Large reads are broken into chunks of 65535 blocks to
ensure that the code works with controllers having a 16 bit block counter.
This patch results in a significant performance improvement.
Time to read a 45 MB file went from 36 seconds to 9 seconds on Overo
Signed-off-by: Steve Sakoman <steve.sakoman@linaro.org>
Tested-by: Steve Sakoman <steve.sakoman@linaro.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The current mmc write implementation is type ulong, but returns int values.
Some of the printf's are terminated with /n/r, one has none.
This patch fixes these issues and also removes some unnecessary local
variables.
Signed-off-by: Steve Sakoman <steve.sakoman@linaro.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
By now, the majority of architectures have working relocation
support, so the few remaining architectures have become exceptions.
To make this more obvious, we make working relocation now the default
case, and flag the remaining cases with CONFIG_NEEDS_MANUAL_RELOC.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
Tested-by: Reinhard Meyer <u-boot@emk-elektronik.de>
This patch adds generic support for the Samsung s3c2440 processor.
Global s3c24x0 changes to struct members converting from upper case to
lower case.
Signed-off-by: Craig Nauman <cnauman@diagraph.com>
Cc: kevin.morfitt@fearnside-systems.co.uk
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Constraint the mmc framework to only send no more than 65535
blocks in one go during the multi-write command. This constraint
comes due to the limitation of 16bit width block counter register
at some hardware.
Signed-off-by: Lei Wen <leiwen@marvell.com>
Cc: Reinhard Meyer <u-boot@emk-elektronik.de>
On OMAP36/37XX the standard on chip pullups are not sufficient to
ensure proper i2c operation without external pullups or switching
to high speed mode and enabling special on chip pullups.
This is an issue for Beagle xM, which does not have external pullups
on the expansion board i2c lines.
The issue manifests itself as an AL (arbitration lost) error when
probing for a non-existent device (i.e. on a Beagle xM with no expansion
boards attached). This issue does not occur on expansion boards that
include pullups or on Overo 37XX COM's since they include pull-ups.
This patch fixes the issue by checking for the AL bit in the i2c_probe
function.
Signed-off-by: Steve Sakoman <steve.sakoman@linaro.org>
On some boards we have flash mapped high in the address space with
considerably small window (say 0xFE000000 and 32MB). When we install
bigger chip (say 64MB) on such a board strange things happen
(flash_write() doesn't work at all, for ex). That's because cfi_flash
driver doesn't care about window size at all.
Of course, cleanest solution would probably be to just extend address
window to be able to map the whole flash but for legacy/compatibility
reasons some people prefer just truncate the flash size and never use
the upper part.
This patch adds an option for cfi_flash driver to handle this situation
properly. To achieve this we add the new function cfi_flash_bank_size()
which can be provided by the board code and weak-aliased to default
implementation that returns value from the CONFIG_SYS_FLASH_BANKS_SIZES
array if it's defined or 0 otherwise (the last case is added for
compatibility).
If non-zero flash bank size is provided and detected chip size is bigger
than provided address window size the warning will be displayed and
flash chip will be truncated.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Changed cfi_flash_bank_size() return type to unsigned long
to match caller function.
Signed-off-by: Wolfgang Denk <wd@denx.de>
This patch solves a problem with USB hanging under higher load on a
i.MX31 board. It falls into class of typical USB problems and fixes:
if you don't understand the real cause, add a delay somewhere.
The problem appeared after introduction of ELF relocation, which
results in smaller code, which appears to run faster (probably because
it fits better in the cache); turning off the instruction cache,
adding debug printf()s and increasing the delay have all been found to
make the problem go away.
Moving the original "udelay(1)" up in the code to it's new place made
the problem appear much less frequently. Increasing the delay to 2
microseconds then made the code run reliably in all (hour-long) tests.
To be on the safe side, we set it to 5 microseconds here.
Signed-off-by: Heiko schocher <hs@denx.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>
Commit 3ed1607 "USB: sync Queue Element Transfer Descriptor against
EHCI spec" added an "__attribute__ ((aligned (32)))" to the
declaration of struct qTD, as used for example in the Linux kernel as
well.
However, it turns out that this attribute causes errors in "usb start"
(like "ERROR: NOT USB_CONFIG_DESC 7b" and similar). Drop the attribute
again.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Dan Lykowski <lykowdk@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>
It is useful to know the EHCI-PCI hccr, hcor and hc_lenght to make sure it was
successfully registered, and at the correct location.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
