Commit graph

38289 commits

Author SHA1 Message Date
Simon Glass
ce02a71c23 tegra: dts: Sync tegra20 device tree files with Linux
Sync everything except the display panel, which will come in a future patch.
One USB port is left disabled since we don't want to support it in U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-07-05 13:19:08 -07:00
Simon Glass
862887d883 errno: Allow errno_str() to be used without CONFIG_ERRNO_STR
The pmic framework uses errno_str() and this requires board that use it to
enable CONFIG_ERRNO_STR to avoid a build error. Update the header to provide
a NULL error message when CONFIG_ERRNO_STR is not defined, and fix the build
error.

This will show as "(null)" when U-Boot prints it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-07-05 13:19:08 -07:00
Simon Glass
00e9e6d1ff errno: Add copyright header and header guard
Bring in a copyright for this file from cmd/pmic.c since this file was
submitted by the same author at around the same time. Also fix the missing
header guard.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-07-05 13:19:08 -07:00
Stephen Warren
f39a6a3277 pci: tegra: actually program REFCLK_CFG* on recent SoCs
On recent SoCs, tegra_pcie_phy_enable() isn't called; but instead
tegra_pcie_enable_controller() calls tegra_xusb_phy_enable(). However,
part of tegra_pcie_phy_enable() needs to happen in all cases. Move that
code to tegra_pcie_port_enable() instead.

For reference, NVIDIA's downstream Linux kernel performs this operation
in tegra_pcie_enable_rp_features(), which is called immediately after
tegra_pcie_port_enable(). Since that function doesn't exist in the U-Boot
driver, we'll just add it to the tail of tegra_pcie_port_enable() instead.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-07-05 11:14:32 -07:00
Stephen Warren
3cfc6be4a8 pci: tegra: correctly program PADS_REFCLK registers
The value that should be programmed into the PADS_REFCLK register varies
per SoC. Fix the Tegra PCIe driver to program the correct values. Future
SoCs will require different values in cfg0/1, so the two values are stored
separately in the per-SoC data structures.

For reference, the values are all documented in NV bug 1771116 comment 20.
The Tegra210 value doesn't match the current TRM, but I've filed a bug to
get the TRM fixed. Earlier TRMs don't document the value this register
should contain, but the ASIC team has validated all these values, except
for the Tegra20 value which is simply left unchanged in this patch.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-07-05 11:14:32 -07:00
Tom Rini
e8009beff6 Merge git://git.denx.de/u-boot-arc 2016-07-04 11:46:21 -04:00
Alexey Brodkin
c7dea6e259 arc: make global_data.h usable in assembly files
Currently on attempt to use global_data.h in an assembly file following
will happen:
-------------------->8-----------------
./arch/arc/include/asm/global_data.h: Assembler messages:
./arch/arc/include/asm/global_data.h:11: Error: bad instruction 'struct arch_global_data{'
./arch/arc/include/asm/global_data.h:12: Error: junk at end of line, first unrecognized character is `}'
scripts/Makefile.build:316: recipe for target 'arch/arc/lib/start.o' failed
-------------------->8-----------------

In this change we disable struct arch_global_data in ASM which fixes
the issue above.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2016-07-04 11:43:41 +03:00
Alexey Brodkin
7a54f5177a arc: Use "-mcpu=archs" instead of deprecated "-marchs" for ARC HS
Newer ARC toolchains don't support "-marchs" option any longer.
Instead "-mcpu=archs" should be used. What's also important older
toiolchains that support ARC HS cores will also happily accept
"-mcpu=archs" so that's a very safe move.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2016-07-04 11:43:40 +03:00
Tom Rini
8d24176a67 Merge branch 'master' of http://git.denx.de/u-boot-sunxi 2016-07-02 16:32:15 -04:00
Quentin Schulz
d2a6af0528 sunxi: Add defconfig and DTS file for Allwinner R16 EVB (Parrot)
The Parrot Board is an evaluation board with an Allwinner R16 (assumed
to be close to an Allwinner A33), 4GB of eMMC, 512MB of RAM, USB host
and OTG, a WiFi/Bluetooth combo chip, a micro SD Card reader, 2
controllable buttons, an LVDS port with separated backlight and
capacitive touch panel ports, an audio/microphone jack, a camera CSI
port, 2 sets of 22 GPIOs and an accelerometer.

The DTS file is identical to the one submitted to the upstream kernel.

Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-07-02 13:53:15 +02:00
Olliver Schinagl
9acebe8a18 sunxi: Add missing boot_media fields in the SPL header
Commit b19236fd1 ("sunxi: Increase SPL header size to 64 bytes to avoid
code corruption") Added defines for MMC0 and SPI as boot identification.
After verifying on an OLinuXino Lime2 with NAND and eMMC, the expected
values have been confirmed and added to spl.h

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-07-02 13:53:03 +02:00
Hans de Goede
cd8b35d2e1 sunxi: spl: Fix DRAM info printing
The switch to simple_printf was causing the SPL dram info to show as:

DRAM: u MiB

This fixes this by switching from %lu to %d for printing the DRAM size.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-07-02 13:50:53 +02:00
Tom Rini
68f7289b4f Merge branch 'master' of git://git.denx.de/u-boot-usb 2016-07-01 22:35:20 -04:00
Tom Rini
2f6b47061d Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2016-07-01 22:35:12 -04:00
Tom Rini
0e1e587ff4 Prepare v2016.07-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-07-01 17:43:17 -04:00
Tom Rini
20a41043fb Merge branch 'master' of git://git.denx.de/u-boot-uniphier 2016-07-01 17:43:06 -04:00
Steve Rae
d90bb43933 mmc: increase MMC SDHCI read status timeout
Otherwise,  ocassionally see errors like this:
  Flashing sparse image at offset 2078720
  Flashing Sparse Image
  sdhci_send_command: Timeout for status update!
  mmc fail to send stop cmd
  write_sparse_image: Write failed, block #2181088 [0]

This does not affect the actual writing speed, which is controlled by
the default value:
  CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT

It only increases the retries when reading:
  SDHCI_INT_STATUS
to avoid the timeout error.

Signed-off-by: Steve Rae <steve.rae@raedomain.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-07-01 17:42:57 -04:00
Lokesh Vutla
df6b506f16 ti_omap5_common: Find right dtb file for DRA72-RevC Evm
DRA72-Evm revC uses dra72-evm-revc.dtb. Update the same in env vatiables.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-07-01 17:42:57 -04:00
Masahiro Yamada
4632739202 autoboot: move bootdelay >= 0 check to abortboot()
Move the bootdelay >= 0 check to the caller, which simplifies
the callees.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2016-07-01 17:42:56 -04:00
Masahiro Yamada
09b9d9e55f autoboot: move CONFIG_SILENT_CONSOLE handling
Factor out the same code from the callees to the caller.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2016-07-01 17:42:56 -04:00
Masahiro Yamada
d8da8298ad autoboot: rename abortboot_{keyed, normal} to __abortboot
Because abortboot_keyed() and abortboot_normal() are not compiled
at the same time, we can rename both of them to __abortboot().
This allows to drop #ifdef from the caller.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2016-07-01 17:42:55 -04:00
Masahiro Yamada
2fbb8462b0 autoboot: remove CONFIG_ZERO_BOOTDELAY_CHECK
As the help message of CONFIG_BOOTDELAY says, CONFIG_BOOTDELAY=-2
means the autoboot with no delay, with no abort check even if
CONFIG_ZERO_BOOTDELAY_CHECK is defined.

To sum up, the autoboot behaves as follows:

 [1] CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=y
    autoboot with no delay, but you can abort it by key input

 [2] CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=n
    autoboot with no delay, with no check for abort

 [3] CONFIG_BOOTDELAY=-1
    disable autoboot

 [4] CONFIG_BOOTDELAY=-2
    autoboot with no delay, with no check for abort

As you notice, [2] and [4] come to the same result, which means we
do not need CONFIG_ZERO_BOOTDELAY_CHECK.  We can control all the
cases only by CONFIG_BOOTDELAY, like this:

 [1] CONFIG_BOOTDELAY=0
    autoboot with no delay, but you can abort it by key input

 [2] CONFIG_BOOTDELAY=-1
    disable autoboot

 [3] CONFIG_BOOTDELAY=-2
    autoboot with no delay, with no check for abort

This commit converts the logic as follow:
  CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=n
    --> CONFIG_BOOTDELAY=-2

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Christian Riesch <christian.riesch@omicronenergy.com>
Acked-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2016-07-01 17:42:55 -04:00
Masahiro Yamada
9060970f4d doc: bootdelay: drop explanation about CONFIG_BOOTDELAY from README
The same information now exists in common/Kconfig.  Do not duplicate
documentation from the point of view of maintainability.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2016-07-01 17:42:54 -04:00
Masahiro Yamada
ea72ee72f2 ARM: socfpga: move CONFIG_BOOTDELAY to Kconfig for IS1 board
This recently added board missed the tree-wide migration of
CONFIG_BOOTDELAY.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2016-07-01 17:42:54 -04:00
Andreas Dannenberg
4aae64c22a ARM: AM437x: Align HS device variant defconfig filename
Align the name of the defconfig file for high-security (HS) device variants
from the AM43xx family of SoCs with the corresponding name used for the
general purpose devices. This allows for easier cross-association of those
files and also provides room to grow from an HS device part number
perspective.

Furthermore, update and cleanup associated MAINTAINERS file.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Madan Srinivas <madans@ti.com>
2016-07-01 17:42:53 -04:00
Praneeth Bajjuri
8dfd6e2129 driver: qspi: correct QSPI disable CS reset value
Correcting QSPI disable/unselect CS reset value.
CTRL_CORE_CONTROL_IO_2: QSPI_MEMMAPPED_CS[10:8]

This is not causing any issue, but its better
to untouch the reserved bits.

Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Ravi Babu <ravibabu@ti.com>
2016-07-01 17:42:53 -04:00
Masahiro Yamada
e64a6b1141 ARM: uniphier: add external IRQ setup code
I will carry this work-around until it is cared in the kernel.
This looks up the AIDET node and sets up a register to handle
active low interrupt signals.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-07-02 05:44:30 +09:00
Masahiro Yamada
1013aef330 ARM: dts: uniphier: add AIDET nodes
The AIDET (ARM Interrupt Detector Add-on Circuit) is a kind of
syscon block related with the interrupt controller.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-07-02 05:44:30 +09:00
Masahiro Yamada
fc9da85c60 pinctrl: uniphier: add Ethernet pin-mux settings
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-07-02 05:44:30 +09:00
Masahiro Yamada
64c1cc4cc5 pinctrl: uniphier: avoid building unneeded pin-mux tables for SPL
SPL does not use all of the devices, so we can save some memory
footprint.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-07-02 05:44:30 +09:00
Masahiro Yamada
5e25b9d5d9 pinctrl: uniphier: support pin configuration for dedicated pins
PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration
(pin biasing, drive strength control), but not pin-muxing.

Allow to fill the mux value table with -1 for those pins; pins with
mux value -1 will be skipped in the pin-mux set function.  The mux
value type should be changed from "unsigned" to "int" in order to
accommodate -1 as a special case.

[ Linux commit: 363c90e743b50a432a91a211dd8b078d9df446e9 ]

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-07-02 05:44:29 +09:00
Masahiro Yamada
3379987e26 pinctrl: uniphier: split pinctrl driver for PH1-LD11 and PH1-LD20
PH1-LD11 and PH1-LD20 have much pin controlling in common, so I
added a single driver shared between them in the initial commit.

However, the Ethernet pin-mux settings I am going to add are
different with each other, and they may diverge more as the
progress of development.  Split it into two dedicated drivers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-07-02 05:44:29 +09:00
Masahiro Yamada
186c133444 pinctrl: uniphier: allow to have pinctrl node under syscon node
Currently, the UniPhier pinctrl driver itself is a syscon, but it
turned out much more reasonable to make it a child node of a syscon
because our syscon node consists of a bunch of system configuration
registers, not only pinctrl, but also phy, and misc registers.
It is difficult to split the node.  This commit allows to migrate to
the new DT structure.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-07-02 05:44:29 +09:00
Masahiro Yamada
c4adc50ea6 ARM: dts: uniphier: sync Device Trees with upstream Linux
I periodically sync Device Trees for better maintainability.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-07-02 05:44:29 +09:00
Masahiro Yamada
aac641bcf4 pinctrl: uniphier: remove unneeded pin group nand_cs1
This SoC does not support NAND CS1.  This place-holder is no longer
necessary.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-06-30 23:49:26 +09:00
Masahiro Yamada
69da34c073 pinctrl: uniphier: fix NAND pin-mux setting for PH1-LD11/LD20
My mistake in the initial support patch.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-06-30 23:49:26 +09:00
Masahiro Yamada
4d1065c8d8 pinctrl: uniphier: remove wrong pin-mux functions for ProXstream2
These are pin group names, not function names.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-06-30 23:49:26 +09:00
Masahiro Yamada
4cb9399e9b ARM: uniphier: fix typo "talbe"
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-06-30 23:49:26 +09:00
Bin Meng
ff6e156966 x86: coreboot: Remove the dummy pch driver
There is a dummy pch driver in the coreboot directory. This causes
drivers of its children fail to function due to empty ops. Remove
the whole file since it is no longer needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-06-29 10:08:15 +08:00
Tom Rini
44faff24f5 Merge git://git.denx.de/u-boot-fsl-qoriq 2016-06-28 15:59:05 -04:00
Tom Rini
6f0aea39ae configs: Re-sync after boot menu changes
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-06-28 15:54:00 -04:00
Abhimanyu Saini
dee01e426b armv8: dts: fsl: Remove cpu nodes from Layerscape DTSIs
Currently layescape SoCs are not using cpu nodes. So removing
them in favour of compatibly with  similar SoCs that
have different cores like LS2080A and LS2088A.

This has been tested on LS2080AQDS, LS1043ARDB, LS1012ARDB.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28 12:08:54 -07:00
Prabhakar Kushwaha
49cdce1635 armv8: fsl-layerscape: Append "A" in SoC name for ARM based SoCs
Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs.
like LS2080A, LS1043A, LS1012A.

So append "A" to SoC names.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28 12:08:53 -07:00
Peng Fan
1483151e84 mmc: fsl: introduce wp_enable
Introudce wp_enable. To check WPSPL, wp_enable needs to be set
to 1 in board code.

Take i.MX6UL for example, for some boards, they do not use WP singal,
so they does not configure USDHC1_WP_SELECT_INPUT, and its default
value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and
SION bit set. So USDHC controller can always get wp signal and WPSPL
shows write protect and blocks driver continuing. This is not what
we want to see, so add wp_enable, and if set to 0, just omit the
WPSPL checking and this does not effect normal working of usdhc
controller.

If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28 12:08:53 -07:00
Ye Li
84ecdf6da9 fsl_esdhc: Update clock enable bits for USDHC
The USDHC moves the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN,
HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec
register. The driver uses RSTA to replace the clock gate off
operation. But this is not a good solution because:
1. when using RSTA, we should wait this bit to clear by itself. This is not
   implemeneted in the code.
2. After RSTA is set, it is recommended that the Host Driver reset the
   external card and reinitialize it.

So in this patch, we change to use the vendorspec registers for these bits
operation.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28 12:08:53 -07:00
Peng Fan
f53225cce4 mmc: fsl: reset to normal boot mode when eMMC fast boot
When booting in eMMC fast boot, MMC host does not exit from
boot mode after bootrom loading image. So the first command
'CMD0' sent in uboot will pull down the CMD line to low and
cause errors.

This patch cleans the MMC boot register in "mmc_init" to put the
MMC host back to normal mode.

Also clear DLL_CTRL delay line settings at USDHC initialization
to eliminate the pre-settings from boot rom.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28 12:08:53 -07:00
Qianyu Gong
68aaa980c4 armv8: ls1043aqds: print FPGA info early for QSPI boot
Now I2C is initialized early enough to access FPGA so it supports to
show board info as early as other boot methods.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28 12:08:53 -07:00
Qianyu Gong
581ff00bf7 armv8: ls1043aqds: use configurable clock
Get the clocks from FPGA through I2C, if IFC is disabled.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28 12:08:43 -07:00
Peng Fan
faaef73f7e common: add new boot media kconfig entry
Add CONFIG_{SD|NAND|ONENAND|SPI|QSPI|SATA}_BOOT kconfig entries.

SoCs supports loading U-Boot from different medias to DRAM, such as
i.MX6/7 supports loading U-Boot to DRAM from sd/emmc/nand/qspi/spi/sata
and etc. For i.MX, imximage will generate different IVT headers according
to boot medias.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Christophe Ricard <christophe-h.ricard@st.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Francois Retief <fgretief@spaceteq.co.za>
Cc: Tom Rini <trini@konsulko.com>
2016-06-27 22:35:25 -04:00
Peng Fan
d14739ffe1 Kconfig: make NOR_BOOT a common option
Not only am335x supports booting from NOR, i.MX6 SoCs also
supports booting from NOR. Make NOR_BOOT a common
option to let different SoCs share it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Christophe Ricard <christophe-h.ricard@st.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Francois Retief <fgretief@spaceteq.co.za>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-06-27 22:32:07 -04:00