sama5's SFR has at offset 0x04 the DDR Configuration Register,
while sam9x60's SFR contains the EBI Chip Select Register. Add
a union to reconcile both boards.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
The Special Function Registers (SFR) are present in sam9x5 and
sam9x60 too, rename sama5_sfr to at91_sfr.h.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Add new board SAM9X60-EK using the ARM926 SAM9X60 SoC.
Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>
[tudor.ambarus@microchip.com:
- fix number of DRAM banks:
One DDR2-SDRAM (W972GG6KB 2 Gbit = 16 Mbit x 16 x 8 banks]
- drop SPL related macros
- drop memtest macros
- drop CONFIG_SPI_BOOT, CONFIG_SYS_USE_DATAFLASH related macros
- drop inclusion of asm/arch/at91sam9_smc.h]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Add Ethernet controller to dtsi file and enable it on sam9x60ek
platform connected with rmii.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
add device tree files for sam9x60ek board with below changes.
- Add initial device nodes (pmc, pinctrl, sdhc, dbgu & pit)
- Add the reg property for the pinctrl node.
- Add the "u-boot,dm-pre-reloc" property to determine which nodes
are used by the board_init_f stage.
Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>
[prasanthi.chellakumar@microchip.com: fix style/whitespace issues]
Signed-off-by: Prasanthi Chellakumar <prasanthi.chellakumar@microchip.com>
[nicolas.ferre@microchip.com:
- fix gclk,
- fix pio/pinctrl controller definition and allow to have more
than only PIOA for this SoC,
- removing pinctrl address]
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
[claudiu.beznea@microchip.com:
- use SAM9X60's compatible for pinctrl
- add drive strength and slew rate options for SDMMC0 pins.]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
[tudor.ambarus@microchip.com:
- u-boot,dm-pre-reloc property in dedicated file,
- fix pit len, starts from 0xFFFFFE40 and it is of len 0x10]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Add node for hlcld for u-boot logo display at boot.
This is compatible with the Precision Design Associates (PDA) TM5000 screen.
Timings are compatible with simple panel from Linux, panel name is
pda_91_00156_a0
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
qspi1 does not have an alias/seq number. This is required for
SPL default SF bus booting for the boards that have this SoC
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Add a function in SFR implementation that will open the DDR input
buffers.
This can be called at DRAM initialization time.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Add support for the SAMA5D27-WLSOM1-EK. It's based on the Microchip
WireLess SoM which contains the SAMa5D27 LPDDR2 2Gbits SiP.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
[eugen.hristev@microchip.com]: added u-boot specific dtsi and ported to 2019.10
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
The SPL device tree is missing the entires for gpio1, uart1, usdhc1 and
usdhc2. This creates the missing imx6q-logicpd-u-boot.dtsi file
which will enable these functions so SPL can properly setup UART, detect
microSD card, and startup.
Fixes: 8f4691e31a ("ARM: imx6q_logic: With SPL_OF_CONTROL enabled,
remove MMC init")
Signed-off-by: Adam Ford <aford173@gmail.com>
On HS devices the access to TRNG is restricted on the non-secure
ARM side, disable the node in DT to prevent firewall violations.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
The memory allocated to store the FIT image containing SYSFW and board
configuration data is statically defined to the largest size expected.
This was 269000 bytes but now needs to be grown to 276000 to make room
for the signatures attached to the board configuration data on High
Security devices.
Signed-off-by: Andrew F. Davis <afd@ti.com>
This patch restores commit c49d0ac38a ("ARM: dts: rmobile: Increase off-on
delay on the SD Vcc regulator"), which was accidentally dropped during DT
resync in commit 317d13ac63 ("ARM: dts: rmobile: Synchronize Gen3 DTs with
Linux 5.0").
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Fixes: 317d13ac63 ("ARM: dts: rmobile: Synchronize Gen3 DTs with Linux 5.0")
The commit 619f002db8 ("rockchip: make_fit_atf.py: fix loadables property
set error") fixed the double-loading of the primary atf-image, but didn't
take into account that there may be rare atf images with only that main
section present.
Right now this will result in a broken its due to the loadables section not
getting closed correctly, so fix that by adapting the guards around the loop.
The guards now protect against 0 segments when the bl31 binary doesn't
contain any section and 1 segment when only a core atf section is present.
Fixes: 619f002db8 ("rockchip: make_fit_atf.py: fix loadables property set error")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
Originally the cpuid var the value gets read into was defined as
u8 cpuid[RK3399_CPUID_LEN];
hence the sizeof(cpuid) would return the correct the correct number
of array elements.
With the move to a separate function cpuid becomes a pointer and
sizeof(cpuid) hence returns the pointer size - 8 in the arm64 case.
We do have the actual id length available as function param so use
it for actual amount of bytes to read.
Fixes: 0482538499 ("rockchip: rk3399: derive ethaddr from cpuid")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
Tinker board needs to mux all the sdmmc gpio and
activate the regulator connected to bank 7. Remove
all the bank that are not in use and mark them as dm,spl
so-that it would initialize at SPL.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
newline \n was missed in fdt_path_offset, error loop.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
ROCKCHIP_BROM_HELPER is selected as if TPL/SPL ROCKCHIP_BACK_TO_BROM
has been defined, so drop the explicit enablement for vyasa board.
This change is supposed to missed during config move to
other locations, and missed to drop the same.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
According to the latest am572x[1] and dra74x[2] data manuals, mmc3
default, hs, sdr12 and sdr25 modes use iodelay values given in
MMC3_MANUAL1. Set the MODE_SELECT bit for these so that manual mode is
selected and correct iodelay values are configured.
[1] http://www.ti.com/lit/ds/symlink/am5728.pdf
[2] http://www.ti.com/lit/ds/symlink/dra746.pdf
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
API get_ti_sci_handle() is relying on the device-tree node name
to be "dmsc" for probing the ti_sci device. But with the introduction
of debug messages for dmsc, the node name changed to dmsc@44083000.
Because of this ti_sci is never probed cause a boot failure. Instead
of relying on device-tree node name, use the first available firmware
node for probing ti_sci.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The da8xx GPIO driver is available with DM_GPIO support. This
patch enables the CMD_GPIO, CMD_DM, and DM_GPIO and DA8XX_GPIO.
Signed-off-by: Adam Ford <aford173@gmail.com>
Add device tree from Linux for driver model conversion
and enable OF_CONTROL. This will remove the following compile
warning:
==================================================
Device Tree Source is not correctly specified.
Please define 'CONFIG_DEFAULT_DEVICE_TREE'
or build with 'DEVICE_TREE=<device_tree>' argument
===================================================
Target was compile tested, build was clean.
Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
In SerDes protocol 0x13BB, lane C was erroneously assigned
to PCIE1, this is now updated to PCIE2
Fixes: 36f50b7523 ("armv8: ls1028a: Add other serdes
protocal support")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The correct config entry is CONFIG_PCIE_LAYERSCAPE and this
typo results in skipping the fixup of Linux PCIe DT nodes.
Also enable the fixup when Layerscape Gen4 controller driver
is enabled.
Fixes: 4da0e52c9d (armv8: fsl-layerscape: fix config dependency
for layerscape pci code)
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
By default, i2c input clock is programmed at
platform clk / 2 in u-boot, but this is not
correct for all the platforms,
Update I2C clock divider's default values as per
SoC (LS1012A, LS1028A, LX2160A and LS1088A).
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The SP805-WDT module on LS1028A requires configuration of PMU's
PCTBENR register to enable watchdog counter decrement and reset
signal generation. The watchdog clock needs to be enabled first.
Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com>
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add the device-tree structure describing the MUX in board dts.
QDS board has an on-board RGMII PHY and 4 slots for extension cards.
All these can be accessed over MDIO through a MDIO MUX controlled
over I2C.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Use obj-$(config) instead of #ifdef $config to make the code looks
clean, and move the misc_init for U-Boot proper only.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The rk3188/Makefile already depends on !TPL_BUILD, so no need to add
this again in parent Makefile, remove it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
- fix bcm2835_sdhost to wait long enough for a transfer to complete
- increase kernel image size from 8 MB to 64 MB on arm64
- add support for RPi4
- add prefixes for raspberry pi related stuff to git-mailrc
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Merge tag 'rpi-next-2019.10' of https://github.com/mbgg/u-boot
- fix mailbox status register used for polling
- fix bcm2835_sdhost to wait long enough for a transfer to complete
- increase kernel image size from 8 MB to 64 MB on arm64
- add support for RPi4
- add prefixes for raspberry pi related stuff to git-mailrc
This clock has a different mbox ID so have this included in the relevant
header file.
Signed-off-by: Andrei Gherzan <andrei@balena.io>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Define two target configs for Raspberry Pi 4 (32 and 64bit) and the
corresponding BCM2838* configs.
Be aware of the current limitation in firmware which requires an
explicit configuration to force the arm in 64bit mode when the
respective target is used.
Signed-off-by: Andrei Gherzan <andrei@balena.io>
[mb: rename BCM2838 -> BCM2711]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Devices of bcm283x have different base address, depending if they are on
bcm2835 or bcm2836/7. Use BCM283x_BASE depending on the SoC you want to
build and only add the offset in the header files.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Andrei Gherzan <andrei@balena.io>
Before we can send a message to the mailbox we have to check that there
is space to do so. Therefore we poll the status register. But up to now
the wrong status register, the one of mailbox 0, was checked. Fix this
by polling the status regiser of mailbox 1.
Signed-off-by: Fabian Vogt <fvogt@suse.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
[mb: rename registers and update commit message]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
