Commit graph

73053 commits

Author SHA1 Message Date
Christine Gharzuzi
f596b01b9a phy: marvell: fix handling of unconnected comphy
- the default value of comphy pipe selector is set to PCIe (x4)
  in case of unconnected comphy the default value remains 0x4
  which may lead to several issues with comphy initialization.

- this patch adds SMC call that powers off the comphy lane in case of
  unconnected comphy.

Change-Id: I196b2916518dd8df3b159ffa85e2989b8e483087
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29 07:45:24 +02:00
Igal Liberman
5f41aaf4c3 phy: marvell: pass sgmii id to firmware
Currently, we don't pass id for SGMII 0/1.
A bug in comphy selector configuration was found (in comphy
firmware), after fixing it, SGMII0/1 have different configuration,
so we need to pass the ID the firmware.

Change-Id: Idcff4029cc9cf018278e493221b64b33574e0d38
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29 07:45:24 +02:00
Grzegorz Jaszczyk
cd2caff77f phy: marvell: cp110: clean up driver after it was moved to atf
Change-Id: I358792a96c13b54e700c05227cc7a8f6bd584694
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
2021-04-29 07:45:24 +02:00
Grzegorz Jaszczyk
affd61f51c phy: marvell: cp110: remove both phy and pipe selector configuration
Now the comphy configuration is handled in atf, therefore there is no
need to configure phy or pipe selector in u-boot, it is configured by
atf for each particular pair: lane and mode.

Change-Id: I0bebf8d5ff66dbeb6bf9ef90876195938a8eb705
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
2021-04-29 07:45:24 +02:00
Grzegorz Jaszczyk
2e28b597fa phy: marvell: cp110: let the firmware perform training for XFI
Replace the XFI training with appropriate SMC call, so the firmware will
perform exact initialization.

Update Stefan 2021-03-23:
Move comphy_smc() function to an earlier place - necessary for the
mainline merge.

Change-Id: I789b130b05529dc80dadcf66aef407d93595b762
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Igal Liberman <igall@marvell.com>
2021-04-29 07:45:24 +02:00
Grzegorz Jaszczyk
f635c3b3a2 phy: marvell: cp110: let the firmware configure comphy for USB
Replace the comphy initialization for USB with appropriate SMC call,
so the firmware will execute required serdes configuration.

Change-Id: I7f773c0dfac70db9dd2653de2cdcfac577e78c4e
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29 07:45:24 +02:00
Grzegorz Jaszczyk
26d9763f3b phy: marvell: cp110: let the firmware configure comphy for RXAUI
Replace the comphy initialization for RXAUI with appropriate SMC call,
so the firmware will execute required serdes configuration.

Change-Id: Iedae0285fb283e05bb263a8b4ce46e8e7451a309
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
2021-04-29 07:45:24 +02:00
Marcin Wojtas
5ed3dc27bb phy: marvell: cp110: remove unused definitions
Even if comphy types of SATA2/SATA3/SGMII3 and comphy speeds of
1.5G/3G/6.25G were referenced in the driver non configuration (dts)
was using it.

This patch removes unused definitions.

Change-Id: I53ed6f9d3a82b9d18cb4e488bc14d3cf687f9488
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2021-04-29 07:45:24 +02:00
Igal Liberman
b21e1f36d4 phy: marvell: enable comphy info prints for all devices
Change-Id: I3b97253e7102a0868440a9e0200acc1c7919c743
Signed-off-by: Igal Liberman <igall@marvell.com>
2021-04-29 07:45:24 +02:00
Igal Liberman
e49cdbe10b phy: marvell: add RX training command
This patch adds support for running RX training using new command called
"rx_training"
Usage:
rx_training - rx_training <cp id> <comphy id>

RX training allows to improve link quality (for SFI mode)
by running training sequence between us and the link partner,
this allows to reach better link quality then using static configuration.

Change-Id: I818fe67ccaf19a87af50d4c34a9db7d6802049a5
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
2021-04-29 07:45:24 +02:00
Igal Liberman
7b27e608f8 phy: marvell: save comphy_map_data priv structure
This allows the lower level driver access to comphy map data
(required for RX training support, which is introduced
in the following patches).

Change-Id: Ib7ffdc4b32076c01c3a5d33f59552c9dfc6b12fa
Signed-off-by: Igal Liberman <igall@marvell.com>
2021-04-29 07:45:24 +02:00
Igal Liberman
c2bf42f5fd phy: marvell: fix several minor bugs in comphy_probe
If fdtdec_get_int can't find speed, set COMPHY_SPEED_INVALID
If fdtdec_get_int can't find type, set COMPHY_TYPE_INVALID
Move the error print if phy-type is invalid
Add continue to the probe loop (in a case of invalid phy)
Cosmetic changes

Change-Id: I0c61b40bfe685437426fe907942ed338b7845378
Signed-off-by: Igal Liberman <igall@marvell.com>
2021-04-29 07:45:24 +02:00
Igal Liberman
3e69b4abff phy: marvell: cp110: utmi: update analog parameters according to latest ETP
Add UTMI analog parameters initialization values according to
latest ETP.

Change-Id: I5bcca205a3995202a18ff126f371a81f69e205c8
Signed-off-by: Igal Liberman <igall@marvell.com>
2021-04-29 07:45:24 +02:00
Omri Itach
22bc868e49 phy: marvell: cp110: initialize only enabled UTMI units
UTMI should be initialized only for enabled device tree nodes.

This fix overrides current internal configuration array
entry with the next DT entry data if error is detected
during the current DT entry parsing or the current port
is disabled.

This way the internal configuration structure will only
contain valid ports information obtained from the DT.

Change-Id: I9c43c6a5d234e15ae9005d1c9bc983fc1f3544b8
Signed-off-by: Omri Itach <omrii@marvell.com>
Signed-off-by: Ken Ma <make@marvell.com>
2021-04-29 07:45:24 +02:00
Igal Liberman
89351ba4c8 phy: marvell: add missing speed during info prints
In get_speed_string() we have an array (speed_strings[])
which includes all possible speed strings.
This array size and content must be aligned to the speed
defines in comphy_data.h.

This patch adds missing 5.125G speed, aligns speed_strings[]
and fixes incorrect printing when speed > 5.0G.

Change-Id: I9900d23595094be321be0c62fcaa88036324568e
Signed-off-by: Igal Liberman <igall@marvell.com>
2021-04-29 07:45:24 +02:00
Igal Liberman
2dbba24088 phy: marvell: rename comphy related definitions to COMPHY_XX
Currently, all comphy definitions are PHY_TYPE_XX and PHY_SPEEED_XX.
Those definition might be confused with MDIO PHY definitions.

This patch does the following changes:
 - PHY_TYPE_XX --> COMPHY_TYPE_XX
 - PHY_SPEED_XX --> COMPHY_SPEED_XX

This improves readability, no functional change.

Change-Id: I2bd1d9289ebbc5c16fa80f9870f797ea1bcaf5fa
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2021-04-29 07:45:24 +02:00
jinghua
4568e2041c phy: marvell: add comphy type PHY_TYPE_USB3
- For some Marvell SoCs, like armada-3700, there are both
  USB host and device controller, but on PHY level the
  configuration is the same.
- The new type supports both USB device and USB host
- This patch is cherry-picked from u-boot-2015 as-is.

Change-Id: I01262027edd8ec23391cff6fb409b3009aedfbb9
Signed-off-by: jinghua <jinghua@marvell.com>
Signed-off-by: Ken Ma <make@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
2021-04-29 07:45:23 +02:00
Stefan Roese
1c817c27e6 arm: octeontx2: cn9130-crb.dtsi: Disable eth2 for now
Because of the incorrectly supported SGMII_2500 mode, this patch
disables eth2 for now until this issue will be fixed in mainline.

Also fix an incorrect comment.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Marek Behun <marek.behun@nic.cz>
2021-04-29 07:45:23 +02:00
Konstantin Porotchkin
c405226c34 arm: octeontx2: Add Octeon TX2 CN9130 CRB support
This patch adds the base support for the Marvell Octeon TX2 CN9130 CRB.
Not all interfaces are supported fully yet.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-29 07:45:13 +02:00
Konstantin Porotchkin
236f17ce14 arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN9130 CRB
This patch adds the dtsi/dts files needed to support the Marvell
Octeon TX2 CN9130 CRB. This is only the base port with not all
interfaces supported fully.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-29 07:39:15 +02:00
Konstantin Porotchkin
c864c41f19 arm: armada: configs: Move environment location for mvebu
Move the default environment location to the end of 4MB flash
region. This change allows to accomodate larger flash boot
images making space for forthcoming code changes.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-29 07:39:15 +02:00
Konstantin Porotchkin
b1c81b4ced arm: armada: dts: Add support for ap807-based platforms
Add support for SoCs based on AP807 die.
Remove unused include file for Armada-8020 SoC.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-29 07:39:15 +02:00
Konstantin Porotchkin
a0ba97e561 arm: armada: dts: Use a single dtsi for cp110 die description
Use a single dtsi file for CP110 die instead of master/slave.
Moving to single file will allow miltiple DTSI inclusions with
re-defined CP index and name.
This change will also allow support for SoCs containing more than
two CP110 dies on board.
Move pin control definitions from CP110 DTS to board DTS files

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-29 07:39:15 +02:00
Konstantin Porotchkin
9f27bcc32f cmd/mvebu: fix the bubt command
- fix the dependency for MMC boot (add XENON to MVEBU_MMC)
- fix the bubt destination assignment (missing # in "else" case)

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-29 07:39:15 +02:00
Konstantin Porotchkin
fec8c900c8 power: regulator: Add support for regulator-force-boot-off
Add support for regulator-force-boot-off DT property.
This property can be used by the board/device drivers for
turning off regulators on early init stages as pre-requisite
for the other components initialization.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-04-29 07:38:57 +02:00
Tom Rini
c306b24948 Merge https://source.denx.de/u-boot/custodians/u-boot-usb 2021-04-28 18:35:54 -04:00
Tom Rini
9c211075d0 - net: designware: fix PHY reset with DM_MDIO, fixing boot of (at least) Odroid-C4
-----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAmCJg4wACgkQd9zb2sjI
 SdHekBAAt53MzWI3wl+wrbFDYjGOqWcV8yIRqwqB6zoHN1WTQqauKE/42fh1r8mY
 Wek26poY6q9VGTskT/OCh1WLPnvqZXEsuJXSHAMZC3m2bjjmoqDDHGnXWQD2RLGZ
 RTOqLO0r50Gh1sKwV4oAVZw4FINwPpd5zLCTxD9jSlT7J9ZhHrn+1FFk+Kvsct4e
 7HTASAz3WZPKLYzBVJnrNiX7U3K92d/sBQgo8bZGpAebjmyjG5syJMrOQgRc7TWx
 PRsDmp7Yn+HHPteE8+3D5DkAuMSsCYL3hbH6SlNIuF7wrCVdhER2cYXpccgD2dEt
 YdBUjUCJlHg53timjAmkF/HQPSE1EZCpt9hHvcMb0G7a7BfN/3JNpdws4e2z6Shn
 pHJEgKdt/S/a+v2x529ElBDwEqcVaLYYOkIKhv29sif18+/3IzpfCWgD8/NWGoo8
 QePQ6JnyA37/2poY0r7/T4oI/Q2YAhdkIOWnUTwfOIMSs+/jJjbTPSouLdr6bPTE
 UYohCv8uzIWMhG4F41YW2tU6P5WtXWWKCYBSoZ8sODVc985g89Wue3PFm20y551F
 HRzF0jeIdYAMYb0UipUbGtP4/QwsTmMOjz1eMrsfbgo5slYIIGgnSe7zv5AgAbZI
 S7DI8OhMLhsIXLqPsApoHs/HR3mxd6NwOnXfyb5HoyjOTkfaZ4Y=
 =kBLz
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-amlogic-20210428' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- net: designware: fix PHY reset with DM_MDIO, fixing boot of (at least) Odroid-C4
2021-04-28 14:22:43 -04:00
Neil Armstrong
98b8204626 net: designware: fix PHY reset with DM_MDIO
The dw_eth_pdata is not accessible from the mdio device, it gets the mdio bus plat
leading to random sleeps (-10174464 on Odroid-HC4).

This moves the dw_mdio_reset function to a common one taking the ethernet
device as parameter and use it from the dw_mdio_reset and dm_mdio variant functions.

Fixes: 5160b4567c ("net: designware: add DM_MDIO support")
Reported-by: Mark Kettenis <mark.kettenis@xs4all.nl>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-04-28 17:45:26 +02:00
Marek Vasut
53396d67ba usb: ehci-mx6: Limit PHY address parsing to !CONFIG_PHY
For systems which use generic PHY support and implement USB PHY driver,
the parsing of PHY properties is unnecessary, disable it.

Signed-off-by: Marek Vasut <marex@denx.de>
Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-28 17:16:18 +02:00
Marek Vasut
94657482f3 mtd: cfi: Fix PPB lock status readout
According to S26KL512S datasheet [1] and S29GL01GS datasheet [2],
the procedure to read out PPB lock bits is to send the PPB Entry,
PPB Read, Reset/ASO Exit. Currently, the code does send incorrect
PPB Entry, PPB Read and Reset/ASO Exit is completely missing.

The PPB Entry sent is implemented by sending flash_unlock_seq()
and flash_write_cmd(..., FLASH_CMD_READ_ID). This translates to
sequence 0x555:0xaa, 0x2aa:0x55, 0x555:0x90=FLASH_CMD_READ_ID.
However, both [1] and [2] specify the last byte of PPB Entry as
0xc0=AMD_CMD_SET_PPB_ENTRY instead of 0x90=FLASH_CMD_READ_ID,
that is  0x555:0xaa, 0x2aa:0x55, 0x555:0xc0=AMD_CMD_SET_PPB_ENTRY.
Since this does make sense, this patch fixes it and thus also
aligns the code in flash_get_size() with flash_real_protect().

The PPB Read returns 00h in case of Protected state and 01h in case
of Unprotected state, according to [1] Note 83 and [2] Note 17, so
invert the result. Moreover, align the arguments with similar code
in flash_real_protect().

Finally, Reset/ASO Exit command should be executed to exit the PPB
mode, so add the missing reset.

[1] https://www.cypress.com/file/213346/download
    Document Number: 001-99198 Rev. *M
    Table 40. Command Definitions, Nonvolatile Sector Protection
    Command Set Definitions
[2] https://www.cypress.com/file/177976/download
    Document Number: 001-98285 Rev. *R
    Table 7.1 Command Definitions, Nonvolatile Sector Protection
    Command Set Definitions

Fixes: 03deff433e ("cfi_flash: Read PPB sector protection from device for AMD/Spansion chips")
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-28 10:29:36 +02:00
Tom Rini
939c4934c8 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-04-28 10:05:13 +02:00
Neil Armstrong
b669db869b reset: fix reset_get_by_index_nodev index handling
This fixes an issue getting resets index 1 and 3+, the spurius "> 0"
made it return the index 0 or 1, whatever index was passed.

The dm_test_reset_base() did not catch it, but the dm_test_reset_base() extension
catches it and this fixes the regression.

This also fixes a reggression on Amlogic G12A/G12B SoCs, where HDMI output was disable
even when Linux was booting.

Fixes: ea9dc35aab ("reset: Get the RESET by index without device")
Reported-by: B1oHazard <ty3uk@mail.ua>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-28 10:05:13 +02:00
Neil Armstrong
49f352dc33 test: reset: Extend base reset test to catch error
With this extended test, we get the following failure :

=> ut dm reset_base
Test: dm_test_reset_base: reset.c
test/dm/reset.c:52, dm_test_reset_base(): reset_method3.id == reset_method3_1.id: Expected 0x14 (20), got 0x2 (2)
Test: dm_test_reset_base: reset.c (flat tree)
test/dm/reset.c:52, dm_test_reset_base(): reset_method3.id == reset_method3_1.id: Expected 0x14 (20), got 0x2 (2)
Failures: 2

A fix is needed in reset_get_by_index_nodev() when introduced in [1].

[1] ea9dc35aab ("reset: Get the RESET by index without device")

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-28 10:05:13 +02:00
Yuichiro Goto
b104caa9a4 IOMUX: Fix buffer overflow in iomux_replace_device()
Use of strcat() against an uninitialized buffer would lead
to buffer overflow. This patch fixes it.

Fixes: 694cd5618c ("IOMUX: Introduce iomux_replace_device()")
Signed-off-by: Yuichiro Goto <goto@k-tech.co.jp>
Cc: Peter Robinson <pbrobinson@gmail.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
2021-04-28 10:05:13 +02:00
Dario Binacchi
48594c38ed pinctrl: single: fix a never true comparison
As reported by Coverity Scan for Das U-Boot, the 'less-than-zero'
comparison of an unsigned value is never true.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
2021-04-28 10:05:13 +02:00
Dario Binacchi
10221d2847 pinctrl: single: check function mask to be non-zero
Otherwise it can generate a division by zero, which has an undefined
behavior.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-04-28 10:05:13 +02:00
Rasmus Villemoes
c6ecb2f81e Makefile: fix generation of defaultenv.h from empty initial file
When CONFIG_USE_DEFAULT_ENV_FILE=y and the file
CONFIG_DEFAULT_ENV_FILE is empty (or at least doesn't contain any
non-comment, non-empty lines), we end up feeding nothing into xxd,
which in turn then outputs nothing. Then blindly appending ", 0x00"
means that we end up trying to compile (roughly)

const char defaultenv[] = { , 0x00 }

which is of course broken.

To fix that, change the frobbing of the text file so that we always
end up printing an extra empty line (which gets turned into that extra
nul byte we need) - that corresponds better to the binary format
consisting of a series of key=val nul terminated strings, terminated
by an empty string.

Reported-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2021-04-28 10:05:13 +02:00
Qu Wenruo
6b4880e63f fs: btrfs: fix the false alert of decompression failure
There are some cases where decompressed sectors can have padding zeros.

In kernel code, we have lines to address such situation:

        /*
         * btrfs_getblock is doing a zero on the tail of the page too,
         * but this will cover anything missing from the decompressed
         * data.
         */
        if (bytes < destlen)
                memset(kaddr+bytes, 0, destlen-bytes);
        kunmap_local(kaddr);

But not in U-boot code, thus we have some reports of U-boot failed to
read compressed files in btrfs.

Fix it by doing the same thing of the kernel, for both inline and
regular compressed extents.

Reported-by: Matwey Kornilov <matwey.kornilov@gmail.com>
Link: https://bugzilla.suse.com/show_bug.cgi?id=1183717
Fixes: a26a6bedaf ("fs: btrfs: Introduce btrfs_read_extent_inline() and btrfs_read_extent_reg()")
Signed-off-by: Qu Wenruo <wqu@suse.com>
2021-04-28 10:05:13 +02:00
Samuel Holland
2e1af1e3e7 arm: zimage: Use correct symbol to hide messages in SPL
When zImage support was added to SPL, the messages were hidden to reduce
code size. However, the wrong config symbol was used. Since this file is
only built when CONFIG_SPL_FRAMEWORK=y, the messages were always hidden.

Use the correct symbol so the messages are printed in U-Boot proper.
Also use IS_ENABLED to drop the #ifdef.

Fixes: 431889d6ad ("spl: zImage support in Falcon mode")
Signed-off-by: Samuel Holland <samuel@sholland.org>
2021-04-28 10:05:13 +02:00
Rasmus Villemoes
4b37a83dc4 powerpc: introduce CONFIG_CACHE_FLUSH_WATCHDOG_THRESHOLD
When flush_cache() is called during boot on our ~7M kernel image, the
hundreds of thousands of WATCHDOG_RESET calls end up adding
significantly to boottime. Flushing a single cache line doesn't take
many microseconds, so doing these calls for every cache line is
complete overkill.

The generic watchdog_reset() provided by wdt-uclass.c actually
contains some rate-limiting logic that should in theory mitigate this,
but alas, that rate-limiting must be disabled on powerpc because of
its get_timer() implementation - get_timer() works just fine until
interrupts are disabled, but it just so happens that the "big"
flush_cache() call happens in the part of bootm where interrupts are
indeed disabled. [1] [2] [3]

I have checked with objdump that the generated code doesn't change
when this option is left at its default value of 0: gcc is smart
enough to see that the ">=" comparison is tautologically true, hence
all assignments to "flushed" are eliminated as dead stores.

On our board, setting the option to something like 65536 ends up
reducing total boottime by about 0.8 seconds.

[1] https://patchwork.ozlabs.org/project/uboot/patch/20200605111657.28773-1-rasmus.villemoes@prevas.dk/
[2] https://lists.denx.de/pipermail/u-boot/2021-April/446906.html
[3] https://lists.denx.de/pipermail/u-boot/2021-April/447280.html

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-04-28 10:05:13 +02:00
Rasmus Villemoes
b18352f2ba powerpc: lib: remove leftover CONFIG_5xx
CONFIG_5xx hasn't existed since commit 5025897774 (powerpc, 5xx:
remove support for 5xx). Remove this last mention of it.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-04-28 10:05:13 +02:00
Rasmus Villemoes
17bd5cce7e allow opting out of WATCHDOG_RESET() from timer interrupt
Having WATCHDOG_RESET() called automatically from the timer interrupt
runs counter to the idea of a watchdog device - if the board runs into
an infinite loops with interrupts still enabled, the watchdog will
never fire.

When using CONFIG_(SPL_)WDT, the watchdog_reset function is a lot more
complicated than just poking a few SOC-specific registers - it
involves accessing all kinds of global data, and if the interrupt
happens at the wrong time (say, in the middle of an WATCHDOG_RESET()
call from ordinary code), that can end up corrupting said global data.

Allow the board to opt out of calling WATCHDOG_RESET() from the timer
interrupt handler by setting CONFIG_SYS_WATCHDOG_FREQ to 0 - as that
setting is currently nonsensical (it would be compile-time
divide-by-zero), it cannot affect any existing boards.

Add documentation for both the existing and extended meaning of
CONFIG_SYS_WATCHDOG_FREQ.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-04-28 10:05:13 +02:00
Rasmus Villemoes
f9fb4c462b timer: mpc83xx_timer: fix build with CONFIG_{HW_, }WATCHDOG
The code, which is likely copied from arch/powerpc/lib/interrupts.c,
lacks a fallback definition of CONFIG_SYS_WATCHDOG_FREQ and refers to
a non-existing timestamp variable - obviously priv->timestamp is
meant.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-04-28 10:05:13 +02:00
Rasmus Villemoes
d0c94749dc watchdog: use time_after_eq() in watchdog_reset()
Some boards don't work with the rate-limiting done in the generic
watchdog_reset() provided by wdt-uclass.

For example, on powerpc, get_timer() ceases working during bootm since
interrupts are disabled before the kernel image gets decompressed, and
when the decompression takes longer than the watchdog device
allows (or enough of the budget that the kernel doesn't get far enough
to assume responsibility for petting the watchdog), the result is a
non-booting board.

As a somewhat hacky workaround (because DT is supposed to describe
hardware), allow specifying hw_margin_ms=0 in device tree to
effectively disable the ratelimiting and actually ping the watchdog
every time watchdog_reset() is called. For that to work, the "has
enough time passed" check just needs to be tweaked a little to allow
the now==next_reset case as well.

Suggested-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-28 10:05:13 +02:00
Tom Rini
48179af9d2 Prepare v2021.07-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-04-28 10:05:13 +02:00
Marek Vasut
1b2d1d774a ARM: rmobile: Enable NVMe support on RCar3
Enable support for PCIe NVMe devices.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-04-28 10:05:12 +02:00
Marek Vasut
ee0a7760fd ARM: rmobile: Enable CONFIG_SYS_FLASH_PROTECTION
Enable CONFIG_SYS_FLASH_PROTECTION on Salvator-X(S), ULCB, Ebisu,
which means the Spansion HF PPB protection bits can be operated
using the 'protect' U-Boot command.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2021-04-28 10:05:12 +02:00
Marek Vasut
c408ce283b clk: renesas: Synchronize Gen2 MSTP teardown tables
Synchronize Gen2 MSTP teardown tables with datasheet Rev.2.00
Feb 01, 2016. This corrects the following bits:
  - added H2 MSTP3[10] SCIF2
  - added H2/M2/E2 MSTP7[29] TCON
  - removed E2 MSTP5[22] Thermal Sensor
  - removed E2 MSTP10[31,24:22] SRC0, SRC7:9

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2021-04-28 10:05:12 +02:00
Marek Vasut
40c9728d24 clk: renesas: Only ever access documented bits in clock driver teardown
The clock driver used a heavy-handed approach where it turned off
all available clocks, while also possibly setting bits which are not
documented in the R-Car datasheet. Update the tables so that only
the bits which are documented are set or cleared when tearing down
the clock driver.

Note that the only clock left running before booting Linux are now
MFIC, INTC-AP, INTC-EX and SCIF2 / SCIF0 on V3x.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2021-04-28 10:05:12 +02:00
Andre Przywara
fbe127f7b5 sunxi: DT: A64: Update devicetree files from Linux 5.12
Import updated devicetree files from the Linux v5.12 release.

Besides some node and audio port renames this changes the PHY modes to
either rgmii-id or rgmii-txid. From the board files the Pinephone sees
a lot of updates.

This also adds the long missing USB PHY property for controller 0, which
allows the U-Boot PHY driver to eventually use port 0 in host mode
(pending another U-Boot patch).

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
2021-04-28 10:05:12 +02:00