When referring to PCIe and USB 'endpoint' is the standard naming
convention.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Remy Bohmer <linux@bohmer.net>
Need to reload the loop counters to keep from corrupting hardware loops.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Crashes rarely happen in the CPLB miss handler compared to the rest of
U-Boot code, so disable hardware tracing when processing misses. This
way a crash due to other functions will be shown properly.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The single initcode function was growing unwieldy, so split it up the
distinct steps into their own function. This should making digesting the
result much easier on people.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The length of the sections is fixed at link time, so let the linker do the
calculation rather than doing it ourselves at runtime.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Add support to configure bus parking mode and master in bus arbitration
configuration (ACR). Add this for the kmeter1 port:
Configure bus arbiter with recommended values from Freescale
to improve bus latency/throughput for application with
intensive QuiccEngine activity.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The memory controller could already be enabled, when spd_sdram() is
called. This could be the case for example, when the SDRAM is initialized
by the JTAG debugger.
The "sync" after the register access via the accessor function is
still needed, because the macro uses the sync before the real write
is done. So until not all accesses are converted to using accessor
functions, this sync still needs to be made "manually" here.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd.eu>
Acked-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
In chip-select interleaving case, we also need set the ODT_RD_CFG
and ODT_WR_CFG in cs1_config register.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Different boards may require different settings of Dynamic ODT (Rtt_Wr).
We provide a means to allow the board specific code to provide its own
value of Rtt_Wr.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
add the override for write leveling sampling and
start time according to specific board.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but
It should be set to tXP parameter, tXP=max(3CK, 7.5ns)
2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but
It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter
We are setting the mode register MR0[A12]='1'
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We incorrectly had the sense of PME_CLK_SEL, FM1_CLK_SEL, FM2_CLK_SEL
backwards so we report the wrong frequency.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We already map the page cache-inhibited. There is no reason we
shouldn't also be marking it guarded to prevent speculative accesses.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We need to add the readback to bootpage translation LAW
to make it effect.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Now that we track which TLB CAM entries are used we can allocate
entries on the fly. Change the SPD DDR TLB setup code to assume
we use at most 8 TLBs (or the number free, which ever is fewer).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We need to track which TLB CAM entries are used to allow us to
"dynamically" allocate entries later in the code. For example the SPD
DDR code today hard codes which TLB entries it uses. We can now make
that pick entries that are free.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
All users of is_fsl_pci_agent have been converted to fsl_is_pci_agent
that uses the standard PCI programming model to determine host vs
agent/end-point.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The FSL_CORENET platforms use a completely different means to determine
which PCIe port is enabled as well as if its a host or agent/end-point.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The e500mc core supports the ability to stash into the L1 or L2 cache,
however we need to uniquely identify the caches with an id.
We use the following equation to set the various stash-ids:
32 + coreID*2 + 0(L1) or 1(L2)
The 0 (for L1) or 1 (for L2) matches the CT field used be various cache
control instructions.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The header files usb.h and usbdescriptors.h have the same nameed
structure definitions for
usb_config_descriptor
usb_interface_descriptor
usb_endpoint_descriptor
usb_device_descriptor
usb_string_descriptor
These are out right duplicates in usb.h
usb_device_descriptor
usb_string_descriptor
This one has extra unused elements
usb_endpoint_descriptor
unsigned char bRefresh
unsigned char bSynchAddress;
These in usb.h have extra elements at the end of the usb 2.0
specified descriptor and are used.
usb_config_descriptor
usb_interface_descriptor
The change is to consolidate the definition of the descriptors
to usbdescriptors.h. The dublicates in usb.h are removed.
The extra element structure will have their name shorted by
removing the '_descriptor' suffix.
So
usb_config_descriptor -> usb_config
usb_interface_descriptor -> usb_interface
For these, the common descriptor elements are accessed now
by an element 'desc'.
As an example
- if (iface->bInterfaceClass != USB_CLASS_HUB)
+ if (iface->desc.bInterfaceClass != USB_CLASS_HUB)
This has been compile tested on MAKEALL arm, ppc and mips.
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
Commit c7190f02 (retain POR values of non-configured ACR, SPCR, SCCR,
and LCRR bitfields) moved the LCRR assignment to after relocation
to RAM because of the potential problem with changing the local bus
clock while executing from flash.
This change unfortunately adversely affects the boot time, as running
all code up to cpu_init_r can cause significant slowdown.
E.G. on a 8347 board a bootup time increase of ~600ms has been observed:
0.020 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
0.168 RS: 232
0.172 I2C: ready
0.176 DRAM: 64 MB
1.236 FLASH: 32 MB
Versus:
0.016 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
0.092 RS: 232
0.092 I2C: ready
0.096 DRAM: 64 MB
0.644 FLASH: 32 MB
So far no boards have needed the late LCRR setup, so simply revert it
for now - If it is needed at a later time, those boards can either do
their own final LCRR setup in board code (E.G. in board_early_init_r),
or we can introduce a CONFIG_SYS_LCRR_LATE config option to only do
the setup in cpu_init_r.
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
There is more and more usage of printing 64bit values,
so enable this feature generally, and delete the
CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
defines.
Signed-off-by: Heiko Schocher <hs@denx.de>
u-boot updates, before starting Linux, the memory node in the
DTS. As this is a "standard" feature, move this functionality
to the cpu.c file for mpc5xxx and mpc512x processors.
Signed-off-by: Heiko Schocher <hs@denx.de>
According to the PPC reference implementation the udelay() function is
responsible for resetting the watchdog timer as frequently as needed.
Most other architectures do not meet that requirement, so long-running
operations might result in a watchdog reset.
This patch adds a generic udelay() function which takes care of
resetting the watchdog before calling an architecture-specific
__udelay().
Signed-off-by: Ingo van Lil <inguin@gmx.de>
This patch adds support for A320 evaluation board from Faraday. This board
uses FA526 processor by default and has 512kB and 32MB NOR flash, 64M RAM.
FA526 is an ARMv4 processor and uses the ARM920T source in this patch.
Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
Defaults are for Infineon DDR timings.
Since none of the supported boards currently do
XIP boot, these seem to be faulty. fix the values
as per the calculations(ACTIMA,B), conf
the sdrc power with pwdnen and wakeupproc bits
Signed-off-by: Nishanth Menon <nm@ti.com>
Provides initial support for TI OMAP-L1x/DA8xx SoC devices.
See http://www.ti.com
Provides:
Low level initialisation.
System clock API.
Timer control.
Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
Remove volatiles and memory mapped structure accesses and replace with
readl and writel macro usage.
Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
This patch adds a unified s3c24x0 cpu header file that selects the header
file for the specific s3c24x0 cpu from the SOC and CPU configs defined in
board config file. This removes the current chain of s3c24-type #ifdef's
from the s3c24x0 code.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Fix stack_setup to place the stack on the correct address in DRAM
accroding to U-Boot standard and remove conditional compilation by
CONFIG_MEMORY_UPPER_CODE macro that is not necessry. This macro
was introduced and used only by this board for some unclear reason.
The definition of this macro is also removed because it's not
referenced elsewhere.
Signed-off-by: Seunghyeon Rhee <seunghyeon@lpmtec.com>
Tested-by: Minkyu Kang <mk7.kang@samsung.com>
