This adds the required GPIO and pinmux configuration to make eMMC / SD work
on Seaboard.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
This adds most of the clock functions required by board and driver code:
-query and adjust peripheral clocks
-query and adjust PLLs
-reset and enable control
These functions are plumbed in as required.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
Currently the mmc_change_freq and mmc_startup functions allocates
buffers on the stack that are passed down to the MMC device driver.
These buffers could be unaligned to the L1 dcache line size. This
causes problems when using DMA and with caches enabled.
This patch correctly cache alignes the buffers used for reading the
ext_csd data from an MMC device.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Currently the sd_change_freq function allocates two buffers on the
stack that it passes down to the MMC device driver. These buffers
could be unaligned to the L1 dcache line size. This causes problems
when using DMA and with caches enabled.
This patch correctly cache alignes the buffers used for reading the
scr register and switch status values from an MMC device.
Change-Id: Ifa8414f572ef907681bd2d5ff3950285a215357d
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Config VMMC voltage to 3V for MMC/SD card slot
and PBIAS settings needed for OMAP4
Fixes MMC/SD detection on boot from eMMC.
Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Enable high capacity to host capability.
Fixes eMMC detection on boot from MMC/SD card.
Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The mmc_send_status() function sets cmd.arg = 0. That's incorrect, so fix it.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Tested-by: Lei Wen <adrian.wenl@gmail.com>
Now that all platforms have been migrated to the new MMC driver, remove
the old one.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Currently if a DMA buffer straddles a buffer alignment boundary
(512KiB) then the DMA engine will pause and generate a DMA
interrupt. Since the DMA interrupt is not enabled it will hang
the MMC driver.
This patch adds support for restarting the DMA transfer. The
SYSTEM_ADDRESS register contains the next address that would have
been read/written when a boundary is hit. So we can read that
and write it back. The write triggers the resumption of the
transfer.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Tested-by : Jaehoon Chung <jh80.chung@samsung.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
This reverts commit c310fc8404.
The Atmel custodian had apparently rejected this patch's approach in
another thread, so this patch reverts it for now.
Signed-off-by: Andy Fleming <afleming@freescale.com>
If we don't want to build support for any partition types we can now
add #undef CONFIG_PARTITIONS in a board config file to keep this from
being compiled in. Otherwise boards assume this is compiled in by
default
Signed-off-by: Matthew McClintock <msm@freescale.com>
According to datasheet,set block count before multiple read/write.
Signed-off-by: elen.song <elen.song@atmel.com>
Acked-by: Andy Fleming <afleming@freescale.com>
This patch provides handling of the two way handshake when SEND_OP_COND
(CMD1) is send to mmc card. It is necessary to inform eMMC card if the
host can work with high capacity cards (Jedec JESD84-A441, point 7.4.3).
The extra flag MMC_MODE_HC (high capacity) is added to indicate if the
host is capable of handling the high capacity eMMC cards.
Since this change is added to the generic mmc framework, then it requires
other boards to indicate if their mmc controllers can handle high capacity
cards. As it is now - the old behaviour of the framework is preserved.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Some Renesas SuperH have MMCIF module. This driver supports it.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Fix the problem that if we use the chip of MMC version 4 and
the capacity is smaller than 2GB or equal, the mmc->capacity is
invalid. According to the JEDEC Standard, the value of ext_csd's
capacity is valid if the value is more than 2GB.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Andy Fleming <afleming@freescale.com>
This could support both armada100 and pantheon serial in the mainline,
while this driver also be tested to support upcoming mg, mmp2 and mmp3
hardware.
Signed-off-by: Lei Wen <leiwen@marvell.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Nowdays, there are plenty of mmc driver in uboot adopt the sd standard
host design, aka as sdhci. It is better to centralize the common logic
together to better maintenance.
Signed-off-by: Lei Wen <leiwen@marvell.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Erase is a very basic function since the begin of sd specification is
announced. Although we could write a bulk of full 0xff memory to the
range to take place of erase, it is more convenient and safe to
implement the erase function itself.
Signed-off-by: Lei Wen <leiwen@marvell.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
This patch added set_mmc_clk for external clock control.
c210 didn't support host clock control.
So We need external_clock_control function for c210.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Fix typo resulting in the compilation error
s5p_mmc.c: In function 's5p_mmc_initialize':
s5p_mmc.c:469: error: 'struct mmc' has no member named 'm_bmax'
introduced by commit "MMC: make b_max unconditional"
(8feafcc49c)
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
CC: John Rigby <john.rigby@linaro.org>
CC: Andy Fleming <afleming@freescale.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add missing header file to fix compilation warning
omap_hsmmc.c: In function 'omap_mmc_init':
omap_hsmmc.c:474: warning: implicit declaration of function 'get_cpu_family'
omap_hsmmc.c:474: warning: implicit declaration of function 'get_cpu_rev'
introduced by commit "MMC: omap_hsmmc.c: disable
multiblock rw on old rev omap34xx silicon"
(4ca9244d74)
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
CC: Andy Fleming <afleming@freescale.com>
CC: John Rigby <john.rigby@linaro.org>
For emmc, it may have up to 7 partitions: two boot partitions, one
user partition, one RPMB partition and four general purpose partitions.
(Refer to JESD84-A44.pdf/page 154)
As bootloader may need to read out or reflashing images on those
different partitions, it is better to enable the partition switch with
console command support.
Also for partition would be restore to user partition(part 0) when CMD0
is used, so change mmc_init routine to perform normal initialization
only once for each slot, unless use the rescan command to force init
again.
Signed-off-by: Lei Wen <leiwen@marvell.com>
Acked-by: Andy Fleming <afleming@freescale.com>
A "send status" command is added with the commit "mmc: checking
status after commands with R1b response". But the status register
returned from send status command of SPI protocol is different from
that of MMC/SD protocol. We do a simple test and generate a response
in stead of full bit-by-bit translation.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
For freescale i.MX53 eSDHCv2, when using CMD12, cmdtype need
to be set to ABORT, otherwise, next read command will hang.
This is a software Software Restrictions in i.MX53 reference manual:
29.7.8 Multi-block Read
For pre-defined multi-block read operation, that is,the number of blocks
to read has been defined by previous CMD23 for MMC, or pre-defined number
of blocks in CMD53 for SDIO/SDCombo,or whatever multi-block read without
abort command at card side, an abort command, either automatic or manual
CMD12/CMD52, is still required by ESDHC after the pre-defined number of
blocks are done, to drive the internal state machine to idle mode. In this
case, the card may not respond to this extra abort command and ESDHC will
get Response Timeout. It is recommended to manually send an abort command
with RSPTYP[1:0] both bits cleared.
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Make existing field b_max field in struct mmc unconditional
and use it instead of CONFIG_SYS_MMC_MAX_BLK_COUNT in mmc_bread
and mmc_bwrite.
Initialize b_max to CONFIG_SYS_MMC_MAX_BLK_COUNT in mmc_register
if it has not been initialized by the hw driver.
Initialize b_max to 0 in all callers to mmc_register.
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Add support for the ARM PrimeCell MultiMedia Interface - PL180.
Ported from original device driver written by ST-Ericsson.
Signed-off-by: Matt Waddel <matt.waddel@linaro.org>
Hi Terry,
> So I guess:
> mmc_init calls mmc_send_op_cond that set high_capacity,
> than it calls mmc_startup, that, with MMC_CMD_SEND_CSD command, set
> the capacity, using values in CSD register.
> So I guess that mmc_change_freq should not recalculate high_capacity.
>
> It seems better, isn't it?
>
> Regards,
> Raffaele
>
Finally I think that it is enough to apply the following patch in order
to fix the issue.
Regards,
Raffaele
Signed-off-by: Andy Fleming <afleming@freescale.com>
Defining CONFIG_MMC_TRACE in the include board file it is possible to activate
a tracing support.
This code helps in case of eMMC hw failure or to investigate possible eMMC
initialization issues.
Signed-off-by: Raffaele Recalcati <raffaele.recalcati@bticino.it>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The first SEND_OP_COND (CMD1) command added is used to ask card capabilities.
After it an AND operation is done between card capabilities and host
capabilities (at the moment only for the voltage field).
Finally the correct value is sent to the MMC, waiting that the card
exits from busy state.
Signed-off-by: Raffaele Recalcati <raffaele.recalcati@bticino.it>
Signed-off-by: Andy Fleming <afleming@freescale.com>
It is recommended to check card status after these kind of commands.
This is done using CMD13 (SEND_STATUS) JEDEC command until
the card is ready.
In case of error the card status field is displayed.
Signed-off-by: Raffaele Recalcati <raffaele.recalcati@bticino.it>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This patch supports mmc/sd card with spi interface. It is based on
the generic mmc framework. It works with SDHC and supports multi
blocks read/write.
The crc checksum on data packet is enabled with the def,
There is a subcomamnd "mmc_spi" to setup spi bus and cs at run time.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Andy Fleming <afleming@freescale.com>
These local vars need not be writable nor exported.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
As DATA_ERROR includes the value IRQSTAT_DTOE, a timeout error
would yield the first error return instead of TIMEOUT.
By swapping the test TIMEOUTs are reported as such
An alternate solution would be to remove the IRQSTAT_DTOE from the DATA_ERROR define
but as that one might be less desired I've opted for the simplest solution
Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The maximum blocks value was hardcoded to 65535 due to a 16 bit
register length. The value can change for different platforms.
This patch makes the default the current value of 65535, but it
is configurable for other platforms.
Signed-off-by: Matt Waddel <matt.waddel@linaro.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark
level register description has been changed:
9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00
25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Don't forget to count full data size for the multiblock operation request.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The timer register is 32bits, not 16bit, so 0xFFFF won't fill it.
Write out -1 to make sure to fill the whole thing.
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Blocksize was hardcoded to 512 bytes. But the blocksize varies
depeding on various mmc subsystem commands (between 8 and 512).
This hardcoding was resulting in interrupt error during data
transfer.
It is now calculated based upon the request sent by mmc subsystem.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
- Timeout counter value is set as DTOCV bits in SYSCTL register
For counter value set as timeout,
Timeout period = (2^(timeout + 13)) SD Clock cycles
- As per 4.6.2.2 section of SD Card specification v2.00, host should
cofigure timeout period value to minimum 0.25 sec.
- Number of SD Clock cycles for 0.25sec should be minimum
(SD Clock/sec * 0.25 sec) SD Clock cycles
= (mmc->tran_speed * 1/4) SD Clock cycles
- Calculating timeout based on
(2^(timeout + 13)) >= mmc->tran_speed * 1/4
Taking log2 both the sides and rounding up to next power of 2
=> timeout + 13 = log2(mmc->tran_speed/4) + 1
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Acked-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Data timeout counter (SYSCTL[DTOCV]) is not reliable for values of 4, 8,
and 12. Program one more than the desired value: 4 -> 5, 8 -> 9, 12 -> 13.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Added support for MMC/SD cards for Davinci. This feature is enabled by
CONFIG_DAVINCI_MMC and is dependant on CONFIG_MMC and CONFIG_GENERIC_MMC
options. This is tested on DM355 and DM365 EVMs with both the available mmc
controllers.
Signed-off-by: Alagu Sankar <alagusankar@embwise.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The default value of the SRS, VS18 and VS30 and ADMAS fields in the host
controller capabilities register (HOSTCAPBLT) are incorrect. The default
of these bits should be zero instead of one.
Clear these bits out when we read HOSTCAPBLT.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Do not issue a manual asynchronous CMD12. Instead, use a (software)
synchronous CMD12 or AUTOCMD12 to abort data transfer.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Some new platform's esdhc pins don't share with other function.
The eSDHC shouldn't be disabled, even if "esdhc" isn't defined
in hwconfig env variable.
Use CONFIG_FSL_ESDHC_PIN_MUX to fix this problem.
Signed-off-by: Chenhui Zhao <b26998@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The current code use all the voltage range support by the host
controller to do the validation. This will cause problem when
the host supports Low Voltage Range. Change the validation
voltage to be based on board setup.
Signed-off-by: Li Yang <leoli@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The max clock of MMC is 52MHz
Signed-off-by: Jerry Huang <Changm-Ming.Huang@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
After booting the u-boot, and first using some SD card (such as Sandisk 2G SD
card), because the field 'clock' of struct mmc is zero, this will cause
the read transfer is always active and SDHC DATA line is always active,
therefore, driver can't handle the next command.
Therefore, we use mmc_set_clock to setup both the data structure and HW
to the initial clock speed of 400000Hz.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
eSDHC host controller reset results in clearing of snoop bit also.
This patch sets the SNOOP bit after the completion of host controller reset.
Without this patch mmc reads are not consistent.
Signed-off-by: P.V.Suresh <pala@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Having a loop with a counter is no timing guarentee for timing
accuracy or compiler optimizations. For e.g. the same loop counter
which runs when the MPU is running at 600MHz will timeout in around
half the time when running at 1GHz. or the example where GCC 4.5
compiles with different optimization compared to GCC 4.4. use timer
to keep track of time elapse and we use an emperical number - 1sec
for a worst case timeout. This should never happen, and is adequate
imaginary condition for us to fail with timeout.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Before this commit, weak symbols were not overridden by non-weak symbols
found in archive libraries when linking with recent versions of
binutils. As stated in the System V ABI, "the link editor does not
extract archive members to resolve undefined weak symbols".
This commit changes all Makefiles to use partial linking (ld -r) instead
of creating library archives, which forces all symbols to participate in
linking, allowing non-weak symbols to override weak symbols as intended.
This approach is also used by Linux, from which the gmake function
cmd_link_o_target (defined in config.mk and used in all Makefiles) is
inspired.
The name of each former library archive is preserved except for
extensions which change from ".a" to ".o". This commit updates
references accordingly where needed, in particular in some linker
scripts.
This commit reveals board configurations that exclude some features but
include source files that depend these disabled features in the build,
resulting in undefined symbols. Known such cases include:
- disabling CMD_NET but not CMD_NFS;
- enabling CONFIG_OF_LIBFDT but not CONFIG_QE.
Signed-off-by: Sebastien Carlier <sebastien.carlier@gmail.com>
This patch adds multi-block read support for the generic MMC
driver. Large reads are broken into chunks of 65535 blocks to
ensure that the code works with controllers having a 16 bit block counter.
This patch results in a significant performance improvement.
Time to read a 45 MB file went from 36 seconds to 9 seconds on Overo
Signed-off-by: Steve Sakoman <steve.sakoman@linaro.org>
Tested-by: Steve Sakoman <steve.sakoman@linaro.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The current mmc write implementation is type ulong, but returns int values.
Some of the printf's are terminated with /n/r, one has none.
This patch fixes these issues and also removes some unnecessary local
variables.
Signed-off-by: Steve Sakoman <steve.sakoman@linaro.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Constraint the mmc framework to only send no more than 65535
blocks in one go during the multi-write command. This constraint
comes due to the limitation of 16bit width block counter register
at some hardware.
Signed-off-by: Lei Wen <leiwen@marvell.com>
Cc: Reinhard Meyer <u-boot@emk-elektronik.de>
This Patch do support 8-bit bus width for s5p
So we add parameter for bus_width (in s5p_mmc_init(), s5p_mmc_initialize())
If want to use 8-bit bus width, only change (0, 8) instead of (0, 4).
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
OMAP boards currently use a legacy mmc driver. This patch adds a new
mmc driver which will work with the generic mmc driver in u-boot.
This new driver will work with both OMAP3 and OMAP4 boards.
This patch does not remove the old driver. It should remain in the
tree until all boards that use it switch to the new driver.
Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com>
Tested-by: Steve Sakoman <steve@sakoman.com>
The current mmc driver returns erroneous capacity information for
eMMC. The capacity of eMMC devices is available only in the ext-CSD
register. This patch add code to read the ext-CDSD register and
correctly calculate eMMC capacity.
Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com>
Acked-by: Steve Sakoman <steve@sakoman.com>
Simplify the command setup and status checking steps, and add a proper
timeout to the status polling code to avoid possible infinite hangs.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Commit d2bf29e3 caused a number of compiler warnings:
mmc.c: In function 'mmc_bwrite':
mmc.c:97: warning: format '%x' expects type 'unsigned int', but argument 2 has type 'long unsigned int'
mmc.c:97: warning: format '%x' expects type 'unsigned int', but argument 3 has type 'lbaint_t'
mmc.c: In function 'mmc_bread':
mmc.c:229: warning: format '%x' expects type 'unsigned int', but argument 2 has type 'long unsigned int'
mmc.c:229: warning: format '%x' expects type 'unsigned int', but argument 3 has type 'lbaint_t'
Fix these.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Lei Wen <leiwen@marvell.com>
This patch is intended to prepare the other S5P SoC. (s5pc210)
If use SoC specific defines then can't share with other SoC.
So, make the accessor functions for access the base address by common way.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
The OMAP3 block read function is not following API and always returning
1 instead of read block count, fix it. Also to simplify code, merge it
with with a helper function, which was only called from the block read
function.
After this patch ext2 filesystem can be used properly.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Tested-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Make driver local variables and functions static and
remove them from the arch header.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Tested-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch adds support mmc driver for s5p SoC
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
this eliminates compiler warnings when cmd_mmc.c is built with CONFIG_SYS_MMC_SET_DEV
the mmc_set_dev implementation in omap3_mmc.c is also tweaked to match
the new prototype in parameter naming and type
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The architecture independent header is moved to drivers/mmc, and the architecture
dependent headers reside in asm/arch-omap3 and asm/arch-omap4
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch adds support for the second and third mmc channels on OMAP3
processors
Boards wishing to use this feature should define CONFIG_SYS_MMC_SET_DEV
in the board config
Tested on Overo
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Tested-by: Philip Balister <philip@opensdr.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch enables PXAMCI support on PXA3xx CPUs. This patch only enables MMC1
though, MMC2 and PXA31x MMC3 will need further patch to be operational.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
In case the delays were set to 10000, the MMC card on PXA27X boards (and PXA3xx
boards) didn't initialize on first try. Increasing the delays and leaving just
those for PXA25x and 26x (that is 200000) fixes this problem.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Commit 77c1458d caused the following compiler warnings:
fsl_esdhc.c: In function 'esdhc_pio_read_write':
fsl_esdhc.c:142: warning: assignment discards qualifiers from pointer target type
fsl_esdhc.c: In function 'esdhc_setup_data':
fsl_esdhc.c:169: warning: unused variable 'wml_value'
fsl_esdhc.c: In function 'esdhc_pio_read_write':
fsl_esdhc.c:164: warning: control reaches end of non-void function
Fix these.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Dipen Dudhat <dipen.dudhat@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
On some Freescale SoC Internal DMA of eSDHC controller has bug.
So PIO Mode has been introduced to do data transfer using CPU.
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
When we set the read or write watermark in WML we should maintain the
rest of the register as is, rather than using some hard coded value.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
To support multiple block read command we must set abort or use auto
CMD12. If we booted from eSDHC controller neither of these are used
and thus we need to reset the controller to allow multiple block read
to function.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We need to stop the clocks on 83xx/85xx as well as imx. No need to make
this code conditional to just imx.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Stefano Babic <sbabic@denx.de>
Some registers of the mxcmmc driver were accessed using
16 bit accessor functions, because only the LSB is
significant. This is not needed and generates
warnings.
Signed-off-by: Stefano Babic <sbabic@denx.de>
There is be a path through mmc_read in drivers/mmc/mmc.c where
malloc'd memory is not freed before exiting mmc_read: it occurs if
mmc_set_blocklen() returns a non-zero value.
Reported-by: Quentin Armitage <Quentin@Armitage.org.uk>
Signed-off-by: Wolfgang Denk <wd@denx.de>
