The PDK2 board is capable of running both 100M and 1G ethernet. However,
the i.MX6 has only one ethernet MAC, so it is possible to configure
either 100M or 1G Ethernet. In case of 100M option, the PHY is on the
SoM and the signals are routed to a RJ45 port. For 1G the PHY is on
the PDK2 board with another RJ45 port. 100M and 1G ethernet use
different signal pins from the i.MX6, but share the MDIO bus.
This SoM board combination is used to demonstrate how to enable 1G
ethernet configuration.
Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Cc: Stefano Babic <sbabic@denx.de>
If `sb_load_cmdfile()` fails to open the configuration file it will jump
to error handling where the code will try to `fclose()` the FILE pointer
which is NULL causing `mkimage` to segfault.
This patch removes the label for error handling and instead returns
immediately which skips the `fclose()` and prevents the segfault. The
errno is also described in the error message to guide users.
Signed-off-by: Mattias Hansson <hansson.mattias@gmail.com>
Reviewed-by: Wolfgang Denk <wd@denx.de>
The FXL6408 GPIO expander manages critical devices,
including on-module USB hub. Configure the expander to
switch the USB hub into bypass mode, allowing to use
on-carrier-board USB hub.
Signed-off-by: Oleksandr Suvorov <cryosay@gmail.com>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Initial support for Fairchild's 8 bit I2C gpio expander FXL6408.
The CONFIG_FXL6408_GPIO define enables support for such devices.
Based on: https://patchwork.kernel.org/patch/9148419/
Signed-off-by: Oleksandr Suvorov <cryosay@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Previously these two options are called CONFIG_SPL_MMC_SUPPORT
and CONFIG_SPL_SERIAL_SUPPORT. During the transition they are
removed by accident. Thus adding them back.
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: uboot-imx <uboot-imx@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Extension boards can be added to Compulab's iot-gate-imx8mm.
We implement extension board manager for detecting the extension
boards.
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: uboot-imx <uboot-imx@nxp.com>
After acking the requested frequency, should wait the ack bit clear
by DDR controller and check the DFS interrupt for next request polling.
Otherwise, the next polling of request bit will get previous value
that DDR controller have not cleared it, so a wrong request frequency
is used.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
On i.MX8ULP, The dram config timing need to be saved into sram for
ddr retention when APD enter PD mode, so add this support on i.MX8ULP.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Obatin the SoC current temperature in print_cpuinfo().
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The DDRLOCKED bit in CGC2 DDRCLK will auto lock up and down by HW
according to DDR DIV updating or DDR CLK halt status change. So DDR
PCC disable/enable will trigger the lock up/down flow. We
need wait until unlock to ensure clock is ready.
And before configuring the DDRCLK DIV, we need polling the DDRLOCKED
until it is unlocked. Otherwise writing ti DIV bits will not set.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This patch implements enable_adc1_clk() to enable or disable the ADC1
clock on i.MX8ULP.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Get the MAC address from fuse bank5 word 3 and 4. It has
MSB first at lowest address, so have a reverse order with other
iMX used in mac.c
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
When LPAV is allocated to RTD, the LPAV won't be reset. So we have to
reset DCNano and MIPI DSI in u-boot before enabling the drivers
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The LPAV is not allocated to APD when dual boot, so LPAV won't
reset when APD is reset. We have to explicitly reset the DDR,
otherwise its initialization will fail.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
8ULP ROM should read the LPOSC trim BIAS fuse to fill the CGC0
LPOSCCTRL[7:0], but it writes a fixed value on A0.1 revision.
A0.2 will fix the issue in ROM. But A0.1 we have to workaround
it in SPL by setting LPOSCCTRL BIASCURRENT again.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Remove the freescale vendor name from CPU revision print to align
with other i.MX platforms
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The setting does not have effect because we should set it after
power on the PS16 for NIC AV.
So move it after upower_init which has powered on all PS
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
To avoid DCNANO underrun issue on high loading test, set its
read Qos on NIC_LPAV to highest
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The board use IO9 of PCA6416 on LPI2C0 and TPM0 for MIPI DSI MUX and
backlight. However the LPI2C0 and TPM0 are M33 resources, in this
patch we simply access them, but this is a temporary solution.
We will modify it when M33 FW changes to set MIPI DSI panel as default
path and enable backlight after reset.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add the DSI clock enable and disable with PCC reset used.
Add the LCD pixel clock calculation and configuration for DCNano
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Assign the PXP/HIFI4/EPDC to APD domain, otherwise APD not
able to receive interrupts from the modules.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
When single boot, assign AP domain as the master domain of the LPAV.
Allocates LPAV master and slave resources like GPU, DCNano, MIPI-DSI
eDMA channel and eDMA request to APD
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
S400 enables RDC only when the DBD_EN is fused. Otherwise, the RDC
is allowed by all masters.
Current S400 has issue if the XRDC has released to A35, then A35 reset
will fail in ROM due to S400 fails to get XRDC.
So temp work around is checking the DBD_EN, if it is not fused, we
don't need to call release XRDC or TRDC.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change boot device logic to also allow environment stored in fat and in
ext4 when booting from SD or from eMMC.
As the boot device check for SD and for eMMC was depending on
ENV_IS_IN_MMC being defined, change the ifdef blocks at env_get_location
to use IS_ENABLED instead for all modes, returning NOWHERE when no valid
mode is found.
Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Correct printf format for unsigned long long is %llx and not %llxx.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
The imx28 uses following voltage supplies hierarchy:
VDD_5V (VDD_BAT) -> VDDIO -> VDDA -> VDDMEM
\-----> VDDD
One shall first enable DCDC on the parent source (VDDIO) and then
follow with its children.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Add EA iMX7ULP COM board support for building SPL.
Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Force selecting features present in SoC i.MX7ULP.
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Return the root clock values for MXC_CSPI_CLK, MXC_I2C_CLK,
MXC_UART_CLK and MXC_QSPI_CLK.
At least for the I2C clock the missing support leads to a wrong
configured I2C frequency. The expected value is 100kHz but the resulting
value is about 1MHz.
Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Use the complete 512kb (4 blocks) nand partition reserved for u-boot
environment instead of just the first block, this allows the module
to have a working environment even if 3 blocks are bad.
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
This is the promised second part of the sunxi PR for 2022.04, albeit
technially outside of the merge window. We were working on this full
steam since the beginning of the year, and it deserves to be merged,
I think.
The main attraction is support for the F1C100s SoC, which sports a
venerable ARM926 core. Support for this SoC and the LicheePi Nano board
has been in Linux for years, and U-Boot patches were posted mid last
year already.
The new SoC using ARMv5 also means that the bulk of the new code should
not touch any existing boards, although we did some refactorings first,
of course, which actually cleans up some existing sunxi code.
Compile tested for all 160 sunxi boards, and briefly tested on BananaPi M1,
OrangePi Zero, Pine64 and Pine-H64. Tested by others on their boards,
including F1C100s and F1C200s devices.
The Lichee Pi Nano is a board based on the F1C100s.
Add defconfigs for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Add device tree files for suniv and
Lichee Pi Nano it is a board based on F1C100s.
dt-bindings/dts are synced with 5.16.0
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Add support for the suniv architecture, which is newer ARM9 SoCs by
Allwinner. The design of it seems to be a mixture of sun3i, sun4i and
sun6i.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Adds support for SUNIV and the F1C100s.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Generic Timer Extension is not available on SUNIV.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Add support for F1C100s internal dram controller.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This patch aims to add header files for the suniv.
The header files included add support for uart, and clocks.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Some Allwinner SoCs use ARM926EJ-S core.
Add Allwinner/sunXi specific code to ARM926EJ-S CPU dircetory.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Both armv7 and arm926ejs use this timer code so move it to mach-sunxi.
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The ARMv7 start code has support for saving some boot params at the
entry point, which is used by some SoCs to return to BROM.
Port this to ARM926EJ-S start code.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Remove some pointless #ifdefs from this file, as there are quite too
many of them already.
Some definitions don't really hurt to have in any case, so remove the
pointless CONFIG_MMC guard around CONFIG_MMC_SUNXI_SLOT.
The BOARD_SIZE_LIMIT applies regardless of ARM64 or not (now), so remove
that guard as well. The maximum number of MMC devices does not depend on
CONFIG_ENV_IS_IN_MMC, so move that out to simplify the file.
Last but not least CONFIG_SPL_BOARD_LOAD_IMAGE serves no real purpose
anymore: it's unconditionally defined for all sunxi boards, and protects
nothing applicable outside of sunxi code anymore. Just remove it.
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
When we added Allwinner SoC support to ARMv8, we needed to pull in an
implementation of lowlevel_init() calling the C function s_init(), as
sunxi required it as this time.
The last few patches got rid of this bogus requirement, and as sunxi was
still the only user, we can now remove this lowlevel_init.S from ARMv8
altogether.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Currently we do some magic "SRAM setup" MMIO writes in s_init(), copied
from the original BSP U-Boot. The comment speaks of this being required
before DRAM access gets enabled, but there is no indication that this
would actually be required that early.
Move this out of s_init(), into board_init_f(). Since this actually only
affects a very few older SoCs, the actual code goes into the cpu/armv7
directory, to move it out of the way for all other SoCs.
This also uses the opportunity to convert some #ifdefs over to the fancy
IS_ENABLED() macros used in actual C code.
We keep the s_init() stub around for now, since armv8's lowlevel_init
still relies on it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
