Commit graph

68149 commits

Author SHA1 Message Date
Simon Glass
c9cc37de2c x86: apl: Support writing the IntelGraphicsMem table
This table is needed by the Linux graphics driver to handle graphics
correctly. Write it to ACPI.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:15 +08:00
Simon Glass
e4f09f97c9 x86: Add wake sources for the acpi_gpe driver
Some devices can wake the system from sleep, e.g opening the lid on a
clamshell or moving a USB mouse.

Add a wake to specify this for USB devices and add the settings for Apollo
Lake.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:15 +08:00
Simon Glass
fd42f263ce i2c: Add a generic driver to generate ACPI info
Many I2C devices produce roughly the same ACPI data with just things like
the GPIO/interrupt information being different.

This can be handled by a generic driver along with some information in the
device tree.

Add a generic i2c driver for this purpose.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-09-25 11:27:15 +08:00
Simon Glass
bddbaf5edf x86: link: Allow more space for U-Boot
The extra ACPI code increases U-Boot above it current size limit. Move
the start earlier to provide space.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:14 +08:00
Simon Glass
23dd0ea4c7 dm: acpi: Use correct GPIO polarity type in acpi_dp_add_gpio()
This function currently accepts the IRQ-polarity type. Fix it to use the
GPIO type instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:14 +08:00
Simon Glass
88490e1979 acpi: Support generating a multi-function _DSM for devices
Add a function to generate ACPI code for a _DSM method for a device.
This includes functions for starting and ending each part of the _DSM.

Signed-off-by: Simon Glass <sjg@chromium.org>
[bmeng: fix the "new blank line at EOF" git warning]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:14 +08:00
Simon Glass
da7cff338f acpi: Add support for conditions and return values
Add functions to support generating ACPI code for condition checks and
return values.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:14 +08:00
Simon Glass
e0a896b88f acpi: Add support for writing a _PRW
A 'Power Resource for Wake' list the resources a device depends on for
wake. Add a function to generate this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:13 +08:00
Simon Glass
99e555a79a x86: coral: Add ACPI tables for coral
This device has a large set of ACPI tables. Bring these in from coreboot
so that full functionality is available (apart from SMI).

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:13 +08:00
Simon Glass
7924b499a2 x86: acpi: Expand the GNVS
Expand this to 4KB so that it is possible to add custom information to it.
On Chromebooks this is used to pass verified-boot information.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:13 +08:00
Simon Glass
55109f1d4e x86: acpi: Support external GNVS tables
At present U-Boot puts a magic number in the ASL for the GNVS table and
searches for it later.

Add a Kconfig option to use a different approach, where the ASL files
declare the table as an external symbol. U-Boot can then put it wherever
it likes, without any magic numbers or searching.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:13 +08:00
Simon Glass
167c3f6e93 x86: Add a common global NVS structure
Add the definition of this structure common to Intel devices. It includes
some optional Chrome OS pieces which are used when vboot is integrated.

Drop the APL version as it is basically the same.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:12 +08:00
Simon Glass
97bafc9df9 x86: Add a config for the systemagent PCIEX regions size
Add a way to specify the required size for this region. This is used when
generating ACPI tables.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:12 +08:00
Simon Glass
4c44aa7aab x86: apl: Correct PCIE_ECAM_BASE
This value is incorrect and causes problems booting Linux. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:12 +08:00
Simon Glass
13539ba705 x86: acpi: Add DPTF asl files
Add common DPTF (Intel Dynamic Performance and Thermal Framework) files,
taken from coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:12 +08:00
Simon Glass
14f643d1a2 x86: acpi: apl: Add asl files for Apollo Lake
Add Apollo Lake ASL files, taken from coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:11 +08:00
Simon Glass
d9434a17e5 x86: acpi: Add base asl files for common x86 devices
Add common x86 ASL files, taken from coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-09-25 11:27:11 +08:00
Simon Glass
4d0c5762ad x86: acpi: Add cros_ec tables
Add ASL files for the Chrome OS EC, taken from coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:11 +08:00
Simon Glass
d9778ff0d3 cros: Add information about booting Chrome OS on x86
Recent versions of Chrome OS do not have a kernel in the root disk, to
save space.

With the improvements to the 'zboot' command it is fairly easy to load
the kernel from the raw partition. Add instructions on how to do this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:11 +08:00
Simon Glass
dc8e7a91f4 cros: Update chromium documentation
A few things have changed since this was written about 18 months ago.
Update the README.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:10 +08:00
Simon Glass
4f96023afd x86: zboot: Allow overriding the command line
When booting Chrome OS images the command line is stored separately
from the kernel. Add a way to specify this address so that images boot
correctly.

Also add comments to the zimage.h header.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: adjust maxargs to 8 for 'zboot start']
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:10 +08:00
Simon Glass
631c2b9fc4 x86: zboot: Add an option to dump the setup information
There is a lot of information in the setup block and it is quite hard to
decode manually. Add a 'zboot dump' command to decode it into a
human-readable format.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:10 +08:00
Simon Glass
f82cd7b725 x86: zboot: Allow setting a separate setup base address
At present the setup block is always obtained from the image
automatically. In some cases it can be useful to use a setup block
obtained elsewhere, e.g. if the image has already been unpacked. Add an
argument to support this and update the logic to use it if provided.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: adjust maxargs to 7 for 'zboot start']
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:10 +08:00
Simon Glass
126f47c3b8 x86: zboot: Set environment variables for image locations
At present it is not possible to tell from a script where the setup block
is, or where the image was loaded to. Add environment variables for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:09 +08:00
Simon Glass
3e59759324 x86: zboot: Add an 'setup' subcommand
Add a subcommand that sets up the kernel ready for execution.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:09 +08:00
Simon Glass
1d9e4bb755 x86: zboot: Add an 'load' subcommand
Add a subcommand that loads the kernel into the right places in memory.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: adjust ZBOOT_STATE_INFO value to match the command order]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:09 +08:00
Simon Glass
6f873f5fc6 x86: zboot: Add an 'info' subcommand
Add a little subcommand that prints out where the kernel was loaded and
its setup pointer. Run it by default in the normal boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:09 +08:00
Simon Glass
88f1cd6c2a x86: zboot: Add a 'go' subcommand
Split out the code that actually boots linux into a separate sub-command.
Add base_ptr to the state to support this.

Show an error if the boot fails, since this should not happen.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:08 +08:00
Simon Glass
5588e776b0 x86: zboot: Set up a sub-command structure
Add subcommands to zboot. At present there is only one called 'start'
which does the whole boot. It is the default command so is optional.

Change the 's' string variable to const while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: reduce maxargs to 6 of 'zboot start' subcommand]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:08 +08:00
Simon Glass
e9d31b302d x86: zimage: Disable interrupts just before booting
At present if an error occurs while setting up the boot, interrupts are
left disabled. Move this call later in the sequence to avoid this problem.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:08 +08:00
Simon Glass
00630f63cc x86: zboot: Correct image type
At present U-Boot sets a loader type of 8 which means LILO version 8,
according to the spec. Update it to 0x80, which means U-Boot with no
particular version.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:08 +08:00
Simon Glass
c038f3be3b x86: zboot: Move kernel-version code into a function
To help reduce the size and complexity of load_zimage(), move the code
that reads the kernel version into a separate function. Update
get_boot_protocol() to allow printing the 'Magic signature' message only
once, under control of its callers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:07 +08:00
Simon Glass
30b372d419 x86: zimage: Avoid using #ifdef
Use IS_ENABLED() instead of #ifdef in this file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:07 +08:00
Simon Glass
e814837488 x86: zimage: Use a state struct to hold the state
At present the 'zboot' command does everything in one go. It would be
better if it supported sub-commands like bootm, so it is possible to
examine what will be booted before actually booting it.

In preparation for this, move the 'state' of the command into a struct.
This will allow it to be shared among multiple functions in this file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:07 +08:00
Simon Glass
6e04cb76db x86: Update the bootparam header
This header is missing a few of the newer features from the specification.
Add these as well as a link to the spec. Also use the BIT() macros where
appropriate.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:06 +08:00
Tom Rini
e119de72e3 Merge branch 'mpc85xx-for-v2021.01' into next
- Add DM_SPI, DM_SPI_FLASH support for powerpc platforms
- Add DM_ETH support on P1010RDB, P1020RDB, P2020RDB
- Remove some un-maintained powerpc platforms
- Add USB_STORAGE support in config
2020-09-24 08:30:25 -04:00
Ran Wang
893cdf0b7f configs: powerpc: add usb (host) mass storage support
commit 0cfccb5401 ("configs: Resync with savedefconfig")
removed CONFIG_USB_STORAGE from some powerpc platforms' defconfig
files, whicih would block the use case of system loading rootfs
from USB drives, add them back.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Priyanka Jain
cddffcaf4a configs: Remove P5040DS secure boot configs
Remove NXP powerpc P5040DS secure boot configs as they are
no longer maintained.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Priyanka Jain
8e01439dd3 board/freescale: Remove P5020DS board support
Remove NXP powerpc P5020DS board support as it is no
longer maintained.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Priyanka Jain
d975f6a693 powerpc:Remove P4080DS secure boot configs
Remove NXP powerpc P4080DS secure boot configs as they are
no longer maintained.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Priyanka Jain
c2dee50ec0 configs: Remove P3041DS secure boot configs
Remove NXP powerpc P3041DS secure boot configs as they are
no longer maintained.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Priyanka Jain
63310debc9 board/freescale: Remove P1024RDB board support
Remove NXP powerpc P1024RDB board support as it is no
longer maintained.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Priyanka Jain
6d1dd76afe board/freescale: Remove P1021RDB board support
Remove NXP powerpc P1021RDB board support as it is no
longer maintained.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Priyanka Jain
53e3096cd0 board/freescale: Remove P1020MBG board support
Remove NXP powerpc P1020MBG board support as it is no
longer maintained.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Priyanka Jain
da3dd417d7 board/freescale: Remove P1020UTM board support
Remove NXP powerpc P1020UTM board support as it is no
longer maintained.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Priyanka Jain
d521cece5a board/freescale: Remove P1025RDB board support
Remove NXP powerpc P1025RDB board support as it is no
longer maintained.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Priyanka Jain
fd7331ed0d configs: Remove P1010RDB secure boot configs
Remove NXP powerpc P1010RDB secure boot configs as they are
no longer maintained.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Priyanka Jain
20b1ae018f board/freescale: Remove p1023rdb board support
Remove NXP powerpc p1023rdb board support as it is no
longer maintained.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Hou Zhiqiang
6c9e68e860 configs: P2020RDB: Enable DM_ETH config
Enable the DM_ETH and DM_MDIO config.

On P2020RDB, the eTSEC1 is connecting with a switch VSC7385,
so also enable the fixed PHY support.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00
Hou Zhiqiang
613e49bb91 dts: powerpc: p2020rdb: Add eTSEC DT nodes
P2020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
    eTSEC1: Connected to RGMII switch VSC7385
    eTSEC2: Connected to SGMII PHY VSC8221
    eTSEC3: Connected to SGMII PHY AR8021

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 08:27:44 -04:00