Commit graph

27486 commits

Author SHA1 Message Date
Lokesh Vutla
1fb68b842e ARM: AM43xx: Update Current Booting devices list
Current Booting devices list is different from that of AM33xx.
Updating the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:01 -05:00
Lokesh Vutla
0d54cb924e ARM: AM43xx: Select clk source for Timer2
Selecting the Master osc clk as Timer2 clock source.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:01 -05:00
Sekhar Nori
f4af163e6c ARM: AM43XX: Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support
CONFIG_ENV_VARS_UBOOT_CONFIG, CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and
CONFIG_BOARD_LATE_INIT is already set. Adding support to detect the
board. These variables are used by findfdt.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:00 -05:00
Sekhar Nori
9f1a8cd33f ARM: AM43XX: board: add support for reading onboard EEPROM
Add support for reading onboard EEPROM to enable
board detection.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:00 -05:00
Lokesh Vutla
1564dba7d9 ARM: AM43xx: Add extra ENV settings
Add Extra env settings.
This is derived from am335x Extra ENV settings.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:00 -05:00
Lokesh Vutla
573b020ecb ARM: AM43xx: Add L2 Support
AM4372 uses PL310 L2 Cache. Enable the configs for the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:00 -05:00
Lokesh Vutla
369cbe1e1e ARM: AM43xx: Adapt to ti_armv7_common.h config file
Use ti_armv7_common.h config file to inclde the common
configs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:00 -05:00
Lokesh Vutla
7ca1b2a210 ARM: AM43xx: Update the base addresses of modules
PRCM, timer base addresses and offsets are different from
AM33xx. Updating the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:13:59 -05:00
Stefan Roese
ce23b18bbb arm: omap3: Fix beagleboard SPL boot hangup (GPIO clocks not enabled)
Patch f33b9bd3
[arm: omap3: Enable clocks for peripherals only if they are used]
breaks SPL booting on Beagleboard. Since some gpio input's are
read to detect the board revision. But with this patch above, the
clocks to the GPIO subsystems are not enabled per default any more.
The GPIO banks need to be configured specifically now.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
2013-12-18 21:13:59 -05:00
Tom Rini
ef184040b7 Merge branch 'master' of git://git.denx.de/u-boot-nand-flash 2013-12-18 18:45:39 -05:00
Albert ARIBAUD
d627eefcd5 Merge remote-tracking branch 'u-boot-pxa/master' into 'u-boot-arm/master' 2013-12-18 22:19:02 +01:00
Albert ARIBAUD
fe7f0810dd Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master' 2013-12-18 21:45:34 +01:00
Tom Rini
2d65256bb0 Merge branch 'master' of git://git.denx.de/u-boot-usb 2013-12-18 15:06:43 -05:00
Marek Vasut
f90aea2a65 ARM: pxa: Fix CONFIG_SYS_HZ on PXA
The PXA incorrectly uses CONFIG_SYS_HZ, which should be 1000 across
U-Boot. Fix this.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2013-12-18 20:40:05 +01:00
Marek Vasut
eb63218b9b usb: ehci: Fix register access
Fix the register access in EHCI HCD. We need to use address of the register
as an ehci_writel() argument.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
2013-12-18 19:53:19 +01:00
Marek Vasut
1e1be6d478 usb: ehci: Do not de-init uninited controllers
In case the controller is not initialized, we shall not de-initialize it.
As the control structure will not be filled, we will produce a null ptr
dereference if the controller is not inited.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
2013-12-18 19:53:19 +01:00
Marek Vasut
8fb83547b9 usb: ehci-pci: Clarify and cleanup the EHCI controller detection
The detection function of the EHCI PCI controller was really cryptic,
add a beefy comment and clean the portion of the code up a bit. No
change in the logic of the code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
2013-12-18 19:53:19 +01:00
Lukasz Majewski
3990994c43 ARM: trats: dfu: Enable default Poll Timeout for Trats board
Provide default Poll Timeout value for Trats board.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2013-12-18 19:53:19 +01:00
Lukasz Majewski
77b9504288 usb: f_dfu: cosmetic: Code cleanup
Code cleanup for dfu_bind_config function

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2013-12-18 19:53:19 +01:00
Lukasz Majewski
33fac4a6a2 usb: dfu: f_dfu: Provide infrastructure to adjust DFU's Poll Timeout value
It is necessary to deter the host from sending subsequent DFU_GETSTATUS
request in the case of e.g. writing the buffer to medium.

Here the timeout is increased when we fill up the whole buffer. This delay
allows eMMC memory to perform its internal operations.
Otherwise we end up with HOST's error regarding GET_STATUS receive timeout.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2013-12-18 19:53:19 +01:00
Lukasz Majewski
4fb127898e dfu: Export allocated dfu buffer size
The method for exporting size of allocated buffer is provided.
It is afterwards used by USB's dfu function code.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2013-12-18 19:53:19 +01:00
Yen Lin
60acde43d7 spi: tegra: clear RDY bit prior to every transfer
The RDY bit indicates that a transfer is complete. This needs to be
cleared by SW before every single HW transaction, rather than only
at the start of each SW transaction (those being made up of n HW
transactions).

It seems that earlier HW may have cleared this bit autonomously when
starting a new transfer, and hence this code was not needed in practice.
However, this is generally a good idea in all cases. In Tegra124, the
HW behaviour appears to have changed, and SW must explicitly clear this
bit. Otherwise, SW will believe that transfers have completed when they
have not, and may e.g. read stale data from the RX FIFO.

Signed-off-by: Yen Lin <yelin@nvidia.com>
[swarren, rewrote commit description, unified duplicate RDY clearing code
and moved it right before the start of the HW transaction, unconditionally
exit loop after reading RX data, rather than checking if TX FIFO is empty,
since it is guaranteed to be]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-12-19 00:00:51 +05:30
Nobuhiro Iwamatsu
16f47c9c51 spi: Add support SH Quad SPI driver
This patch adds a driver for Renesas SoC's Quad SPI bus.
This supports with 8 bits per transfer to use with SPI flash.

Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-12-18 23:23:41 +05:30
Luka Perkov
57af475389 sf: probe: add support for MX25L2006E
Add support for Macronix MX25L2006E SPI flash.

Signed-off-by: Luka Perkov <luka@openwrt.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-12-18 23:23:41 +05:30
Luka Perkov
28303f617a sf: probe: Hex values are in lower case
All other hex values in sf_probe.c are in lower case so we should
fix this one too.

Signed-off-by: Luka Perkov <luka@openwrt.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-12-18 23:23:41 +05:30
Alban Bedel
766afc3dff arm: tegra: Fix the CPU complex reset masks
The CPU complex reset masks are not matching with the datasheet for
the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20
and T30 the register consist of groups of 4 bits, with one bit for
each CPU core. On T20 the 2 high bits of each group are always stubbed
as there is only 2 cores.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swrren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-12-18 10:19:49 -07:00
Alban Bedel
8f38038193 ARM: tegra: Add the Tamonten™ NG Evaluation Carrier board
Add support for the new Tamonten™ NG platform from Avionic Design.
Currently only I2C, MMC, USB and ethernet have been tested.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-12-18 10:19:49 -07:00
Alban Bedel
ac2ff538cd i2c: tegra: Add the fifth bus on SoC with more than 4 buses
Create the i2c adapter object for the fifth bus on SoC with more than
4 buses. This allow using all the bus available on T30.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-12-18 10:19:49 -07:00
Alban Bedel
3346cbb8e8 ARM: tegra: support SKU b1 of Tegra30
Add the Tegra30 SKU b1 and treat it like other Tegra30 chips.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Reviewed-by: Julian Scheel <julian.scheel@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-12-18 10:19:48 -07:00
Jim Lin
81d21e98b0 ARM: config: USB: Tegra30/114: Fix EHCI timeout issue on "bootp"
Fix the timeout issue after running "bootp" command in u-boot
console. For example you see "EHCI timed out on TD- token=0x...".
TXFIFOTHRES bits of TXFILLTUNING register should be set to 0x10
after a controller reset and before RUN bit is set
(per technical reference manual).

Signed-off-by: Jim Lin <jilin@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-12-18 10:19:48 -07:00
Vidya Sagar
7dcd3a21ff tegra: allow build to succeed with SPL disabled
u-boot-dtb-tegra.bin and u-boot-nodtb-tegra.bin binaries
are generated only if the SPL build is enabled as they have
dependency on SPL build

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-12-18 10:19:48 -07:00
Thierry Reding
e4e251a94a Change maintainer for Avionic Design boards
I no longer work for Avionic Design and don't have access to hardware,
so I'll pass on maintainership to Alban.

Acked-by: Alban Bedel <alban.bedel@avionic-design.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-12-18 10:19:48 -07:00
Thierry Reding
4475c7752d Tegra114: Do not program CPCON field for PLLX
PLLX no longer has the CPCON field on Tegra114, so do not attempt to
program it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-12-18 10:19:48 -07:00
Jimmy Zhang
44de8e22ec Tegra114: Fix PLLX M, N, P init settings
The M, N and P width have been changed from Tegra30. The maximum value
for N is limited to 255. So, the tegra_pll_x_table for Tegra114 should
be set accordingly.

Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-12-18 10:19:48 -07:00
Sergei Ianovich
914f2bd1f0 arm: pxa: init ethaddr for LP-8x4x using DT
When DT define aliases for etherner0 and ethernet1, U-Boot
automatically patched MAC addresses using ethaddr and eth1addr
environment variables respectively.

Custom initialization is no longer needed.

Signed-off-by: Sergei Ianovich <ynvich@gmail.com>
CC: Marek Vasut <marex@denx.de>
2013-12-18 18:15:26 +01:00
Sergei Ianovich
7cd5441eb3 arm: pxa: update LP-8x4x to boot DT kernel
DT kernel requires CONFIG_OF_LIBFDT. 'bootm' needs to know DT location.
In addition, fix kernel console device and enable U-Boot long help.

Signed-off-by: Sergei Ianovich <ynvich@gmail.com>
CC: Marek Vasut <marex@denx.de>
2013-12-18 18:15:25 +01:00
Sergei Ianovich
bf92349b41 arm: pxa: fix 2nd flash chip address on LP-8x4x
Initial configuration has worng address of the second chip.
There is an alias for the 1st chip at 0x02000000 in earlier
verions of LP-8x4x, so the boot normally.

However, new LP-8x4xs have a bigger 1st flash chip, and hang on
boot without this patch.

Signed-off-by: Sergei Ianovich <ynvich@gmail.com>
CC: Marek Vasut <marex@denx.de>
2013-12-18 18:15:25 +01:00
Sergei Ianovich
a3d6ca4323 arm: pxa: fix LP-8x4x USB support
Signed-off-by: Sergei Ianovich <ynvich@gmail.com>
CC: Marek Vasut <marex@denx.de>
2013-12-18 18:15:25 +01:00
Albert ARIBAUD
f4e4aadead Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master' 2013-12-18 17:51:28 +01:00
Masahiro Yamada
57270260ad Makefile: fix broken pipe error for lcd4_lwmon5 board
Before this commit, a broken pipe error sometimes happened
when building lcd4_lwmon5 board with Buildman.

This commit re-writes build rules of
u-boot.spr and u-boot-img-spl-at-end.bin
more simply without using a pipe.

Besides fixing a broken pipe error,
this commit gives us other advantages:

  - Do not generate intermidiate files, spl/u-boot-spl.img
    and spl/u-boot-spl-pad.img for creating u-boot.spr

  - Do not generate an intermidiate file, u-boot-pad.img
    for creating u-boot-img-spl-at-end.bin

Such intermidiate files were not deleted by "make clean" or "make mrpropr".
Nor u-boot-pad.img was ignored by git.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stefan Roese <sr@denx.de>
2013-12-18 10:23:37 -05:00
Bo Shen
ace8f50642 Makefile: fix the typo error for mrproper
Fix the typo error for mrproper from mkproper.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Simon Glass <sjg@chromium.org>
2013-12-18 10:23:36 -05:00
Sergei Ianovich
23f00caf6e ARM: pxa: prevent PXA270 occasional reboot freezes
Erratum 71 of PXA270M Processor Family Specification Update
(April 19, 2010) explains that watchdog reset time is just
8us insead of 10ms in EMTS.

If SDRAM is not reset, it causes memory bus congestion and
the device hangs.

We put SDRAM in selfresh mode before watchdog reset, removing
potential freezes.

Signed-off-by: Sergei Ianovich <ynvich@gmail.com>
CC: Marek Vasut <marex@denx.de>
2013-12-18 16:00:37 +01:00
Yoshihiro Shimoda
f3bf212abc serial_sh: add support for SH7753
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2013-12-18 16:50:00 +09:00
Yoshihiro Shimoda
3067f81f16 net: sh-eth: add support for SH7753
SH7753 has two fast ethernet controllers and two gigabit ethernet
controllers. It is similar to SH7757.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2013-12-18 16:49:45 +09:00
Yoshihiro Shimoda
320cf35080 sh: add support for sh7753evb board
The SH7753 EVB board has SH7753, 512MB DDR3-SDRAM, SPI ROM,
Gigabit Ethernet, and eMMC.

This patch support the following functions:
 - 512MB DDR3-SDRAM, SCIF4, SPI ROM, Gigabit Ethernet, eMMC

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2013-12-18 16:49:08 +09:00
Nobuhiro Iwamatsu
b8f383b86b arm: koelsch: Add support reset function
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2013-12-18 16:35:46 +09:00
Nobuhiro Iwamatsu
bb611cce32 arm: koelsch: Add support I2C
This supports sh_i2c on koelsch board.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2013-12-18 16:35:46 +09:00
Nobuhiro Iwamatsu
90362c0c04 arm: koelsch: Add support Ethernet
The koelsch board has one sh-ether device.
This supports sh-ether.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2013-12-18 16:35:45 +09:00
Nobuhiro Iwamatsu
b9986be084 arm: lager: Add support reset function
The lager board uses I2C for reset.

ned-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2013-12-18 16:35:45 +09:00
Nobuhiro Iwamatsu
b9107adf0b arm: lager: Add support I2C
The lager board has I2C for rcar.
This supports I2C for rcar on lager board.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2013-12-18 16:35:45 +09:00