Commit graph

55545 commits

Author SHA1 Message Date
Gregory CLEMENT
dd1033e4e0 MSCC: add support for Ocelot SoCs
This family of SoCs are found in the Microsemi Switches solution and have
already a support in the linux kernel.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-12-19 15:23:01 +01:00
Gregory CLEMENT
464b96bb80 MIPS: Allow to prefetch and lock instructions into cache
This path add a new helper allowing to prefetch and lock instructions
into cache. This is useful very early in the boot when no RAM is
available yet.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-12-19 15:23:01 +01:00
Gregory CLEMENT
48ee7b6853 MIPS: move create_tlb() in an proper header: mipsregs.h
Export create_tlb() as an inline function in mipsregs.h. It allows to
remove the declaration of the function from the board files.

Then it will allow also to use this function very early in the boot when
the stack is not usable.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-12-19 15:23:01 +01:00
Daniel Schwierzeck
a0abb52c5a MIPS: remove local_irq_[save|restore] from CP0 macros
With moving write_on_tlb() to arch/mips/include/asm/mipsregs.h
there are now compiler warnings when some generic code includes
asm/io.h. This happens for example when enabling OF live tree.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19 15:23:01 +01:00
Gregory CLEMENT
02aea4da1d gpio: mscc-bitbang-spi: Add a simple gpio driver for bitbgang spi
The VCore III SoCs such as the Luton but also the Ocelot can remap an SPI
flash directly in memory. However, for writing in the flash the
communication has to be done by software.

Each of the signal used for the SPI are exposed in a single register. In
order to be able to use the soft-spi driver, the management of this pin
is done through this simple gpio driver.

Even if the main purpose of this driver is to be used by soft-spi, it can
still be used as a normal gpio driver but with limitation: for example
the first pin can't be used as output.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19 15:23:01 +01:00
Gregory CLEMENT
53bdae2418 pinctrl: mscc: Add gpio and pinctrl driver for MSCC MIPS SoCs (VcoreIII based)
This driver supports the pin and gpio controller found in the Ocelot and
Luton SoCs.

The driver was inspired from the pinctrl driver in Linux, but was
simplified and was modified to allow supporting an other SoCs (Luton).

For Ocelot and Luton the controller is the same, only the pins to program
differ.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
[changed to only descend into mscc/ dependent on CONFIG_PINCTRL_MSCC]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19 15:23:01 +01:00
Gregory CLEMENT
bea91b0c9b DW SPI: Allow to overload the management of the external CS
On some platforms, as the Ocelot ones, when wanting to control the CS
through software, it is not possible to do it through the GPIO
controller. Indeed, this signal is managed through a dedicated range of
registers inside the SoC..

By declaring the external_cs_manage function as weak, it is possible to
manage the CS at platform level and then using the appropriate registers.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-12-19 15:23:01 +01:00
Stefan Roese
9766a9c653 mips: mt76xx: linkit/gardena: Don't use CONFIG_OF_EMBED
Building with CONFIG_OF_EMBED generates build warnings, as it should
only be used for debugging purposes. So let's move all MT7688 targets to
CONFIG_OF_SEPARATE instead with this patch.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19 15:23:01 +01:00
Stefan Roese
a5f50e0114 mips: mt76xx: Flush d-cache in arch_misc_init() to solve d-cache issues
It has been noticed, that sometimes the d-cache is not in a
"clean-state" when U-Boot is running on MT7688. This was detected when
using the ethernet driver (which uses d-cache) and a TFTP command does
not complete. Flushing the complete d-cache (again?) here seems to fix
this issue.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19 15:23:01 +01:00
Daniel Schwierzeck
8da7495299 mips: xilfpga: fix DTC warnings
This fixes following DTC warning:

arch/mips/dts/nexys4ddr.dtb: Warning (compatible_is_string_list): /ethernet@10e00000/mdio/phy@1:compatible: property is not a string list

As upstream DTS in Linux doesn't have the offending property,
simply remove it to fix the warning.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19 15:23:01 +01:00
Daniel Schwierzeck
d2f02586fd mips: ath79: fix DTC warnings
Remove all interrupt nodes that cause warnings regarding a missing
interrupt parent. There are no interrupt controller nodes defined
and the device trees don't match the ones in Linux anymore.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
a4bfa0e969 bmips: enable ar-5315u enet support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
93bd64bf05 bmips: bcm6318: add support for bcm6368-enet
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
173e3aec81 bmips: enable vr-3032u enet support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
b07f2dc6a0 bmips: bcm63268: add support for bcm6368-enet
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
ba329fd1f2 bmips: enable dgnd3700v2 enet support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
4518a24c29 bmips: bcm6362: add support for bcm6368-enet
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
54468f5853 bmips: enable ar-5387un enet support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
45934ed846 bmips: bcm6328: add support for bcm6368-enet
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
2e498f23ac bmips: enable wap-5813n enet support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
d9c1f0c23f bmips: bcm6368: add support for bcm6368-enet
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
9622972af4 net: add support for bcm6368-enet
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
9c0c7e8487 bmips: enable nb4-ser enet support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
15591a9ae1 bmips: enable hg556a enet support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
4f88720e6a bmips: bcm6358: add support for bcm6348-enet
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
eb4bdc7cc2 bmips: enable ct-5361 enet support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
9dc07b9493 bmips: bcm6348: add support for bcm6348-enet
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
ec96de3b66 bmips: enable f@st1704 enet support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
d7f5bc1aea bmips: bcm6338: add support for bcm6348-enet
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:00 +01:00
Álvaro Fernández Rojas
55e55fe4a6 net: add support for bcm6348-enet
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19 15:23:00 +01:00
Álvaro Fernández Rojas
6e0faa22dd bmips: bcm6318: add bcm6348-iudma support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:00 +01:00
Álvaro Fernández Rojas
83eae02462 bmips: bcm63268: add bcm6348-iudma support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:00 +01:00
Álvaro Fernández Rojas
b2bf5a2243 bmips: bcm6362: add bcm6348-iudma support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:00 +01:00
Álvaro Fernández Rojas
85132221e2 bmips: bcm6328: add bcm6348-iudma support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:00 +01:00
Álvaro Fernández Rojas
0417eb5590 bmips: bcm6368: add bcm6348-iudma support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:00 +01:00
Álvaro Fernández Rojas
487250e6df bmips: bcm6358: add bcm6348-iudma support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:00 +01:00
Álvaro Fernández Rojas
c225d6619e bmips: bcm6348: add bcm6348-iudma support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:00 +01:00
Álvaro Fernández Rojas
9ab403d0dd bmips: bcm6338: add bcm6348-iudma support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:00 +01:00
Álvaro Fernández Rojas
ccfd69883a dma: add bcm6348-iudma support
BCM6348 IUDMA controller is present on multiple BMIPS (BCM63xx) SoCs.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19 15:23:00 +01:00
Rick Chen
368ff57805 doc: README.ae350: Sync for ax25-ae350 rename
Rename ax25-ae350 as ae350_rv[32|64] for 32 or 64 bit.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-18 13:26:02 +08:00
Rick Chen
ab3f92dee6 riscv: configs: Rename ax25-ae350 defconfig
Remove cpu name from the defconfig naming.
Because other cpus maybe run on AE350 platform.
So only use platfrom name in defconfig naming
will be better.

Also sync MAINTAINERS:
Rename
a25-ae350_32_defconfig as ae350_rv32_defconfig
ax25-ae350_64_defconfig as ae350_rv64_defconfig

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-18 13:25:55 +08:00
Anup Patel
9acaf60bfd riscv: qemu: Imply SIFIVE_SERIAL for emulation
This patch enables SiFive UART driver for QEMU RISC-V emulation
by implying SIFIVE_SERIAL on BOARD_SPECIFIC_OPTIONS.

Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-18 09:56:54 +08:00
Anup Patel
e2842496ac drivers: serial: Add SiFive UART driver
This patch adds SiFive UART driver. The driver is 100% DM driver
and it determines input clock using clk framework.

Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-18 09:56:54 +08:00
Bin Meng
dcad9b8d66 riscv: Remove ae350.dts
This is not used by any board. Remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
3c85099aa3 riscv: bootm: Change to use boot_hart from global data
Avoid reading mhartid CSR directly, instead use the one we saved
in the global data structure before.

With this patch, BBL no longer needs to be hacked to provide the
mhartid CSR emulation for S-mode U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
51ab4570f3 riscv: Save boot hart id to the global data
At present the hart id passed via a0 in the U-Boot entry is saved
to s0 at the beginning but does not preserve later. Save it to the
global data structure so that it can be used later.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
7f5d35a547 riscv: Adjust the _exit_trap() position to come before handle_trap()
With this change, we can avoid a forward declaration.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
10753ef8fd riscv: Return to previous privilege level after trap handling
At present the trap handler returns to hardcoded M-mode/S-mode.
Change to returning to previous privilege level instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
496262cca6 riscv: Fix context restore before returning from trap handler
sp cannot be loaded before restoring other registers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
4b3f5ed5ac riscv: Move trap handler codes to mtrap.S
Currently the M-mode trap handler codes are in start.S. For future
extension, move them to a separate file mtrap.S.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00