ndev->queues is a pointer to pointer, but the allocation wrongly
requests sizeof(struct nvme_queue). Fix it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
The codes currently try to read PCI vendor id of the NVMe block
device by dm_pci_read_config16() with its parameter set as its
root complex controller (ndev->pdev) instead of itself. This is
seriously wrong. We can read the vendor id by passing the correct
udevice parameter to the dm_pci_read_config16() API, however there
is a shortcut by reading the cached vendor id from the PCI device's
struct pci_child_platdata.
While we are here fixing this bug, apparently the quirk stuff handle
codes in nvme_get_info_from_identify() never takes effect since its
logic has never been true at all. Remove these codes completely.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
The R8A7795 and R8A7796 tables use different constants to identify
clock in DT, so split the tables and use the correct constants on
R8A7795. This fixes UART clock misconfiguration on R8A7795.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Pasting longer lines into the U-Boot console prompt sometimes leads to
characters missing. One problem here is the small 16-byte FIFO of the
legacy NS16550 UART, e.g. on x86 platforms.
This patch now introduces a Kconfig option to enable RX buffer support
for all DM based serial drivers. With this option enabled, I was
able paste really long lines into the U-Boot console, without any
characters missing.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This reverts commit 6822cf3ec7.
As Bin Meng has tested and pointed out, we don't need the RX interrupt
for the RX buffer support at all. Just reading all available characters
into a buffer is sufficient to solve the problem with the dropped
characters upon long lines pasted into the U-Boot prompt. Since this
RX buffer support can be implemented in a generic way, without any
device specifica (e.g. for the ns16550), I'll post a new patch with
a new serial RX buffer support for DM, which all DM based serial
drivers can use.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present the ICH SPI opcode registers configuration is done in the
ich_spi_remove() routine, a little bit weird but that's how current.
Linux MTD driver works. This changes to move the opcode registers
configuration to a separate routine ich_spi_config_opcode() which
might be called by U-Boot itself as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
At present the ICH SPI controller driver reads the controller lock
status from its register in the probe routine and saves the lock
status to a member of priv. Later the driver uses the cached status
from priv to judge whether the controller setting is locked and do
different setup.
But such logic is only valid when there is only the SPI controller
driver that touches the SPI hardware. In fact the lock status change
can be trigged outside the driver, eg: during the fsp_notify() call
when Intel FSP is used.
This changes the driver to read the lock status every time when an
SPI transfer is initiated instead of reading the cached one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
To i.MX7ULP, we need to create two info instances for
iomux0 and iomux1 respectively, otherwise iomuxc0/1 will
share one info instance and use one base, because imx_pinctrl_probe
will use info to store base address and etc. But iomuxc0/1
actually have different base address.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
when using SHARE_MUX_CONF_REG, wrong mask is used for
writing config value, which causes mux value is cleared.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Add USB serial download protocol support to SPL. If the SoC started
in recovery mode the SPL will immediately switch to SDP and wait for
further downloads/commands from the host side.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
Support U-Boot images in SPL so that u-boot.img files can be
directly downloaded and executed. Furthermore support U-Boot
scripts download and execution in full U-Boot so that custom
recovery actions can be downloaded from the host in a third
step.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Add SDP (Serial Downloader Protocol) implementation for U-Boot. The
protocol is used in NXP SoC's boot ROM and allows to download program
images. Beside that, it can also be used to read/write registers and
download complete Device Configuration Data (DCD) sets. This basic
implementation supports downloading images with the imx header format
reading and writing registers.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
Add an i2c mux driver providing access to i2c bus segments using a
hardware MUX sitting on a master bus and controlled through gpio pins.
E.G. something like:
---------- ---------- Bus segment 1 - - - - -
| | SCL/SDA | |-------------- | |
| |------------| |
| | | | Bus segment 2 | |
| Linux | GPIO 1..N | MUX |--------------- Devices
| |------------| | | |
| | | | Bus segment M
| | | |---------------| |
---------- ---------- - - - - -
SCL/SDA of the master I2C bus is multiplexed to bus segment 1..M
according to the settings of the GPIO pins 1..N.
Note commit log from kernel
commit 92ed1a76("i2c: Add generic I2C multiplexer using GPIO API")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Peng Fan <peng.fan@nxp.com> (i.MX6QP-Sabreauto)
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Add i2c driver which can be used on both STM32F7 and STM32H7.
This I2C block supports the following features:
_ Slave and master modes
_ Multimaster capability
_ Standard-mode (up to 100 kHz)
_ Fast-mode (up to 400 kHz)
_ Fast-mode Plus (up to 1 MHz)
_ 7-bit and 10-bit addressing mode
_ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
_ All 7-bit addresses acknowledge mode
_ General call
_ Programmable setup and hold times
_ Easy to use event management
_ Optional clock stretching
_ Software reset
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Otherwise:
drivers/usb/gadget/f_fastboot.c:564:32: warning: format "%lx" expects
argument of type "long unsigned int", but argument 3 has type "unsigned
int" [-Wformat=]
Signed-off-by: Tom Rini <trini@konsulko.com>
Staticize a few functions and variables which are no longer exposed.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
There is no guarantee that commands are null-terminated in the USB
request buffer, so limit the length of data that is printed.
Signed-off-by: John Keeping <john@metanate.com>
Tested-by: Steve Rae <steve.rae@raedomain.com>
Fastboot loads an image at CONFIG_FASTBOOT_BUF_ADDR, but currently
tells do_bootm() to look for an image at $loadaddr. This breaks if
CONFIG_FASTBOOT_BUF_ADDR is different from the current user-set
loadaddr.
Instead, tell do_bootm() to pick up the image where it was laoded.
Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Steve Rae <steve.rae@raedomain.com>
- Merge sys_reset data of LD4, Pro4, sLD8 and Pro5
- Merge sys_reset data of LD11 and LD20
- Use primitive UNIPHIER_RESETX() macro because bit assignments for
system reset will be changed for every SoC in the future
- Add NAND and eMMC resets
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Since commit f0776a5517 ("spl: dm: Kconfig: SPL_CLK depends on
SPL_DM"), the following warning is displayed:
$ make uniphier_v8_defconfig
warning: (ARCH_ZYNQ && ARCH_ZYNQMP && STM32F7 && CLK_UNIPHIER) selects
SPL_CLK which has unmet direct dependencies (CLK && SPL_DM)
While I am here, I am removing the prompt to make it user-unconfigurable
option so that "select CLK_UNIPHIER" can be omitted.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Fix the IOMUX setting for SDcard CMD pin at the same time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The dts from kernel is using rk3228-pinctrl as compatible name,
need to sync with it to make the driver work.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This changes pci_mmc driver to use PCI_CLASS_SYSTEM_SDHCI instead of
individual vendor id & device id pair to support generic PCI SD host
controller.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This patch allows to show the EXT_CSD[179] partition_config
register info, just by specifying the dev param:
U-Boot> mmc partconf 0
EXT_CSD[179], PARTITION_CONFIG:
BOOT_ACK: 0x0
BOOT_PARTITION_ENABLE: 0x0
PARTITION_ACCESS: 0x0
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
All boards which use DM_MMC have now been converted to use DM_MMC_OPS.
Drop the option and good riddance.
Signed-off-by: Simon Glass <sjg@chromium.org>
Enable driver model for MMC (including BLK), SATA and USB. Note that USB
does not yet work correctly since the nodes are disabled. Hopefully this
can be resolved by the maintainer.
Signed-off-by: Simon Glass <sjg@chromium.org>
We want to use fsl_esdhc_init() with driver model. Move the mmc_init() out
of this function so that we can use it for our common init.
Signed-off-by: Simon Glass <sjg@chromium.org>
With driver model we want to store the mmc and configuration structure in
platform data. Set up structure up and use it for non-DM as well.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since esdhc_init_common() can fail it should return an error code. Update
this and also adjust the timeout mechanism to use get_timer(), which is a
more common approach.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since esdhc_reset() can fail it should return an error code. Update this
and also adjust the timeout mechanism to use get_timer(), which is a more
common approach.
Signed-off-by: Simon Glass <sjg@chromium.org>
Driver model wants to use the core functions in this file but accesses the
driver-private data in a different way. Move the code into new 'common'
functions and set up stubs to call these. Also sort the operations into
alphabetical order for consistency.
Signed-off-by: Simon Glass <sjg@chromium.org>
With driver model we will not use mmc->priv to access driver-private data.
To accomodate this, update internal functions so that we can pass the
private data directly. This will allow the caller to obtain it as it
prefers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Update this driver to support driver model. This involves implementing the
AHCI operations and reusing existing common code.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present the AHCI uclass is just a shell and we still use the global
functions to access SATA. Fix this by adding operations to the uclass.
Signed-off-by: Simon Glass <sjg@chromium.org>
Driver model wants to use the core functions in this file but accesses the
uclass-private data in a different way. Move the code into new 'common'
functions and set up stubs to call these.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function will not be used with driver model and it relates to the
other exported functions. Move it down next to them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rename dwc_ahsata.h to indicate that it is a private header file. We plan
to create another header with some public functions.
Signed-off-by: Simon Glass <sjg@chromium.org>
There is a strange &(var) coding style in this driver. Adjust it to use
&var instead, which is more usual.
Signed-off-by: Simon Glass <sjg@chromium.org>
With driver model sata_dev_desc[] does not exist. We still want to use the
common code of this driver so update it to pass struct ahci_uc_priv * to
each of these functions, instead of an integer which must be looked up in
sata_dev_desc[].
Signed-off-by: Simon Glass <sjg@chromium.org>
Most of the casts in this driver are not necessary. With driver model we
do not cast from void *. Update the driver to follow this rule.
Signed-off-by: Simon Glass <sjg@chromium.org>
With driver model this becomes uclass-private data. Rename the parameter
varable to reflect this.
With the driver model conversion we will not have any exported functions.
Move all exported functions to be together at the end of the file so that
we can deal with them in one #ifdef block.
Signed-off-by: Simon Glass <sjg@chromium.org>
With the driver model conversion we will not have any exported functions.
Move all exported functions to be together at the end of the file so that
we can deal with them in one #ifdef block.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a function to find the name of an interface type (e.g. "sata", "scsi")
from the interface type enum.
This is useful for generic code (not specific to SATA or SCSI, for
example) that wants to display the type of interface it is dealing with.
Signed-off-by: Simon Glass <sjg@chromium.org>
We cannot call dm_scan_fdt_dev() with of-platdata since there is no device
tree. Fix this with an #if check.
Fixes: 3be9a37 (dm: syscon: scan sub-nodes of the syscon node)
Signed-off-by: Simon Glass <sjg@chromium.org>
The bind() method is called before the device is probed and so the
device has no private data, should use the platform data, and set up
a new struct to hold the mmc and cfg members.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Since we now have clock driver for the RCar Gen3 , add support for
enabling the clock into the SH SDHI driver to prevent hacks in the
board files.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The command handling in this driver is awful, esp. because the driver
depends on command numbers to determine whether this is APPCMD or not.
Also, handling of command RSP response types is totally wrong.
This patch at least plucks out some of the custom command encoding and
fixes the APPCMD handling. The RSP handling still needs work, yet that
might not be needed as it turns out the uniphier-sd.c driver is in much
better shape and supports the same IP, so we might be able to just drop
this driver in favor of the uniphier one.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add MMC DM and DT probing support into the SH SDHI driver.
This patch abstracts out the common bits of the send command
and set ios functions, so they can be used both by DM and non
DM setups and adds the DM probe support.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The long response entry 0..3 LSByte comes from the next response
register MSByte, not from the next response register LSByte. Fix
this to make the driver report correct values in response 136 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
On some flash (like Macronix), QE (quad enable) bit is in the same
status register as BP# bits, and we need preserve its original value
during a reboot cycle as this is required by some platforms (like
Intel ICH SPI controller working under descriptor mode).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
[Refined code for readability]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
We are now using an env_ prefix for environment functions. Rename these
other functions as well, for consistency:
getenv_vlan()
getenv_bootm_size()
getenv_bootm_low()
getenv_bootm_mapsize()
env_get_default()
Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
We are now using an env_ prefix for environment functions. Rename these
for consistency. Also add function comments in common.h.
Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
We are now using an env_ prefix for environment functions. Rename these
two functions for consistency. Also add function comments in common.h.
Quite a few places use getenv() in a condition context, provoking a
warning from checkpatch. These are fixed up in this patch also.
Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
We are now using an env_ prefix for environment functions. Rename these
commonly used functions, for consistency. Also add function comments in
common.h.
Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
We are now using an env_ prefix for environment functions. Rename setenv()
for consistency. Also add function comments in common.h.
Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Use the env_save() function directly now that there is only one
implementation of saveenv().
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Denk <wd@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Even after memory free of phydev, priv is still pointing to the
obsolete address.
So update priv->phydev as NULL after memory free.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Add support for Microchip LAN7500, LAN7800 and LAN7850,
USB to 10/100/1000 Ethernet Controllers.
Signed-off-by: Yuiko Oshino <yuiko.oshino@microchip.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
A few years ago STM32F1 SoCs support has been added :
0144caf22c gpio: stm32: add stm32f1 support
2d18ef2364 ARMv7M: add STM32F1 support
But neither STM32F1 dedicated defconfig nor board was
associated to these commits.
Got confirmation from Tom Rini and Matt Porter to remove
all this code [1]
[1] http://u-boot.10912.n7.nabble.com/Remove-STM32F1-support-td301603.html
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Convert name to show explicitly that we are using milliseconds. For a
watchdog timer this is precise enough.
No functional change intended.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Maximum Data Transfer Size (MDTS) field indicates the maximum
data transfer size between the host and the controller. The
host should not submit a command that exceeds this transfer
size. The value is in units of the minimum memory page size
and is reported as a power of two (2^n).
The spec also says: a value of 0h indicates no restrictions
on transfer size. On the real NVMe card this is normally not
0 due to hardware restrictions, but with QEMU emulated NVMe
device it reports as 0. In nvme_blk_read/write() below we
have the following algorithm for maximum number of logic
blocks per transfer:
u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift);
dev->max_transfer_shift being 0 will for sure cause lbas to
overflow. Let's use 20. With this fix, the NVMe driver works
on QEMU emulated NVMe device.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
NVMe should use the nsze value from the queried device. This will
reflect the total number of blocks of the device and fix detecting
my Samsung 960 EVO 256GB.
Original:
Capacity: 40386.6 MB = 39.4 GB (82711872 x 512)
Fixed:
Capacity: 238475.1 MB = 232.8 GB (488397168 x 512)
Signed-off-by: Jon Nettleton <jon@solid-run.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This adds support to detect the catchall PCI class for NVMe devices.
It allows the drivers to work with most NVMe devices that don't need
specific detection due to quirks etc.
Tested against a Samsung 960 EVO drive.
Signed-off-by: Jon Nettleton <jon@solid-run.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This adds nvme_print_info() to show detailed NVMe controller and
namespace information.
Signed-off-by: Zhikang Zhang <zhikang.zhang@nxp.com>
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
NVM Express (NVMe) is a register level interface that allows host
software to communicate with a non-volatile memory subsystem. This
interface is optimized for enterprise and client solid state drives,
typically attached to the PCI express interface.
This adds a U-Boot driver support of devices that follow the NVMe
standard [1] and supports basic read/write operations.
Tested with a 400GB Intel SSD 750 series NVMe card with controller
id 8086:0953.
[1] http://www.nvmexpress.org/resources/specifications/
Signed-off-by: Zhikang Zhang <zhikang.zhang@nxp.com>
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This adds a new uclass id and block interface type for NVMe.
Signed-off-by: Zhikang Zhang <zhikang.zhang@nxp.com>
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jon Nettleton <jon@solid-run.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
clock driver.
Add or fix the div-field overflow check at the same time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
dwmmc controller has default internal divider by 2,
and we always provide double of the clock rate request by
dwmmc controller. Sync code for all Rockchip SoC with:
4055b46 rockchip: clk: rk3288: fix mmc clock setting
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixup for 'missing DIV_ROUND_UP' conflict for clk_rk3288.c:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This adds a device-model driver for the timer block in the RK3368 (and
similar devices that share the same timer block, such as the RK3288) for
the down-counting (i.e. non-secure) timers.
This allows us to configure U-Boot for the RK3368 in such a way that
we can run with the secure timer inaccessible or uninitialised (note
that the ARMv8 generic timer does not count, if the secure timer is
not enabled).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To fully support DM timer in SPL and TPL, we need a few things cleaned
up and normalised:
- inclusion of the uclass and drivers should be an all-or-nothing
decision for each stage and under control of $(SPL_TPL_)TIMER
instead of having the two-level configuration with TIMER and
$(SPL_TPL_)TIMER_SUPPORT
- when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can
not be compiled in
This normalises configuration to $(SPL_TPL_)TIMER and moves the config
options to drivers/timer/Kconfig (and cleans up the collateral damage
to some defconfigs that had SPL_TIMER_SUPPORT enabled).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The timer-uclass depends on full OF_CONTROL through its interrogation
of /chosen and the code to determine the clock-frequency.
For the OF_PLATDATA case, these code-paths are disabled and it becomes
the timer driver's responsibility to correctly set the clock-frequency
in the uclass priv-data.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For the RK3368, we can reuse the SPI driver (although we'll have to
eventually investigate whether it can be merged with the
designware_spi.c driver) also used for the RK3288 and RK3399.
This adds the necessary compatible string to support the RK3368.
Note that the assumption that GPLL will be clocked at 594MHz is not
true for the RK3368, but this will not lead to incorrect functioning
(just to a lower-than-expected SPI operating frequency): this has been
documented in the driver, so it doesn't cause any headaches when
someone next needs to touch the clock code of this driver.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip (where the other DM-enabled DRAM controller
drivers for rockchip devices should also be moved eventually).
At this stage, only the following feature-set is supported:
- DDR3
- 32-bit configuration (i.e. fully populated)
- dual-rank (i.e. no auto-detection of ranks)
- DDR3-1600K speed-bin
This driver expects to run from a TPL stage that will later return to
the RK3368 BROM. It communicates with later stages through the
os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
init code).
Unlike other DMC drivers for RK32xx and RK33xx parts, the required
timings are calculated within the driver based on a target frequency
and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
time).
The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
register for controlling the operation of its (single-channel) DRAM
controller in the GRF block. This provides for selecting DDR3, mobile
DDR modes, and control low-power operation.
As part of this change, DDRC0_CON0 is also added to the GRF structure
definition (at offset 0x600).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The GMAC in the RK3368 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.
This adds the RK3368-specific logic necessary to reuse this driver.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
As SPI support may be useful in the boot-flow, this adds support for
configuring the SPI controller's clocks in the RK3368 clock driver.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With the clock support in rk3368_clk_set_rate() conditionalized on
various feature definitions, 'priv' can remain unused (e.g. in the
SPL build when only MMC is enabled).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To enable the GMAC on the RK3368, we need to set up the clocking
appropriately to generate a tx_clk for the MAC.
This adds an implementation that implements the use of the <&ext_gmac>
clock (i.e. an external 125MHz clock for RGMII provided by the PHY).
This is the clock setup used by the boards currently supported by
U-Boot (i.e. Geekbox, Sheep and RK3368-uQ7).
This includes the change from commit
- rockchip: clk: rk3368: define GMAC_MUX_SEL_EXTCLK
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
As part of the DRAM initialisation process (running as part of the TPL
stage) on the RK3368, we need to set up the DRAM PLL.
This implements support for configuring the PLL to for 1200, 1332 or
1600 MHz (i.e. for DDR3-1200, DDR3-1333, DDR3-1600 operating modes).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The original clock support for MMC/SD cards on the RK3368 suffered
from a tendency to select a divider less-or-equal to the the one
giving the requested clock-rate: this can lead to higher-than-expected
(or rather: higher than supported) clock rates for the MMC/SD
communiction.
This change rewrites the MMC/SD clock generation to:
* always generate a clock less-than-or-equal to the requested clock
* support reparenting among the CPLL, GPLL and OSC24M parents to
generate the highest clock that does not exceed the requested rate
In addition to this, the Linux DTS uses HCLK_MMC/HCLK_SDMMC instead of
SCLK_MMC/SCLK_SDMMC: to match this (and to ensure that clock setup
always works), we adjust the driver appropriately.
This includes the changes from:
- rockchip: clk: rk3368: convert MMC_PLL_SEL_* definitions to shifted-value form
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To implement a TPL stage (incl. its DRAM controller setup) for the
RK3368, we'll want to configure the DPLL (DRAM PLL).
This commit implements setting the DPLL (CLK_DDR) and provides PLL
configuration details for the common DRAM operating speeds found on
RK3368 boards.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The RK3368 has a somewhat temperamental BootROM (which I learned the
hard way) when it comes to reconfiguring the CPLL and GPLL (in fact,
experiments show that changing the GPLL broke things for me, while
changing the CPLL seems to be more benign). These should not be
modified by the SPL stage, if we intend to return to the BootROM for
chain booting the next stage.
This commit changes the clock initialisation to not change CPLL/GPLL
before returning to the BootROM (i.e. in TPL). As it's safe to change
these settings if we no longer intend to return to U-Boot, we'll run
the full PLL setup a little later (i.e. in SPL).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With the RK3368's limited TPL size, we'll want to use OF_PLATFDATA for
the SPL stage. This implements support for OF_PLATDATA in the clock
driver for the RK3368.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The RK3368 TRM recommends to configure the bandwith adjustment (CON2)
for PLLs to NF/2. This implements this for all reconfigurations of
PLLs and removes the 'has_bwadj' flag (as the RK3368 always has the
bandwidth-adjustment feature according to its manual).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To implement pinctrl support for the RK3368, we need to add the
bit-definitions to configure the IOMUX and tie these into the
pinctrl framework. This also adds the mapping from the IRQ# back
onto the periheral id for the SPI devices.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
There is no real reason to keep the bit-definitions for the IOMUX in
the grf header file (which defines the register layout of the GRF block):
these should only be used by our pinctrl driver (with the possible
exception of early debug-init code in TPL/SPL).
This moves the relevant definitions from the grf_rk3368.h header
into the pinctrl driver pinctrl_rk3368.c.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The RK3368 has two SD/MMC controllers that can be used from U-Boot
both during SPL and for booting an OS from the full bootloader stage.
While both are configured to (mostly) sensible settings from the BROM,
additional configuration for the MMC controller is needed to configure
it to 8bit mode.
This adds pinctrl support for the MMC controller.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this
point), we need support for additional pin-configuration. This commit
adds the pinctrl support for GMAC in RGMII mode:
* adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID
* configures the RGMII pins
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The RK3368 GRF header was still defines with a shifted-mask but with
non-shifted function selectors for the IOMUX defines. As the RK3368
support is still fresh enough to allow a quick change, we do this now
before having more code use this.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
To simplify drivers/Makefile a bit when using TPL/SPL, we consistently
use the $(SPL_TPL_) macro to test for drivers that have separate
configuration symbols for the full U-boot, SPL and TPL stages.
Instead of explicitly repeating them in two separate if-guarded
sections of the Makefile, we can now simply list these options once.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Introduce TPL_CLK to allow finer-grained selection of TPL features
for feature-rich (i.e. DM-based) TPL stages.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
SPL_CLK should also depend on SPL_DM (and not just on CLK).
Add the additional dependency.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
To allow finer grained selection of features for TPL, we introduce
TPL_RAM (in analogy to SPL_RAM).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit models the dependency from SPL_RAM to SPL_DM in Kconfig.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This change introduces TPL variants of the REGMAP and SYSCON config
options (i.e. TPL_REGMAP and TPL_SYSCON in analogy to SPL_REGMAP and
SPL_SYSCON) in preparation of a finer-grained feature selection for
building feature-rich TPL variants.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
SPL_REGMAP and SPL_SYSCON were marked as depending on DM, when a
stricter dependency of SPL_DM was possible. This commit makes the
prereq more specific.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
The OMAP3_SPI driver can work with or without DM_SPI. Moving this
outside of the #if DM_SPI section allows us to include it on boards
that don't support DM_SPI yet.
Signed-off-by: Adam Ford <aford173@gmail.com>
This converts the following to Kconfig:
CONFIG_NAND
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Sync up a few more, add imply's]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_CMD_TCA642X
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This driver is not used in U-Boot. Drop it and its associated CONFIG
options.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This driver is not used by any board. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
It does not seem worth having an option to enable another sub-command in
this legacy driver. Drop this option so that the sub-command is always
available.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This converts the following to Kconfig:
CONFIG_CMD_PCA953X
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Allow sending restart conditions upon direction change as this is
required by some chips.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Heiko Schocher <hs@denxx.de>
Set BM poll size once during priv probe and do not
overwrite it during port probe procedure. Pool is common for
all CP ports.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
TX drain in transmit procedure could cause issues due
to race between drain procedure and transmition of descriptor
between AGGR TXQ and physical TXQ.
TXQ will be cleared before moving to Linux by stop procedure.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
MVPP22 driver support 64 Bit arch and require BM pool
high address configuration.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Remove IRQ configuration from U-Boot PP driver.
U-Boot don't use interrupts and configuration of IRQ in U-Boot
caused crashes in Linux shared interrupt mode.
Also interrupt use is redundant in RX routine since a single RX
queue is used.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
MBUS driver were replaced by AXI in PPv22 and relevant
only for PPv21.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
U-boot use single physical tx queue with size 16 descriptors.
So aggregated tx queue size should be equal to physical tx queue
and cpu descriptor chunk(number of descriptors delivered from
physical tx queue to aggregated tx queue by one chunk) shouldn't be
larger than physical tx queue.
Fix:
Set AGGR_TXQ and CPU_DESC_CHUNK to be 16 descriptors, same as
physical TXQ.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Issue:
BM counters were overrun by probe that called per Network interface and
caused release of wrong number of buffers during remove procedure.
Fix:
Use probe_done and num_ports to call init and remove procedure
once per communication controller.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch enables padding of packets shorter than 64B in TX(set by default).
Disabling of padding causes crashes on MACCIATO board.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
A8K marvell SoC has two South Bridge communication controllers(CP0 and CP1).
Each communication controller has packet processor ports and MDIO.
On MACHIATOBin board ports from CP1 are connected to mdio on CP0.
Issue:
Wrong base address is assigned to MDIO interface during probe.
Fix:
Get MDIO address from PHY handler parent base address.
This should be refined in the future when MDIO driver is implemented.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch add GPIO configuration support in mvpp2x driver.
Driver will handle 10G SFP gpio reset and SFP TX disable. GPIO pins should
be set in device tree.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
In fsl_mc_ldpaa_exit(), in case of mc is booted and dpl is applied,
it should return earlier without executing dpbp_exit().
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Acked-by: Priyanka Jain <priyanka.jain@nxp.com>
Acked-by: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
We shouldn't always change the status to okay. There could be
situations that the esdhc is intentionally disabled in the device
tree.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This bug is brought by the commit 3d8553f0a3 (pci: layerscape: add
LS2088A series SoC pcie support), which only updated cfg_res.start
and did not update the .end field. This causes fdt_resource_size()
getting wrong value when calculate the cfg1 space address.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[YS: Revise subject and commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
Commit 4483b7eb added variable vqmmc_dev but only uses it under
CONFIG_DM_REGULATOR. Add the same macro to variable declaration to
get rid of compiling warning.
Signed-off-by: York Sun <york.sun@nxp.com>
The driver is for all boards 24XX and up, so let's eliminate the
extra option called CONFIG_SYS_I2C_OMAP34XX since the driver checks
for CONFIG_OMAP34XX we don't need CONFIG_SYS_I2C_OMAP34XX.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add missing probe function to the device driver to active a device.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add the print message to tell us why the erase operation doesn't work.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This adds support for Macronix flash MX25U6435F (device ID 0xc22537).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The environment variable "disable_giga" can now be used to disable
1000baseTx on the Micrel's KSZ9031.
Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Added the AFE (Analog Front End) settings for stability to the
Broadcom Cygnus phy. This improves the time take to perform
auto negotiation.
Signed-off-by: Arun Parameswaran <arun.parameswaran@broadcom.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
move to Kconfig:
CONFIG_BCM_SF2_ETH
CONFIG_BCM_SF2_ETH_DEFAULT_PORT
CONFIG_BCM_SF2_ETH_GMAC
Also modified defconfigs of all platforms that use these configs.
Signed-off-by: Suji Velupillai <suji.velupillai@broadcom.com>
Tested-by: Suji Velupillai <suji.velupillai@broadcom.com>
Reviewed-by: JD Zheng <jiandong.zheng@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Steve Rae <steve.rae@raedomain.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The correct option is PHY_MICREL_KSZ90X1, but some configs still
select the 9021 and 9031 options, which are deprecated.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
There should be no longer be any ksz9000 users that pick up the PHY
driver from ksz8xxx, so remove ksz9000 remnants from there.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The KS8721BL and KSZ9021 PHYs are software-incompatible, yet they
share the same ID. Drivers for bothe PHYs cannot safely coexist, so
the solution was to use #ifdefs to select between the two drivers.
As a result KSZ9031, which has a unique ID, is now caught in the
crossfire. Unless CONFIG_PHY_MICREL_KSZ9031 is defined, the KSZ9031
will not function properly, as some essential configuration code is
ifdef'd-out.
To prevent such situations, move the KSZ9000 drivers to a separate
file, and place them under a separate Kconfig option. While it is
possible to enable both KSZ8000 and KSZ9000 drivers at the same time,
the assumption is that it is highly unlikely for a system to contain
both a KSZ8000 and a KSZ9000 PHY, and that only one of the drivers
will be enabled at any given time.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The register constants don't use the exact names that are used in the
TRM, so add comments that use the exact names so that it is clear what
register is being referred to.
https://www.atheros-drivers.com/qualcomm-atheros-datasheets-for-AR9331.html
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Marek Vasut <marex@denx.de>
After upgrading to GCC 7.1, the duplicate const specifies in the
r8152 driver trigger the following build warnings with buildman
(observed on a 'buildman rockchip' test)::
../drivers/usb/eth/r8152.c:62:35: warning: duplicate 'const' declaration specifier [-Wduplicate-decl-specifier]
static const struct r8152_version const r8152_versions[] = {
^~~~~
This commit fixes these by removing the duplicate 'const' specifier
from the declarations.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
phy_device_create(..) sets the addr of phy_device with a sane value.
There is no need overwrite it.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add rk3288 soc specific driver for mipi dsi.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add Makefile item for soc specific driver for rk3399 mipi dsi.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
To compatible with different rockchip soc, we split the mipi dirver into
common and soc specific parts, and all the soc share the common
functions from common driver part.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[agust: fix build breakage and warnings]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
ahci_probe_scsi() now takes a 'base' argument, and there is an API
that prepares base address for us: ahci_probe_scsi_pci().
Reported-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Add support for enabling and disabling the clock using the clock
framework based on the content of OF instead of doing it manually
in the board file.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The order of parameters passed to the phy_connect() was wrong.
Moreover, only PHY address 0 was used. Replace this with code
capable of detecting the PHY address.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add support for probing the RAVB Ethernet block from device tree.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Since we now have clock driver on the RCar Gen3 , obtain the clock
configuration using the clock framework functions. In case this
fails, fall back to the original code for pulling the clock config
directly out of OF.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Convert the SH Serial to Kconfig using tools/moveconfig.py tool
and a bit of manual adjustment to cater for failed conversions.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add clock driver for the RCar Gen3 R8A7795 and R8A7796 SoCs .
This driver allows reading out the clock configuration set by
previous boot stages and enabling and disabling clock using
the MSTP registers. Setting clock is not supported thus far.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Dont use local temporary buffer for printing out the
info instead use directly from memroy. This fixes the
issue of stack corruprion due to local buffer overflow.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
These macros and one variable is not used anywhere that's why
they should be removed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Dont panic incase of mmio write/read failures instead return
error and let the peripheral driver take care of clock get
and set failures.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add support for CCF, this CCF reads the ref clocks
from dt and checks all the required clock control
registers for its source , divisors and calculates
the clock from them. This supports clock and set
functions.
Panic when read/write fails.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Pet the watchdog once upon each command call (qspi_xfer) and during
each loop iteration in several commands.
This fixes a watchdog reset especially during erase command.
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Convert the pci_mmc driver over to driver model and migrate all x86 boards
that use it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: remove DM_MMC from edison_defconfig]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This adds support for PCI-based AHCI controller based on DM SCSI.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
This converts Intel ICH6 GPIO driver to Kconfig, and add it to the
imply list of platform drivers.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
PCI is the de facto interconnect bus in an x86 system.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Without a timer, U-Boot just doesn't boot. This is not something
we can turn off.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Rename try_msr_calibrate_tsc() to cpu_mhz_from_msr(), as that
better describes what the routine does.
This keeps in sync with Linux kernel commit:
02c0cd2: x86/tsc_msr: Remove irqoff around MSR-based TSC enumeration
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Atom processors use a 19.2 MHz crystal oscillator.
Early processors generate 100 MHz via 19.2 MHz * 26 / 5 = 99.84 MHz.
Later processors generate 100 MHz via 19.2 MHz * 125 / 24 = 100 MHz.
Update the Silvermont-based tables accordingly, matching the Software
Developers Manual.
Also, correct a 166 MHz entry that should have been 116 MHz, and add
a missing 80 MHz entry for VLV2.
This keeps in sync with Linux kernel commit:
05680e7: x86/tsc_msr: Correct Silvermont reference clock values
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Some processor abbreviations in the comments of freq_desc_tables[]
are obscure. This updates part of these to mention processors
that are known to us. Also expand frequency definitions.
This keeps in sync with Linux kernel commit:
9e0cae9: x86/tsc_msr: Update comments, expand definitions
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
If either ratio or freq is zero, the return value is zero. There
is no need to create a fail branch and return zero there.
This keeps in sync with Linux kernel commit:
14bb4e3: x86/tsc_msr: Remove debugging messages
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
try_msr_calibrate_tsc() is currently Intel-specific, and should not
execute on any other vendor's parts.
This keeps in sync with Linux kernel commit:
ba82683: x86/tsc_msr: Identify Intel-specific code
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Currently we read the tsc radio like this:
ratio = (MSR_PLATFORM_INFO >> 8) & 0x1f;
Thus we get bit 8-12 of MSR_PLATFORM_INFO, however according to the
Intel manual, the ratio bits are bit 8-15.
Fix this problem by masking 0xff instead.
This keeps in sync with Linux kernel commit:
886123f: x86/tsc: Read all ratio bits from MSR_PLATFORM_INFO
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Some LDOs have a bypass capability. Make sure that the bypass is disabled
when is the LDO is enabled (otherwise the voltage can't be changed).
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Modify palmas_mmc1_poweron_ldo() API to set the voltage based on the
voltage parameter passed as argument instead of always setting it to
3.0V. This allows MMC1 to set the LDO1 regulator voltage to 3.3V or 1.8V.
1.8V is required to add support for UHS mode.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add a driver-model version of this driver which mostly uses the existing
code. The old code can be removed once all boards are switched over.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function has #ifdefs in it which we want to avoid for driver model.
Instead we should use different compatible strings and the .data field.
It also uses the MMC device number which is not available in driver
model except through aliases.
Move the function's into its caller so that the driver-model version can
do things its own way.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
At present the driver-private data is obtained in various functions by
various means. With driver model this is provided automatically. Without
driver model it comes from a C array declared at the top of the file.
Adjust internal functions so that they are passed the private data as
a parameter, allowing the caller to obtain it using either means.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Use the driver-model naming convention for this structure. It is data
private to the driver so the local variable should be called 'priv'.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Use the driver-model naming convention for this structure. It is data
private to the driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This is expected to be attached to the uclass and the code operates that
way, but the uclass has not been updated. Fix it to avoid using memory at
address 0.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 47fc61a (dm: ahci: Drop use of probe_ent)
When the SATA code was moved into drivers/ata these Kconfig options were
added to that directory. They already exist in drivers/scsi. Remove them
from drivers/ata to fix the duplication.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 7f2b5f4 (sata: Move drivers into new drivers/ata directory)
At present if U-Boot proper uses driver model for MMC, then SPL has to
also. While this is desirable, it places a significant barrier to moving
to driver model in some cases. For example, with a space-constrained SPL
it may be necessary to enable CONFIG_SPL_OF_PLATDATA which involves
adjusting some drivers.
Add new SPL versions of the options for DM_MMC, DM_MMC_OPS and BLK. By
default these follow their non-SPL versions, but this can be changed by
boards which need it.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present the AHCI SCSI driver only supports PCI with driver model.
Rename the existing function to indicate this and add support for adding
a non-PCI controller .
Signed-off-by: Simon Glass <sjg@chromium.org>
Migrate all remaining instances of CMD_NAND, CMD_NAND_TRIMFFS
CMD_NAND_LOCK_UNLOCK and CMD_NAND_TORTURE from the headers into the
defconfig files.
Tested-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With driver model the serial device is often not called "serial". Mark
driver-model stdio devices so that they can be detected and we can look up
the uclass. This is a more reliable way of finding out whether the console
is connected to a serial device or not.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add watchdog driver for Intel Tangier based platforms.
Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Move clk_release_all() prototype and definition inside
OF_CONTROL flag to avoid following compilation error for
poplar platform:
aarch64: + poplar
+drivers/usb/host/built-in.o: In function `ehci_usb_remove':
+drivers/usb/host/ehci-generic.c:159: undefined reference to `clk_release_all'
+drivers/usb/host/built-in.o: In function `ehci_usb_probe':
+drivers/usb/host/ehci-generic.c:133: undefined reference to `clk_release_all'
+make[1]: *** [u-boot] Error 139
+make: *** [sub-make] Error 2
Introduced by 4e542c4 clk: add clk_release_all()
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Fix following warnings encountered with platforms
dra7xx_evm and dra7xx_hs_evm :
arm: + dra7xx_evm
+ hccr = (struct xhci_hccr *)devfdt_get_addr(dev);
+ ^
+ hcor = (struct xhci_hcor *)((phys_addr_t)hccr +
+ ^
w+drivers/usb/host/xhci-dwc3.c: In function 'xhci_dwc3_probe':
w+drivers/usb/host/xhci-dwc3.c:124:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
w+drivers/usb/host/xhci-dwc3.c:125:30: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
w+drivers/usb/host/xhci-dwc3.c:125:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
arm: + dra7xx_hs_evm
+ hccr = (struct xhci_hccr *)devfdt_get_addr(dev);
+ ^
+ hcor = (struct xhci_hcor *)((phys_addr_t)hccr +
+ ^
w+drivers/usb/host/xhci-dwc3.c: In function 'xhci_dwc3_probe':
w+drivers/usb/host/xhci-dwc3.c:124:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
w+drivers/usb/host/xhci-dwc3.c:125:30: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
w+drivers/usb/host/xhci-dwc3.c:125:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
Introduced by 7e65e84 usb: host: xhci-dwc3: Convert driver to DM
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This driver is used to stub PHY operations in a driver (USB, SATA).
This is useful when the 'client' driver (USB, SATA, ...) uses the PHY
framework and there is no actual PHY harwdare to drive.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Call generic_phy_init() only when a PHY was found.
This will avoid a crash if no "phys" property is found in DT.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reported-by: Patrick Delaunay <patrick.delaunay@st.com>
Call generic_phy_init() only when a PHY was found.
This will avoid a crash if no "phys" property is found in DT.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reported-by: Patrick Delaunay <patrick.delaunay@st.com>
Add CONFIG_DM_USB flag to avoid following compilation errors
detected by buildman :
+drivers/usb/host/built-in.o: In function `xhci_dwc3_remove':
+drivers/usb/host/xhci-dwc3.c:168: undefined reference to `xhci_deregister'
+drivers/usb/host/built-in.o: In function `xhci_dwc3_probe':
+drivers/usb/host/xhci-dwc3.c:145: undefined reference to `usb_get_dr_mode'
+drivers/usb/host/xhci-dwc3.c:152: undefined reference to `xhci_register'
introduced by patch d5c3f014da3 "usb: host: xhci-dwc3: Convert driver to DM"
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reported-by: Ran Wang <ran.wang_1@nxp.com>
- factorize code between read and write transaction
- always use dfu_transaction_cleanup() to initialize
the internal variable: easy maintenance
- replace direct access by dfu_get_buf() and dfu_get_buf_size()
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change long (32 bits on arm) to u64 (same type than offset)
for size and read offset r_left
So partition and device used for DFU can be greater than 4GB
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
solve issue on get_medium_size() function
the detection of error is a simple test < 0
but for ARM platform, long is 32bits and 2GB = 0x80000000
is seen as error.
I solve the issue by changing the prototype fo the function
to separate size and result.
This patch prepare the next patch with size change to u64.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Fix the memory leak by freeing the allocated out request buffer
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
So far LS/FS devices directly attached to xHC root port can be
successfully enumerated by xHCI driver, but if they are connected
behind a hub, the enumeration process fails to address the device.
It turns out xHCI driver still misses a part that in the device's
input slot context, all Transaction Translator (TT) related fields
are not programmed. The xHCI spec defines how to enable TT.
Now LS/FS devices like USB keyboard/mouse can be enumerated behind
a high speed hub.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
There is no way to know whether the attached device is a hub or
not in advance before the device's descriptor is fetched. But
once we know it's a high speed hub, per the xHCI spec, we need
to tell xHC it's a hub device by initializing hub-related fields
in the input slot context.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For USB host controllers like xHC, its internal representation of
hub needs to be updated after the hub descriptor is fetched. This
adds a new op that does this.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
xHCI spec says: the values of the 'route string' field shall be
initialized by the first 'Address Device' command issued to a
device slot, and shall not be modified by any other command.
So far U-Boot does not program this field, and it does not prevent
SS device directly attached to root port, or HS device behind an HS
hub, from working, due to the fact that 'route string' is used by
the xHC to target SS packets. But in order to enumerate devices
behind an SS hub, this field must be programmed.
With this commit and along with previous commits, now SS & HS devices
attached to a USB 3.0 hub can be enumerated by U-Boot.
As usual, this new feature is only available when DM is on.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For future extension, change xhci_setup_addressable_virt_dev()
signature to accept a pointer to 'struct usb_device', instead
of its members slot_id & speed, as the struct already contains
these two plus some other useful information of the device.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sometimes we need know if a given hub device is root hub or not.
Add a new API to test this. This removes the xHCI driver's own
version is_root_hub() and change to use the new API.
While we are here, remove the unused/commented out get_usb_device()
in the xHCI driver too.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Use USB hub device's dev->uclass_priv to point to 'usb_hub_device'
so that with driver model usb_hub_reset() and usb_hub_allocate()
are no longer needed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
As there is no board that currently uses xhci-pci driver without DM
USB, drop its support and leave only DM support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add CONFIG_USB_XHCI_PCI as a Kconfig option.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
EHC reports supported maximum number of ports in the HCSPARAMS
register, so it's unnecessary to use a hardcoded config option
CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
xHC reports supported maximum number of ports in the HCSPARAMS1
register, so it's unnecessary to use a hardcoded config option
CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
HCSPARAMS1:MaxPorts field specifies the maximum port number value,
and its valid values are in the range of 1 to 255.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
USB 3.0 hubs have a slightly different hub descriptor than USB 2.0
hubs, with a fixed (rather than variable length) size. Change the
host controller drivers that access those last two fields
(DeviceRemovable and PortPowerCtrlMask) to use the union.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Testing a USB 3.0 hub by connecting it to the xHCI port on Intel
MinnowMax, when issuing 'get hub descriptor' to the hub, xHCI
reports a transfer event TRB with a completion code 6 which means
'Stall Error'.
In fact super speed USB hub descriptor type is 0x2a, not 0x29.
Sending correct SETUP packet to the hub makes it not stall anymore.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
A valid input slot context for a 'configure endpoint' command requires
the 'Context Entries' field to be initialized to the index of the last
valid endpoint context that is defined by the target configuration. We
set up the 'Context Entries' field, but we forget to include the input
slot context in the input control context 'Add Context flags' bitmap.
So xHC will simply ignore input slot context and continue using its own
which contains old information of the device.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
