Commit graph

239 commits

Author SHA1 Message Date
Heinrich Schuchardt
421e7a41c6 sunxi: remove __packed from struct sunxi_prcm_reg
struct sunxi_prcm_reg is naturally packed. There is no need to define it as
packed. Defining it as packed leads to compilation errors with GCC 9.2.1:

  CC      arch/arm/lib/reloc_arm_efi.o
arch/arm/cpu/armv7/sunxi/psci.c: In function ‘sunxi_cpu_set_power’:
:qarch/arm/cpu/armv7/sunxi/psci.c:163:21: error: taking address of packed
member of ‘struct sunxi_prcm_reg’ may result in an unaligned pointer value
[-Werror=address-of-packed-member]
  163 |  sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff,
      |                     ^~~~~~~~~~~~~~~~~~~~~~~~~

Remove __packed attribute from struct sunxi_prcm_reg.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-12-18 20:19:58 +05:30
Icenowy Zheng
5f19c93021 sunxi: set PIO voltage to hardware-detected value on startup on H6
The Allwinner H6 SoC has a register to set the PIO banks' voltage. When
it mismatches the real voltage supplied to the VCC to the PIO supply,
the PIO will work improperly.

The PIO controller also has a register that contains the status of each
VCC rail of the PIO supplies, and it has the same definition with the
configuration register. so we can just copy the content of this register
to the configuration register at startup, to ensure the configuration is
correct at startup stage.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
[jagan: s/__maybe__unused/__maybe_unused]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 14:40:34 +05:30
Jernej Skrabec
e8c19ffa98 sunxi: H6: DRAM: Add support for half DQ
Half DQ configuration seems to be very rare for H6 based boards/STBs,
but exists nevertheless. Currently the only known product which needs
this support is Tanix TX6 mini.

This commit adds support for half DQ configuration. Code was tested
for regressions on other configurations (OrangePi 3 1 GiB/LPDDR3, Tanix
TX6 4 GiB/DDR3) and none were found.

Thanks to Icenowy Zheng for help with this code.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: thomas graichen <thomas.graichen@gmail.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Maxime Ripard <mripard@kernel.org>
2019-10-25 14:15:49 +05:30
Andre Przywara
75a8a641f3 sunxi: H6: Add DDR3 support to DRAM controller driver
At the moment the H6 DRAM driver only supports LPDDR3 DRAM.

Extend the driver to cover DDR3 DRAM as well.

The changes are partly motivated by looking at the ZynqMP register
documentation, partly by looking at register dumps after boot0/libdram
has initialised the controller.

Many thanks to Jernej for contributing some fixes!

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16 17:09:41 +05:30
Andre Przywara
770b85a418 sunxi: H6: move LPDDR3 timing definition into separate file
Currently the H6 DRAM driver only supports one kind of LPDDR3 DRAM.
Split the timing parameters for this LPDDR3 configuration  into a
separate file, to allow selecting an alternative later at compile time
(as the sunxi-dw driver does).

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16 17:09:31 +05:30
Clément Péron
26f8e0d7f2 arm: sunxi: h6: fix reset using r_wdog
Some H6 boards have a watchdog which didn't make the SoC
reboot properly.

Reason is still unknown but several people have test it.
Chen-Yu Tsai :
Pine H64 = H6 V200-AWIN H6448BA 7782 => OK
OrangePi Lite 2 = H6 V200-AWIN H8068BA 61C2 => KO

Martin Ayotte :
Pine H64 = H8069BA 6892 => OK
OrangePi 3 = HA047BA 69W2 => KO
OrangePi One Plus = H7310BA 6842 => KO
OrangePi Lite2 = H6448BA 6662 => KO

Clément Péron:
Beelink GS1 = H6 V200-AWIN H7309BA 6842 => KO

After the series of result, Icenowy try to reach Allwinner about this
issue but they seems not interested to investigate it.

As we don't have the ARIS coproc to do power management and watchdogis
the only solution to reset the board.

So, Change from watchdog to R_watchdog to allow a reboot on all H6
boards.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-20 22:24:47 +05:30
Andre Przywara
067e0b9684 sunxi: Allow booting from 128KB SD/eMMC offset
On modern Allwinner SoCs (tested: H2+, A64, H5, H6) the BootROM can
actually load the SPL also from sector 256 (128KB) of an SD card or eMMC
chip. For more details, see [1].
In this case the boot source indicator (written at offset 0x28 of SRAM A1)
has bit 4 set, so it's 0x10 for SD card and 0x12 for eMMC.

Add those new values to the existing boot source check to allow booting
the SPL from those "high" disk offsets as well. For this to work, the
value of CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR needs to be adjusted,
for instance to 0x140 (right after the high SPL). Doing this dynamically
sounds desirable, but looks nasty to implement.

[1] https://groups.google.com/forum/#!topic/linux-sunxi/MaiijyaAFjk

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-10 15:34:32 +05:30
Jagan Teki
99ba430870 reset: Add Allwinner RESET driver
Add common reset driver for all Allwinner SoC's.

Since CLK and RESET share common DT compatible, it is CLK driver
job is to bind the reset driver. So add CLK bind call on respective
SoC driver by passing ccu map descriptor so-that reset deassert,
deassert operations held based on ccu reset table defined from
CLK driver.

Select DM_RESET via CLK_SUNXI, this make hidden section of RESET
since CLK and RESET share common DT compatible and code.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:08 +05:30
Jagan Teki
0d47bc7056 clk: Add Allwinner A64 CLK driver
Add initial clock driver for Allwinner A64.

Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk gate table.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:08 +05:30
Stefan Mavrodiev
da1ae5905e sunxi: board: Add i2c initialization for sun50i
To use TWI0/1/2 the user can select CONFIG_I2C#_ENABLE.
However even the controller is enabled, the mux for the pins
are not set.

This patch follows the existing mux method. Since the pads are
different, separate check is added for each i2c.

Tested with A64-SOM204 board.

Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-18 22:19:08 +05:30
Vasily Khoruzhick
31a4ac4d79 sun50i: A64: add support for R_I2C controller
Allwinner A64 has a I2C controller, which is in the R_ MMIO zone and has
two groups of pinmuxes on PL bank, so it's called R_I2C.

Add support for this I2C controller and the pinmux which doesn't conflict
with RSB.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Vagrant Cascadian <vagrant@debian.org>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-11-13 22:09:10 +05:30
Vasily Khoruzhick
20940ef2a3 mmc: sunxi: add support for automatic delay calibration
A64 and H6 support automatic delay calibration and Linux driver uses it
instead of hardcoded delays. Add support for it to u-boot driver.

Fixes eMMC instability on Pinebook

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cc: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-11-13 22:07:39 +05:30
Andre Przywara
5776610e9e sunxi: store DRAM size in SPL header
At the moment we rely on the infamous get_ram_size() function to learn
the actual DRAM size in U-Boot proper. This function has two issues:
1) It only works if the DRAM size is a power of two. We start to see
boards which have 3GB of (usable) DRAM, so this does not fit anymore.
2) As U-Boot has no notion of reserved memory so far, it will happily
ride through the DRAM, possibly stepping on secure-only memory. This
could be a region of DRAM reserved for OP-TEE or some other secure
payload, for instance. It will most likely crash in that case.

As the SPL DRAM init routine has very accurate knowledge of the actual
DRAM size, lets propagate this wisdom to U-Boot proper.
We re-purpose a currently reserved word in our SPL header for that.
The SPL itself stores the detected DRAM size there, and bumps the SPL
header version number in that case. U-Boot proper checks for a valid
SPL header and a high enough version number, then uses the DRAM size
from there. If the SPL header field is not sufficient, we fall back to
the old DRAM scanning routine.

Part of the DRAM might be present and probed by SPL, but not accessible
by the CPU. They're restricted in the main U-Boot binary, when accessing
the DRAM size from SPL header.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-29 20:41:15 +05:30
Andre Przywara
55d481d201 sunxi: Extend SPL header versioning
On Allwinner SoCs we use some free bytes at the beginning of the SPL image
to store various information. We have a version byte to allow updates,
but changing this always requires all tools to be updated as well.

Introduce the concept of semantic versioning [1] to the SPL header:
The major part of the version number only changes on incompatible
updates, a minor number bump indicates backward compatibility.
This patch just documents the major/minor split, adds some comments
to the header file and uses the versioning information for the existing
users.

[1] https://semver.org

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-10-29 20:41:15 +05:30
Icenowy Zheng
7ac5f33483 sunxi: fix sid base address macro name for H6
In the current H6 CPU memory space code, the SUNXI in the macro name of
the SID address base is wrongly spelled as SNUXI, which leads to SID
readout not working.

Fix this macro name.

Fixes: 55f6b1c351c9 ("sunxi: add basic memory map definitions of H6 SoC")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2018-08-20 17:22:59 +05:30
Icenowy Zheng
da2616543a sunxi: add DRAM support to H6
The Allwinner H6 SoC comes with a set of new DRAM controller+PHY combo.
Both the controller and the PHY seem to be originate from DesignWare,
and are similar to the ones in ZynqMP SoCs.

This commit introduces an initial DRAM driver for H6, which contains
only LPDDR3 support. The currently known SBCs with H6 all come with
LPDDR3 memory, including Pine H64 and several Orange Pi's.

The BSP DRAM initialization code is closed source and violates GPL. Code
in this commit is written by experimenting, referring the code/document
of other users of the IPs (mainly the ZynqMP, as it's the only found PHY
reference) and disassebling the BSP blob.

Thanks for Jernej Skrabec for review and fix some issues in this driver
(including the most critical one which made it to work), and rewrite
some code from register dump!

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
42956f1b85 sunxi: add MMC support for H6
The Allwinner H6 SoC has 3 MMC controllers like the ones in A64, with
the MMC2 come with the capability to do crypto by EMCE.

Add MMC support for H6. EMCE support is not added yet.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
7f51a4020e sunxi: add UART0 setup for H6
The UART0 on H6 is available at PH bank (and PF bank, but the PF one is
muxed with SD card).

Add pinmux configuration.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
10196c9627 sunxi: use sun6i-style watchdog for H6
The H6 SoC has a sun6i-style watchdog in its timer part.

Enable the usage of it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
0558676d4b sunxi: add clock code for H6
The new Allwinner H6 SoC has a brand new CCU layout.

Add clock code for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
80197801f4 sunxi: change RMR64's RVBAR address for H6
Allwinner H6 has a different RVBAR address with A64/H5.

Add conditional RVBAR configuration into the code which does RMR switch.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
e77b7496c6 sunxi: add basic memory map definitions of H6 SoC
The Allwinner H6 SoC come with a totally new memory map.

Add basical definition of the new memory map into a header file, and let
the cpu.h header include it in the situation of H6.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
cadc7c20e5 sunxi: change SUNXI_HIGH_SRAM option to SUNXI_SRAM_ADDRESS
The new Allwinner H6 SoC has its SRAM A1 at neither 0x0 nor 0x10000, but
it's at 0x20000. Thus the SUNXI_HIGH_SRAM option needs to be refactored
to support this new configuration.

Change it to SUNXI_SRAM_ADDRESS, which holds the real address of SRAM
A1 in the memory map.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Lothar Felten
30e71ad5b7 sunxi: R40: add gigabit ethernet clocks
Add clock control entries for the gigabit interface of the Allwinner
R40/V40 CPU

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
2018-07-16 12:27:27 +05:30
Jagan Teki
9c22aec410 usb: sunxi: Use proper reg_mask for clock gate, reset
Masking clock gate, reset register bits based on the
probed controller is proper only due to the assumption
that masking should start with 0 even thought the controller
has separate PHY or shared between OTG.

unfortunately these are fixed due to lack of separate
clock, reset drivers.

Say for example EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG)
so we need to start reg_mask 0 - 2.

This patch calculated the mask, based on the register base
so that we can get the proper bits to set with respect to
probed controller.

We even do this masking by using PHY index specifier from dt,
but dev_read_addr_size is failing for 64-bit boards.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-06-29 10:52:18 +02:00
Jagan Teki
9763df8b8a sunxi: Fix USB PHY index for H3
This patch update the USB PHY index for Allwinner H3.

Same change[1] initially sent, by 'Chen-Yu Tai' but missed
to apply due to recursive version changes on the same series.

[1] https://lists.denx.de/pipermail/u-boot/2018-January/318817.html

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-06-29 10:52:18 +02:00
Vasily Khoruzhick
b62cdbdded sunxi: clock: Fix EHCI and OHCI clocks on A64
EHCI0 is bit 24, EHCI1 - 25, OHCI0 - 28, OHCI1 - 29

Fixes commit fef73766d9 ("sunxi: clock: Fix OHCI clock gating for H3/H5")

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2018-06-13 07:33:42 +02:00
Jagan Teki
f5871a66fd sunxi: Drop legacy usb_phy.c
Allwinner PHY USB code is now part of generic-phy framework,
so drop existing legacy handling like arch/arm/mach-sunxi.c
and related code areas.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28 16:40:43 +05:30
Chen-Yu Tsai
fef73766d9 sunxi: clock: Fix OHCI clock gating for H3/H5
Clock gating bits on H43/H5 were wrong, fix them.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28 16:40:43 +05:30
Jagan Teki
26fc4d6c51 sunxi: clock: Fix clock gating for H3/H5/A64
clock gating bits on a64 are different than H3_H5, so fixed
only required bits on clock_sun6i.h.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28 16:40:43 +05:30
Vasily Khoruzhick
1c353aea2b pwm: sunxi: add support for PWM found on Allwinner A64
This commit adds basic support for PWM found on Allwinner A64.
It can be used for pwm_backlight driver (e.g. for Pinebook)

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2018-05-15 08:18:09 +02:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Miquel Raynal
663e8a9b54
sunxi: allow NAND support to be compiled for sun8i platforms
Add some clocks/PLL definitions as well as the dependency on MACH_SUN8I
in Kconfig.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03 12:11:52 +02:00
Masahiro Yamada
ed3986ca30 bitops: collect BIT macros to include/linux/bitops.h
Same macros are defined in various places.  Collect them into
include/linux/bitops.h like Linux.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:57 +09:00
Tom Rini
2d5e6b4aac Merge git://git.denx.de/u-boot-video 2017-10-29 10:11:08 -04:00
Vasily Khoruzhick
79f285ddeb sunxi: video: split out PLL configuration code
It will be reused in new DM LCD driver.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2017-10-27 09:39:19 +02:00
Quentin Schulz
c96f598be7 sunxi: clk: fix N formula for CPUX clocks
As explained in arch/arm/mach-sunxi/clock_sun8i_a83t.c, clk for CPU
clusters is computed as clk = 24*n. However, the current formula is clk
= 24*(n-1).

This results in a clock set to a frequency that isn't specified as
possible for CPUs.

Let's use the correct formula.

Fixes: f542948b1e ("sunxi: clk: add basic clocks for A83T")

Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-10-25 10:05:05 +02:00
Maxime Ripard
8829076a5b arm: sunxi: Move spl_boot_device in a separate function
U-Boot itself might need to identify the boot device, for example to be
able to tell where to load the kernel from when several options are
possible.

Move the logic of spl_boot_device to a function that is compiled both for
the SPL and the main binary.

Tested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:06 +02:00
Maxime Ripard
3a61b080ac musb: sunxi: switch to the device model
The device model was implemented so far using a hook that needed to be
called from the board support, without DT support and only for the host.

Switch to probing both in peripheral and host mode through the DT.

Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-03 19:12:05 +02:00
Dave Prue
6ff005cf19 sunxi: Fix CONFIG_SUNXI_GMAC references
SUNXI_GMAC was still used to configure the code where as the
same has been renamed and moved to Kconfig in below commit
"sunxi: Move SUNXI_GMAC to Kconfig"
(sha1: 4d43d065db)

Signed-off-by: Dave Prue <dave@prue.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
[Tweek commit message, config_whitelist.txt, build-whitelist.sh]
Signed-off-by: Jagan Teki <jagan@openedev.com>
2017-09-01 20:48:27 +05:30
Maxime Ripard
de9b1771c3 mmc: sunxi: Support new mode
Almost all of the newer Allwinner SoCs have a new operating mode for the
eMMC clocks that needs to be enabled in both the clock and the MMC
controller.

Details about that mode are sparse, and the name itself (new mode vs old
mode) doesn't give much details, but it seems that the it changes the
sampling of the MMC clock. One side effect is also that it divides the
parent clock rate by 2.

Add support for it through a Kconfig option.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-28 22:36:44 +05:30
Icenowy Zheng
39858b12cc sunxi: add PRCM secure switch register definition
Some new Allwinner SoCs' PRCM has a secure switch register, which
controls the access to some clock and power registers in PRCM block.

Add the definition of this register and its bits in the PRCM header
file.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-11 15:49:39 +05:30
Tom Rini
ebba9d1daf Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2017-06-19 08:08:40 -04:00
Jernej Skrabec
b98efa1db3 sunxi: video: Add support for CSC and TVE to DE2 driver
Extend DE2 driver with support for TVE driver, which will be added in
next commit. TVE unit expects data to be in YUV format, so CSC support
is also added here.

Note that HDMI driver has higher priority, so TV out is not probed if
HDMI monitor is detected.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-09 15:30:47 +02:00
Jernej Skrabec
a8191dfec0 sunxi: Add base address for TV encoder
This commit adds TVE base address for Allwinner H3 and H5 SoCs.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-09 15:30:28 +02:00
Icenowy Zheng
f6457ce578 sunxi: Add selective DRAM type and timing
DRAM chip varies, and one code cannot satisfy all DRAMs.

Add options to select a timing set.

Currently only DDR3-1333 (the original set) is added into it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
f43a009959 sunxi: Rename bus-width related macros in H3 DRAM code
The DesignWare DRAM controller used by H3 and newer SoCs use a bit to
identify whether the DRAM is half-width.

As H3 itself come with 32-bit DRAM, the two modes of the bit used to be
named "MCTL_CR_32BIT" and "MCTL_CR_16BIT", but for SoCs with 16-bit DRAM
they're really 8-bit and 16-bit.

Rename the bit's macro, and also rename the variable name in
dram_sun8i_h3.c.

This commit do not add 16-bit DRAM controller support, but the support
will be introduced in next commit.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
9934aba427 sunxi: makes an invisible option for H3-like DRAM controllers
Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like
DesignWare DRAM controller, which do not have official free DRAM
initialization code, but can use modified dram_sun8i_h3.c.

Add a invisible option for easier DRAM initialization code reuse.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Siarhei Siamashka
7f0ef5a945 sunxi: Store the device tree name in the SPL header
This patch updates the mksunxiboot tool to optionally add
the default device tree name string to the SPL header. This
information can be used by the firmware upgrade tools to
protect users from harming themselves by trying to upgrade
to an incompatible bootloader.

The primary use case here is a non-removable bootable media
(such as NAND, eMMC or SPI flash), which already may have
a properly working, but a little bit outdated bootloader
installed. For example, the user may download or build a
new U-Boot image for "Cubieboard", and then attemept to
install it on a "Cubieboard2" hardware by mistake as a
replacement for the already existing bootloader. If this
happens, the flash programming tool can identify this
problem and warn the user.

The size of the SPL header is also increased from 64 bytes
to 96 bytes to provide enough space for the device tree name
string.
[Andre: split patch to remove OF_LIST hash feature]

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2017-05-17 23:23:58 +05:30
Jernej Skrabec
940aed8f6b sunxi: Add clock support for TV encoder
This patch adds support for TV encoder clocks which will be used later.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
2017-05-15 21:22:57 +02:00