Commit graph

62062 commits

Author SHA1 Message Date
Simon Glass
6a3fc91ea7 buildman: Ask genboardscfg to be quiet
Now that this tool has a 'quiet' flag, use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-12-10 21:11:31 -07:00
Simon Glass
69bbdd112b genboardcfg: Support a quiet mode
We don't really need buildman to print this every time it runs. Add a flag
to run quietly, that buildman can use.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-12-10 21:11:30 -07:00
Tom Rini
fd4b8f813f - fix crash and board reset when drawing RLE8 bitmaps
bigger than the framebuffer resolution
 - reduce dead code in video and console uclass routines
   (tested on mx53cx9020, sama5d2_xplained, stm32mp157c-ev1,
    stm32f746-disco, stm32f769-disco and wandboard)
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Merge tag 'fixes-for-2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-video

- fix crash and board reset when drawing RLE8 bitmaps
  bigger than the framebuffer resolution
- reduce dead code in video and console uclass routines
  (tested on mx53cx9020, sama5d2_xplained, stm32mp157c-ev1,
   stm32f746-disco, stm32f769-disco and wandboard)
2019-12-10 15:41:15 -05:00
Simon Glass
cb10579484 test.py: Make search for autoconf.mk more permissive
Buildman doesn't store this file in the same directory as a normal build.
Update the conftest code to handle both cases.

Change-Id: I1fd0e56054d7dc77394a7589336aa0991bd0133d
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-12-10 06:02:49 -07:00
Cristian Ciocaltea
4251fbc6fb buildman: Improve [make-flags] section parser to allow quoted strings
The parser responsible for the '[make-flags]' section in
the '.buildman' settings file is currently not able to
handle quoted strings, as given in the sample bellow:

[make-flags]
qemu_arm=HOSTCC="cc -isystem /add/include" HOSTLDFLAGS="-L/add/lib"

This patch replaces the simple string splitter based on the <space>
delimiter with a regex tokenizer that preserves spaces inside double
quoted strings.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
2019-12-10 05:54:55 -07:00
Heinrich Schuchardt
5e5c785e34 serial: sandbox: support Unicode
Due to a conversion error the sandbox does not accept byte values 0x80-0xff
from the keyboard. The UEFI extended text input unit test requires Unicode
support.

Use unsigned char for the serial buffer.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
2019-12-10 05:54:55 -07:00
Heinrich Schuchardt
15ab77c203 sandbox: add missing compatible property in device tree
In the device tree UEFI unit test the compatible property of the device is
read.

Provide the missing property.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-12-10 05:42:25 -07:00
Swapna Gurumani
e50d238a1c configs: sama5d27_som1_ek: Add default config to read ENV from QSPI
In the initial SPI flash setup, the default bus mode being used was 3,
which is incorrect, causing a CRC error when the ENV was being read from
QSPI. Setting the default bus mode to 0 which is the correct mode.

Signed-off-by: Swapna Gurumani <swapna.gurumani@microchip.com>
2019-12-10 12:43:50 +02:00
Tom Rini
520f955902 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- Increase stack size to avoid a stack overflow during distro boot.
- Add hifive-unleashed-a00.dts for SIFIVE FU540.
- Add OF_SEPARATE support for SIFIVE FU540.
- Add SPL support for Andes AX25 AE350.
- Improve U-Boot SPL / OpenSBI smp boot flow for RISC-V.
2019-12-09 21:53:23 -05:00
Lukas Auer
0e1233ce90 spl: opensbi: wait for ack from secondary harts before entering OpenSBI
At the start, OpenSBI relocates itself to its link address. If the link
address ranges of U-Boot SPL and OpenSBI overlap, the relocation can
lead to code corruption if a hart is still running U-Boot SPL during
relocation. To avoid this problem, the main hart is specified as the
preferred boot hart to perform the relocation. This fixes the code
corruption problems based on the assumption that since the main hart
schedules the secondary harts to enter OpenSBI, it will be the last to
enter OpenSBI. However it was reported that this assumption is not
always correct.

To make sure the assumption always holds true, wait for all secondary
harts to acknowledge the call-function request before entering OpenSBI
on the main hart.

Reported-by: Rick Chen <rick@andestech.com>
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-12-10 08:23:10 +08:00
Lukas Auer
90ae281437 riscv: add option to wait for ack from secondary harts in smp functions
Add a wait option to smp_call_function() to wait for the secondary harts
to acknowledge the call-function request. The request is considered to
be acknowledged once each secondary hart has cleared the corresponding
IPI.

As part of the call-function request, the secondary harts invalidate the
instruction cache after clearing the IPI. This adds a delay between
acknowledgment (clear IPI) and fulfillment (call function) of the
request. We want to use the acknowledgment to be able to judge when the
request has been completed. Remove the delay by clearing the IPI after
cache invalidation and just before calling the function from the
request.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-12-10 08:23:10 +08:00
Lukas Auer
8b3e97badf riscv: add functions for reading the IPI status
Add the function riscv_get_ipi() for reading the pending status of IPIs.
The supported controllers are Andes' Platform Level Interrupt Controller
(PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local
Interruptor (CLINT).

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
2019-12-10 08:23:10 +08:00
Lukas Auer
b86f6d1e64 spl: opensbi: specify main hart as preferred boot hart
OpenSBI uses a relocation lottery to determine the hart to relocate
OpenSBI to its link address. In the U-Boot SPL boot flow, the main hart
schedules the secondary harts to enter OpenSBI before doing so itself.
One of the secondary harts will therefore always be the winner of the
relocation lottery. This is problematic if the link address ranges of
OpenSBI and U-Boot SPL overlap. OpenSBI will be relocated and therefore
overwrite U-Boot SPL while some harts may still run it, leading to code
corruption.

Avoid this problem by specifying the main hart as the preferred boot
hart to perform the OpenSBI relocation. The main hart will be the last
hart to enter OpenSBI, relocation can therefore occur safely.

The boot hart field was added to version 2 of the OpenSBI FW_DYNAMIC
info structure. The header file include/opensbi.h is synchronized with
include/sbi/fw_dynamic.h from the OpenSBI project to update the info
structure. The header file is recent as of commit
7a13beb21326 ("firmware: Add preferred boot HART field in struct
fw_dynamic_info").

Reported-by: Rick Chen <rick@andestech.com>
Suggested-by: Anup Patel <Anup.Patel@wdc.com>
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-12-10 08:23:10 +08:00
Rick Chen
04883bf7ac doc: update AX25-AE350 RISC-V documentation
Add descriptions about U-Boot SPL feature and how to build and run.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
2019-12-10 08:23:10 +08:00
Rick Chen
cca8b1e5b2 riscv: dts: Add #address-cells and #size-cells in nor node
Those are required for cfi-flash driver to get correct address information.
Also modify size description correctly.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
2019-12-10 08:23:10 +08:00
Rick Chen
f05b6569a9 riscv: dts: Support four cores SMP
Add CPU2 and CPU3 information in cpus node
to support four cores SMP booting.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
2019-12-10 08:23:10 +08:00
Rick Chen
444c46413f riscv: Fix clear bss loop in the start-up code
For RV64, it will use sd instruction to clear t0
register, and the increament will be 8 bytes. So
if the difference between__bss_strat and __bss_end
was not 8 bytes aligned, the clear bss loop will
overflow and acks like system hang.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
2019-12-10 08:23:10 +08:00
Rick Chen
31dae22faa spl: cache: Allow cache drivers in SPL
When ax25-ae350 try to enable v5l2 cache
driver in SPL configuration, it need this
option for cache support in SPL.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
2019-12-10 08:23:10 +08:00
Rick Chen
8ba595b6bd riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL
The mcache_ctl csr only can be manipulated in M mode.
Add SPL_RISCV_MMODE for U-Boot SPL to control cache
operation.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
2019-12-10 08:23:10 +08:00
Rick Chen
43a0832ba0 riscv: andes_plic: Fix some wrong configurations
Fix two wrong settings of andes plic driver as below:

1. Fix wrong pending register base definition.
2. Declaring the en variable in enable_ipi() as unsigned int instead of
   int can help to fix wrong plic enabling setting in RV64.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
2019-12-10 08:23:10 +08:00
Rick Chen
7e24518c90 riscv: ax25-ae350: Use generic memory size setup
To get memory size from device tree instead of
get_ram_size(). This can avoid memory access fault
in U-Boot proper after PMP configurations in OpenSBI.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
2019-12-10 08:23:10 +08:00
Rick Chen
cd61e86e6d riscv: ax25-ae350: add SPL configuration
This patch provides four configurations which can support U-Boot SPL
to boot from RAM or FLASH and then boot FIT image including OpenSBI
FW_DYNAMIC firmware and U-Boot proper images from RAM or MMC boot devices.

With ae350_rv[32|64]_spl_defconfigs:

U-Boot SPL will be loaded by gdb or FSBL and runs in RAM in machine mode
and then load FIT image from RAM device on AE350.

With ae350_rv[32|64]_spl_xip_defconfigs:

U-Boot SPL can be burned into SPI flash and run in flash in machine mode
and then load FIT image from SPI flash or MMC device on AE350.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
2019-12-10 08:23:10 +08:00
Rick Chen
ca06444aac riscv: ax25: add SPL support
The U-Boot SPL will boot in M mode and load the FIT image which
include OpenSBI and U-Boot proper images. After loading progress,
it will jump to OpenSBI first and then U-Boot proper which will
run in S mode.

Also remove V5L2_CACHE due to U-Boot SPL code size consideration.
Without this concern, it can be enable manually for performance.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
2019-12-10 08:23:10 +08:00
Rick Chen
31fbf6032d Use dts support from U-Boot via OF_SEPARATE instead of depending from opensbi.
This would help to make the necessary changes in drivers and device trees
in U-Boot tree itself. This feature would also be helpful to not pass
dtb during opensbi builds.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Rick Chen <rick@andestech.com>
2019-12-10 08:23:10 +08:00
Jagan Teki
b82a18549f riscv: dts: Add hifive-unleashed-a00 dts from Linux
Sync the hifive-unleashed-a00 dts from Linux with
below commit details:

commit <2993c9b04e616df0848b655d7202a707a70fc876> ("riscv: dts: HiFive
Unleashed: add default chosen/stdout-path")

Idea is to periodically sync the dts from Linux instead of
tweaking internal changes one after another, so better not
add any intermediate changes in between. This would help to
maintain the dts files easy and meaningful since we are
reusing device tree files from Linux.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-12-10 08:23:10 +08:00
Lukas Auer
6b20dc165e riscv: increase stack size to avoid a stack overflow during distro boot
This fixes a problem, where booting Linux using distro boot will
sometimes lead to an invalid instruction exception on the main hart. The
secondary harts are not affected and boot Linux successfully. The root
cause of this problem is a stack overflow on the main hart.

With distro boot, the current default stack size of 8KiB on RISC-V is
not sufficient and will cause a stack overflow. The stacks are allocated
sequentially. In the case of a stack overflow the stack of the main hart
can reach into that of another hart and be corrupted.

The stack overflow previously did not cause any problems, because only
stack frames, which are not used anymore since the hart enters Linux,
were corrupted. Starting with GCC 9, the stack usage has decreased. Now,
only the most recent stack frame overflows into the stack of a secondary
hart and is corrupted. The illegal instruction exception is caused by
the secondary hart overwriting the return address in the stack frame of
the main hart with an address that does not include valid code.

Increase the default stack size of each hart to 16KiB to avoid this
problem.

Reported-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Tested-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Rick Chen <rick@andestech.com>
2019-12-10 08:23:10 +08:00
Suman Anna
1045ff4d1a ARM: DRA7: Fixup DSP OPP_HIGH clock rate on DRA76P/DRA77P SoCs
The commit 1b42ab3eda ("ARM: DRA7: Fixup DSPEVE, IVA and GPU clock
frequencies based on OPP") added the core logic to update the kernel
device-tree blob to adjust the DSP, IVA and GPU DPLL clocks based on
a one-time OPP choice selected in U-Boot for most of the DRA7xx/AM57xx
family of SoCs.

The DSPs on DRA76xP/DRA77xP SoCs (DRA76x ACD package SoCs) though
provide a higher performance and can run at a higher clock frequency
of 850 MHz at OPP_HIGH instead of 750 MHz. Fix up the logic to use the
correct clock rates on these SoCs. Note that this higher clock rate is
not applicable to other Jacinto 6 Plus SoCs (DRA75xP/DRA74xP SoCs or
AM574x SoCs) that follow the ABZ package.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-12-09 14:00:24 -05:00
Tom Rini
ac1ca99926 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-net 2019-12-09 13:48:22 -05:00
Ben Wolsieffer
2c4e067d49 cmd: pxe: Increase maximum path length
On NixOS, cross compiled kernels have long suffixes that cause them to
exceed the current maximum path length. The PXE/TFTP max path length is
used for extlinux.conf support as well, which is where this problem
usually manifest's itself.

Signed-off-by: Ben Wolsieffer <benwolsieffer@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:49:48 -06:00
Vignesh Raghavendra
c627abe0de configs: j721e_evm_a72_defconfig: Enable DMA and Ethernet
Enable configs related to DMA and Ethernet so as to support networking at
U-Boot prompt

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-12-09 09:47:43 -06:00
Vignesh Raghavendra
4886f1cb59 arm: dts: k3-j721e-common-proc-board: Add DMA and CPSW related DT nodes
Add DT nodes related to DMA and CPSW to -u-boot.dtsi to get networking
up on J721e EVM.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-12-09 09:47:43 -06:00
Vignesh Raghavendra
382c0c629e net: ti: am65-cpsw-nuss: Add new compatible for J721e
Add new compatible to handle J721e SoC

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-12-09 09:47:43 -06:00
Vignesh Raghavendra
461a290c5a net: ti: am65-cpsw-nuss: Rework RX flow ID handling
Get flow ID information for RX DMA channel using dma_get_cfg() interface
instead of reading from DT. This is required in order to avoid DT update
whenever there is change in the range of flow ID allocated to the host.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-12-09 09:47:43 -06:00
Vignesh Raghavendra
5e6d9ccde9 dma: ti: k3-udma: Implement dma_get_cfg() interface
Implement dma_get_cfg() interface to pass flow id information for DMA
clients to use. This is needed because on K3 SoCs, CPSW (ethernet) and
UDMA (DMA provider) support "flows" within a given RX DMA channel. This
allows different network packets to be segregated while using same RX
DMA channel. In order for basic ethernet to work, CPSW slave must be
aware of the flow ID allocated for the RX channel by the DMA driver.
This interface allows CPSW to query flow ID from DMA provider and
configure it in CPSW HW.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-12-09 09:47:43 -06:00
Vignesh Raghavendra
b8a4dd28f3 dma: Introduce dma_get_cfg() interface
Sometimes, there would be a need to exchange data between DMA provider
and DMA client which are very specific to DMA driver of the SoC/platform
and are not generic enough to be put into struct dma. Therefore, introduce
dma_get_cfg() interface to get DMA provider specific data from client
device. Clients can use unique configuration ID flags to get different
configuration data from DMA driver.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-12-09 09:47:43 -06:00
Cédric Le Goater
08b3e90a01 net: ftgmac100: align RX/TX descriptors on ARCH_DMA_MINALIGN
Fixes: e766849713 ("net: ftgmac100: convert the RX/TX descriptor arrays")
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
1e354cb393 drivers: net: fsl_enetc: register internal MDIO bus
This bus is used to access internal SoC PHYs.  These PHYs are configured
by the ENETC driver directly, but it's useful to have command line access
to this MDIO to debug the system especially when using new external PHYs.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
6c96446859 drivers: net: fsl_enetc_mdio: return with time-out if HW is stuck
On some boards MDIO may get stuck if it detects echo on the line.  This is
a know hardware issue, there is a board fix for it.  In case we're running
on a board that doesn't have the fix, we don't want to loop here forever
and freeze U-Boot.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
a931f78307 drivers: net: fsl_enetc: move PCS and PHY config to probe
This reduces the time needed to establish a link as we don't reset the link
each time the interface is used.  Our Link capabilities do not change at
run-time so there is no need to re-apply PHY configuration each time.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
307f8a6d1f drivers: net: fsl_enetc: Add 2.5Gbps to supported link speeds
The original code enabled link speeds up to 1Gbps, but the interface can
go up to 2.5G, enable that speed to in PHY AN mask.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
17bd7eae72 drivers: net: fsl_enetc: use the new MDIO DM helper functions
Uses the new dm_eth_phy_connect helper to connect to the PHY to simplify
the code.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
2f6245594e net: mdio-uclass: add dm_eth_phy_connect helper function
The function connects an ethernet device to a PHY using DT information.
This API is only available for eth devices with an associated device tree
node.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
a5d32c37d9 net: mdio-uclass: rename arguments of dm_mdio_phy_connect for clarity
Renamed dm_mdio_phy_connect arguments dev to mdiodev and addr to phyaddr
for a bit more clarity and consistency with the following patches.
Also use NULL instead of 0 on error return path.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Andre Przywara
16cdc2daa0 net: tftp: Fix too small block size
Commit b618b37076 ("net: Convert CONFIG_TFTP_BLOCKSIZE to Kconfig")
accidentally set the default *option* TFTP block size to 512 bytes, even
though the comment in the code says that this is a terrible choice. Most
boards didn't define the symbol before, so they got the default block size
of 1468 bytes before, but now use 512 bytes, which is also the fallback.
This leads to both abysmal performance and a lot of hashes printed
on the screen (one character for every 5K), which is both annoying and
slow over serial links.

Set the default block size in Kconfig back to the value it had before.

This improves TFTP performance from 2.8 MB/s to 6.9 MB/s on a Pine64.

Fixes: b618b37076 ("net: Convert CONFIG_TFTP_BLOCKSIZE to Kconfig")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
e22e3aff92 drivers: net: fsl_enetc: use XFI, USXGMII interface type macros
Apply 10G PCS init for USXGMII, XFI interface types.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
ee278acdf1 doc: bindings: Aquantia PHY node binding
A couple of optional properties have been introduced for Aquantia PHY
allowing the driver to set up wiring related configuration points that
are otherwise driven by firmware.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
e81031c2b8 doc: bindings: add bindings document for PHY nodes
It defines that PHY nodes must be children on MDIO bus nodes and defines
the only required property in U-Boot, reg.  This property along with the
example provided are copied over from Linux.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
6d9bc2043a drivers: net: aquantia: check system interface too when checking for link up
In some cases the link on the system interface of the aquantia PHY comes up
after the link on line interface.  The link state loop only checks the line
side, which may result in first packet sent being lost.
Use aquantia_link_is_up instead, which checks both system and line side on
gen 2/3 PHYs to avoid losing the 1st packet.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
05f86070c0 drivers: net: aquantia: set SMBus addr based on DT property
Aquantia PHYs have a SMBus interface mostly used for debug.  The addresses
on this interface are normally set up by PHY firmware, but depending on the
board they may end up not being unique.  Add an optional DT property used
to change SMBus address if needed.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
7552ee9a01 drivers: net: aquantia: set MDI reversal based on DT property
MDI pins up to the RJ45 connector may be reversed on the board and the
default PHY configuration applied by firmware may or may not match that.
Add an optional DT property to configure MDI reversal for this case.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00