Commit graph

19701 commits

Author SHA1 Message Date
Jean-Jacques Hiblot
1a83f9931e phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC
Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES
wrapper used to configure some of the input signals to the SERDES. It is
used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures
three clock selects (pll0, pll1, dig) and supports resets for each of the
lanes.

This is an adaptation of the linux driver.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-10-kishon@ti.com
2021-07-27 10:57:12 +05:30
Aswath Govindraju
193c735162 phy: cadence: Add driver for Torrent SERDES
Add driver for Torrent SERDES.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-9-kishon@ti.com
2021-07-27 10:57:12 +05:30
Alan Douglas
39b823381d phy: cadence: Add driver for Sierra PHY
Add a Sierra PHY driver with PCIe and USB support.
This driver is a port from the mainline linux driver.

The PHY has multiple lanes, which can be configured into
groups, and a generic PHY device is created for each group.

There are two resets controlling the overall PHY block, one
to enable the APB interface for programming registers, and
another to enable the PHY itself.  Additionally there are
resets for each PHY lane.

The PHY can be configured in hardware to read register
settings from ROM, or they can be written by the driver.

The sequence of operation on startup is to enable the APB
bus, write the PHY registers (if required)  for each lane
group, and then enable the PHY.  Each group of lanes
can then be individually controlled using the power_on()/
power_off() function for that generic PHY

One difference with the linux driver is that the PHY is
always reset after it is powered-on. This is because role
switching is not supported in u-boot and the cable
orientation is handled by the PHY reset.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Alan Douglas <adouglas@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-8-kishon@ti.com
2021-07-27 10:57:12 +05:30
Kishon Vijay Abraham I
77cbaf8837 dm: core: Add helper to compare node names
Add helper to compare node names.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20210721155849.20994-2-kishon@ti.com
2021-07-27 10:56:53 +05:30
Aswath Govindraju
46077ef251 mmc: sdhci_am654: Read ti, strobe-sel property from device tree
Read the strobe select value from the device tree property ti,strobe-sel,
required for HS400 speed mode

Fixes: a20008eabd ("mmc: am654_sdhci: Add Support for configuring PHY in J721e")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Link: https://lore.kernel.org/r/20210525093826.10390-2-a-govindraju@ti.com
2021-07-27 10:56:09 +05:30
Faiz Abbas
bda47bef7c mmc: sdhci: Write to HOST_CONTROL2 register for HS400 speed mode
Enable HS400 speed mode by writing to HOST_CONTROL2 register.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Link: https://lore.kernel.org/r/20210405144428.12159-1-a-govindraju@ti.com
2021-07-27 10:56:09 +05:30
Michal Simek
bfc05d7e2a psci: Do not define do_poweroff() if CONFIG_SYSRESET_CMD_POWEROFF is enabled
CONFIG_SYSRESET_CMD_POWEROFF defines do_poweroff() in sysreset-uclass.c
that's why don't define it twice when both CONFIG_SYSRESET_CMD_POWEROFF and
CONFIG_CMD_POWEROFF are enabled. CONFIG_SYSRESET_CMD_POWEROFF depends on
CONFIG_CMD_POWEROFF.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26 09:18:45 +02:00
Ashok Reddy Soma
258ce79cfc net: xilinx: axi_mrmac: Add MRMAC driver
Add support for xilinx multirate(MRMAC) ethernet driver.
This driver uses multichannel DMA(MCDMA) for data transfers of MRMAC.
Added support for 4 ports of MRMAC for speeds 10G and 25G.
MCDMA supports upto 16 channels but in this driver we have setup only
one channel which is enough.

Tested 10G and 25G on all 4 ports.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26 09:18:45 +02:00
Michal Simek
0c383a7957 clk: zynqmp: Add support for enabling clock on lpd_lsbus
lpd_lsbus is clock which is used by many IPs like dmas, gems, gpio, sdhcis,
spis, ttcs, uarts, watchdog that's why make sense to also enable access to
change this clock. For this clock you already get the rate.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26 09:18:45 +02:00
Michal Simek
419b4a86f7 mmc: zynq_sdhci: Make variables/structure static
All these variables/structure are local and should be static.

Issues are reported by sparse:
drivers/mmc/zynq_sdhci.c:49:11: warning: symbol 'zynqmp_iclk_phases' was not declared. Should it be static?
drivers/mmc/zynq_sdhci.c:50:11: warning: symbol 'zynqmp_oclk_phases' was not declared. Should it be static?
drivers/mmc/zynq_sdhci.c:53:11: warning: symbol 'versal_iclk_phases' was not declared. Should it be static?
drivers/mmc/zynq_sdhci.c:54:11: warning: symbol 'versal_oclk_phases' was not declared. Should it be static?
drivers/mmc/zynq_sdhci.c:546:24: warning: symbol 'arasan_ops' was not declared. Should it be static?

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-26 09:18:45 +02:00
Michal Simek
c0436fcf1a mmc: zynq_sdhci: Fix kernel doc warnings
Fix these kernel doc warnings:
drivers/mmc/zynq_sdhci.c:181: warning: contents before sections
drivers/mmc/zynq_sdhci.c:236: warning: contents before sections
drivers/mmc/zynq_sdhci.c:291: warning: contents before sections
drivers/mmc/zynq_sdhci.c:297: warning: Function parameter or member 'degrees' not described in                   'sdhci_versal_sdcardclk_set_phase'
drivers/mmc/zynq_sdhci.c:354: warning: contents before sections
drivers/mmc/zynq_sdhci.c:360: warning: Function parameter or member 'degrees' not described in                   'sdhci_versal_sampleclk_set_phase'
drivers/mmc/zynq_sdhci.c:467: warning: contents before sections

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-26 09:18:45 +02:00
Ashok Reddy Soma
a70bdafd67 mmc: zynq_sdhci: Split set_tapdelay function to in and out
Split arasan_zynqmp_set_tapdelay() to handle input and output tapdelays
separately. This is required to handle zero values for ITAP and OTAP
values. If we dont split, we will have to remove the if() in the
function, which makes ITAP values to be overwritten when OTAP values are
called to set and vice-versa.

Restrict tap_delay value calculated to max allowed 8 bits for ITAP and 6
bits for OTAP for ZynqMP.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26 09:18:45 +02:00
Ashok Reddy Soma
ee9ae005dc mmc: zynq_sdhci: Use Mask writes for Tap delays
Restrict tap_delay value to the allowed size(8bits for itap and 6 bits
for otap) before writing to the tap delay register.

Clear ITAP and OTAP delay bits before updating with the new tap value
for Versal platform.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26 09:18:45 +02:00
Ashok Reddy Soma
affcba728b mmc: zynq_sdhci: Allow configuring zero Tap values
Allow configuring ITAP and OTAP values with zero to avoid failures in
some cases (one of them is SD boot mode). Legacy, SDR12 modes require
to program the ITAP and OTAP values as zero, whereas for SDR50 and SDR104
modes ITAP value is zero.

In SD boot mode firmware configures the SD ITAP and OTAP values and
in this case u-boot has to re-configure required tap values(including zero)
based on the operating mode.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26 09:18:45 +02:00
Ashok Reddy Soma
8e34aa00e9 mmc: zynq_sdhci: Resolve uninitialized return value
set_phase() functions are not modifying the ret value and returning
the same uninitialized ret, return 0 instead.

Keep the return type as int to return errors when the tapdelay's are
set via xilinx_pm_request() in future.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26 09:18:45 +02:00
Chen Baozi
91a043896d serial: pl011: Enable DEBUG_UART_PL011 in SPL
Commit b81406db51 ("arm: serial: Add debug UART capability to the
pl01x driver") add supports to use pl01x as a debug UART. However,
due to CONFIG_IS_ENABLED macro requires CONFIG_SPL_* prefix, the
_debug_uart_init() would not choose TYPE_PL011 in SPL build. This
patch fixes the bug by judging CONFIG_DEBUG_UART_PL011 explicitly.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-24 08:57:53 -04:00
Chia-Wei Wang
bc7b38450b reset: ast2600: Fix missing reference operator
Fix missing reference operator '&' to correctly get
HW register addresses for writel().

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-07-24 08:57:53 -04:00
Chen Baozi
198201509a serial: pl011: Resend the character if FIFO is full in debug uart
pl01x_putc() might return -EAGAIN if there was no space in FIFO. In that
case, high-level caller should wait until there is space and resend the
character.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-23 18:53:46 -04:00
Stephan Gerhold
ad7e967738 serial: serial_msm: Delay initialization to let pins stabilize
For some reason, the DragonBoard 410c aborts autoboot immediately if
U-Boot is started without LK. It looks like it picks up a single broken
character via serial and therefore believes a key was pressed to abort
autoboot.

After some debugging, it seems like adding some delay after pinctrl
setup but before UART initialization fixes the issue. It's also worth
mentioning that unlike when booting from LK, the pinctrl setup is
actually necessary when booting U-Boot without LK since UART is broken
if the pinctrl line is removed.

I suspect that reconfiguring the pins might take some time to stabilize
and if the UART controller is enabled too quickly it will pick up some
random noise. Adding a few milliseconds of delay fixes the issue and
shouldn't have any other negative side effects.

3ms seems to be the minimum delay required in my tests, use 5ms instead
just to be sure.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2021-07-23 18:53:46 -04:00
Masami Hiramatsu
1ad3c8365a board: synquacer: Initialize SCBM SMMU at board_init()
Since the SCBM SMMU is not only connected to the NETSEC
but also shared with the F_SDH30 (eMMC controller), that
should be initialized at board level instead of NETSEC.

Move the SMMU initialization code into board support
and call it from board_init().

Without this fix, if the NETSEC is disabled, the Linux
eMMC ADMA cause an error because SMMU is not initialized.

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-23 18:53:45 -04:00
Nandor Han
c74675bd90 reboot-mode: read the boot mode from RTC memory
RTC devices could provide battery-backed memory that can be used for
storing the reboot mode magic value.

Add a new reboot-mode back-end that uses RTC to store the reboot-mode
magic value. The driver also supports both endianness modes.

Signed-off-by: Nandor Han <nandor.han@vaisala.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-23 10:16:39 -04:00
Nandor Han
f9db2f16cb reboot-mode: read the boot mode from GPIOs status
A use case for controlling the boot mode is when the user wants
to control the device boot by pushing a button without needing to
go in user-space.

Add a new backed for reboot mode where GPIOs are used to control the
reboot-mode. The driver is able to scan a predefined list of GPIOs
and return the magic value. Having the modes associated with
the magic value generated based on the GPIO values, allows the
reboot mode uclass to select the proper mode.

Signed-off-by: Nandor Han <nandor.han@vaisala.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-23 10:16:39 -04:00
Nandor Han
2541ce2c1a reboot-mode: add support for reboot mode control
A new driver uclass is created to handle the reboot mode control.

The new uclass driver is updating an environment variable with the
configured reboot mode. The mode is extracted from a map provided
at initialization time. The map contains a list of modes
and associated ids.

Signed-off-by: Nandor Han <nandor.han@vaisala.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-23 10:16:39 -04:00
Lukasz Majewski
2132fce7e1 i2c: pcf8575: Add support for 8 bit I2C IO expanders (like pca8574)
This patch add support for using NXP's pca8574 I2C IO expander, which
has only 8 IO lines.

After this change the .data member's information from struct udevice_id
are used to either sent one or two bytes.

Moreover, the '_le16' suffix from pcf8575_i2c_{write|read}_le16()
functions have been removed as now we also sent 8 bit data.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2021-07-23 07:13:25 -04:00
Lukasz Majewski
0119c91052 i2c: pcf8575: Remove not used members of pcf8575_chip structure
Those members are not used anymore as ones from gpio_dev_priv
structure (when DM_GPIO support is enabled) are used instead.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2021-07-23 07:13:25 -04:00
Etienne Carriere
9e6da34c72 tee: optee: sync cache on pre-reloc OP-TEE invocation
This change ensures both U-Boot and OP-TEE see the same content
from shared memory when OP-TEE is invoked prior U-Boot relocation.

This change is required since U-Boot may execute with data cache off
while OP-TEE always enables cache on memory shared with U-Boot.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-07-23 07:13:25 -04:00
Tom Rini
4906d698d3 Merge branch 'network_master' of https://source.denx.de/u-boot/custodians/u-boot-net 2021-07-22 23:05:28 -04:00
Cosmin-Florin Aluchenesei
669884ea6f net: fsl-mc: fix logically dead code
The result of dpio_close() is actually taken into account.

Signed-off-by: Cosmin-Florin Aluchenesei <aluchenesei.cosmin-florin@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-22 22:16:26 +03:00
Cosmin-Florin Aluchenesei
b9b7b5e49c drivers: net: aquantia: fix unsigned compared against 0
Change the reg variable to not be unsigned so that we not get into an
unsigned compared against 0.

Signed-off-by: Cosmin-Florin Aluchenesei <aluchenesei.cosmin-florin@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-22 22:15:33 +03:00
Patrick Delaunay
b547f4bd9e net: dwc_eth_qos: define LOG_CATEGORY
Define LOG_CATEGORY to allow filtering with log command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-22 22:09:27 +03:00
Patrick Delaunay
a5db6e1d81 net: eth-phy: define LOG_CATEGORY
Define LOG_CATEGORY to allow filtering with log command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-22 22:09:27 +03:00
Patrick Delaunay
c6a0df2d1d net: dwc: add a common empty ops eqos_null_ops
Add a common empty ops: eqos_null_ops() to remove the duplicated empty
functions and reduce the driver size for stm32 and imx config.

This patch also aligns the prototype of ops 'eqos_stop_clks' with other
eqos ops by adding return value.

Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-07-22 22:05:44 +03:00
Patrick Delaunay
9dbdc234a7 net: dwc_eth_qos: use generic ethernet phy for stm32 variant
Use the generic ethernet phy which already manages the correct binding
for gpio reset, including the assert an deassert delays.

Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-07-22 22:05:44 +03:00
Patrick Delaunay
ebf9a91f86 net: dwc_eth_qos: remove the field phyaddr of the struct eqos_priv
Since the commit commit 6a895d039b ("net: Update eQos driver and FEC
driver to use eth phy interfaces") the field phyaddr of driver private data
struct eqos_priv is no more used in eqos_start() for the phy_connect()
parameter.

Now this variable is only initialized in eqos_probe_resources_stm32()
it can be removed.

Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-07-22 22:05:44 +03:00
Patrick Delaunay
035d8483ac net: eth-phy: manage subnode mdio0
Bind any subnode with name beginning by mdio, mdio0 for example,
and not only the "mdio" as namei of subnode.

Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-07-22 22:05:44 +03:00
Patrick Delaunay
880ecb09b9 net: eth-phy: use dev_dbg and log_notice
Replace debug trace and printf to log macros:
- debug() replaced by dev_dbg() when device is available, this macro
indicate the device name since commit ceb70bb870 ("dm: Print device
name in dev_xxx like Linux")
- printf() replaced by log_notice() to allow  dispatch to log backends.

Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-07-22 22:05:44 +03:00
Patrick Delaunay
d33982d5bc net: eth-phy: add support of device tree configuration for gpio reset
The gpio reset and the assert or deassert delay are defined in generic
binding of the ethernet phy in Linux:
Documentation/devicetree/bindings/net/ethernet-phy.yaml

  reset-gpios:
    maxItems: 1
    description:
      The GPIO phandle and specifier for the PHY reset signal.

  reset-assert-us:
    description:
      Delay after the reset was asserted in microseconds. If this
      property is missing the delay will be skipped.

  reset-deassert-us:
    description:
      Delay after the reset was deasserted in microseconds. If
      this property is missing the delay will be skipped.

See also U-Boot: doc/device-tree-bindings/net/phy.txt

This patch adds the parsing of this common DT properties in the
u-class "eth_phy_generic", used by default in the associated driver
"eth_phy_generic_drv"

This parsing function eth_phy_of_to_plat can be reused by other
ethernet phy drivers for this uclass UCLASS_ETH_PHY.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-22 22:05:28 +03:00
Peter Hoyes
b8da46fda6 net: Use phys_addr_t for SMC net device addresses
Use same type as eth_device->iobase and support addresses greater
than INT_MAX.

Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2021-07-22 21:55:05 +03:00
Chen Guanqiao
1b098b3e65 dm: core: fix no null pointer detection in ofnode_get_addr_size_index()
Fixed a defect of a null pointer being discovered by Coverity Scan:
   CID 331544:  Null pointer dereferences  (REVERSE_INULL)
   Null-checking "size" suggests that it may be null, but it has already been
   dereferenced on all paths leading to the check.

Signed-off-by: Chen Guanqiao <chenguanqiao@kuaishou.com>
2021-07-21 10:27:35 -06:00
Simon Glass
96f37b092f blk: Support iteration
It is useful to be able to iterate over block devices. Typically there
are fixed and removable devices. For security reasons it is sometimes
useful to ignore removable devices since they are under user control.

Add iterators which support selecting the block-device type.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-21 10:27:35 -06:00
Simon Glass
6b165ab2b7 sandbox: mmc: Support fixed MMC devices
Add support for reading devicetree flags for MMC devices. With this we
can distinguish between fixed and removable drives. Note that this
information is only available when the device is probed, not when it is
bound, since it is read in the of_to_plat() method. This could be changed
if needed later.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-21 10:27:35 -06:00
Simon Glass
56dae9ef3c cros_ec: Use standard calls for recovery-request checking
Rather than calling directly into the sandbox SDL code, we can use the
normal U-Boot console handling for this feature. Update the code, to make
it more generic.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-21 10:27:34 -06:00
Simon Glass
656d744770 cros_ec: Support the full-size vboot context
The v2 format is 64-bytes in size. Support this and drop v1 since it is
not used anymore.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-21 10:27:34 -06:00
Simon Glass
1e465eb669 cros_ec: Drop cros_ec_entering_mode()
This function is not needed anymore. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-21 10:27:34 -06:00
Simon Glass
201efb2bb0 cros_ec: Allow reading the battery-charge state
Add a function to read this information from the EC. It is useful for
determining whether the battery has enough charge to boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-21 10:27:34 -06:00
Simon Glass
504fb66997 dm: Support lzma in the flashmap
Allow lzma compression as well as lz4.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-21 10:27:34 -06:00
Simon Glass
4bbaa88fad dm: core: Add logging for DM_SEQ_ALIAS
It is sometimes helpful to see which sequence is assigned to a device.
Add debugging info for that.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-21 10:27:34 -06:00
Marek Vasut
85cd345dc8 sysinfo: rcar3: Add Renesas R-Car Gen3 sysinfo driver
The Renesas R-Car Gen3 development kits contain board ID EEPROM.
This driver parses out the board ID and revision out of that
EEPROM and exports it e.g. for the board-info print on boot.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Sean Anderson <sean.anderson@seco.com>
Cc: Simon Glass <sjg@chromium.org>
2021-07-20 23:33:54 +02:00
Tom Rini
83befb4466 Merge tag 'ti-v2021.10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-ti
- Enabled distro boot for all TI platforms.
- Cleanup for AM335x Guardian Board
- PRUSS rproc on AM65 platform.
- Add PMIC support for J7200
- Misc fixes for Nokia RX-51

# Conflicts:
#	arch/arm/mach-omap2/am33xx/Kconfig
2021-07-19 08:29:24 -04:00
Tom Rini
ac9fa5705c pci: Require DM_PCI
As the migration deadline has passed, require that DM_PCI be used.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-18 21:06:08 -04:00