Commit graph

1343 commits

Author SHA1 Message Date
Andy Shevchenko
c974a3d155 watchdog: tangier: Convert to use WDT class
Convert legacy driver to use watchdog class.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2019-06-22 22:27:13 +08:00
Andy Shevchenko
7ce74b70b9 x86: Revert "Don't set up MTRRs in SPL"
This breaks Intel Edison to work. It gets laggish and unable to boot kernel.

Reverts commit 665cb18ea6 for now
till better solution will be proposed.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-22 22:26:22 +08:00
Christian Gmeiner
b52e9f0cb7 x86: coreboot: make it possible to process unhandled tags
coreboot makes it possible to add own entries into coreboot's
table at a per mainboard basis. As there might be some custom
ones it makes sense to provide a way to process them.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-19 16:17:33 +08:00
Vagrant Cascadian
048a92ea54 Fix spelling of available.
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
2019-05-09 19:52:55 -04:00
Simon Glass
3dc13cc3a0 x86: samus: Update device tree for verified boot
Add nvdata drivers for the TPM and RTC as used on samus. These are needed
for Chromium OS verified boot on samus.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:19 +08:00
Simon Glass
969ed01242 x86: samus: Update device tree for SPL
Add tags to allow required nodes to be present in SPL / TPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:19 +08:00
Simon Glass
7c03caf6fa x86: Add a simple TPL implementation
Add the required CPU code so that TPL builds correctly. Also update the
SPL code to deal with being booted from TPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:18 +08:00
Simon Glass
49dffb7a07 x86: Add a way to jump from TPL to SPL
When TPL finishes it needs to jump to SPL with the stack set up correctly.
Add a function to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:18 +08:00
Simon Glass
bfeeb8d863 x86: broadwell: Update PCH to work in TPL
The early init should only happen once. Update the probe method to
deal with TPL, SPL and U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:18 +08:00
Simon Glass
e766d9f183 x86: Fix device-tree indentation
With the use of a phandle we can outdent the device tree nodes a little.
Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:17 +08:00
Simon Glass
c5edefb7f7 x86: Update device tree for Chromium OS verified boot
The standard image generated by U-Boot on x86 is u-boot.rom. Add a
separate image called image.bin for verified boot. This supports
verification in TPL of which SPL/U-Boot to start, then jumping to the
correct one, with SPL setting up the SDRAM and U-Boot proper providing
the user interface if needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:17 +08:00
Simon Glass
93c7607580 x86: Update device tree for TPL
Add TPL binaries to the device x86 binman desciption. When enabled, TPL
will start first, doing the 16-bit init, then jump to SPL and finally
U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:17 +08:00
Simon Glass
bf4d8beb12 x86: Don't generate a bootstage report in SPL
This report is normally generated by U-Boot proper. Correct the condition
here so that it respects the Kconfig options for bootstage.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:16 +08:00
Simon Glass
665cb18ea6 x86: Don't set up MTRRs in SPL
The MTRRs are normally set up in U-Boot proper, so avoid setting them up
in SPL as well.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:16 +08:00
Simon Glass
9fa31fc51d x86: Support TPL in Intel common code
Update the Makefie rules to ensure that the correct files are built when
TPL is being used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:16 +08:00
Simon Glass
2b36eabd8a x86: broadwell: Implement PCH_REQ_PMBASE_INFO
Implement this ioctl() to support power off.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:15 +08:00
Simon Glass
9ffe7cd5c4 x86: ivybridge: Implement PCH_REQ_PMBASE_INFO
Implement this ioctl() to support power off.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:15 +08:00
Simon Glass
079b38ba04 x86: mrccache: Add more debugging
When the MRC cache fails to save it is useful to have some debugging info
to indicate what when wrong. Add some more debug() calls.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:14 +08:00
Simon Glass
9a67994e01 x86: Support saving MRC data from SPL
When SPL is used to set up the memory controller we want to save the MRC
data in SPL to avoid needing to pass it up to U-Boot proper to save. Add a
function to handle that.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:14 +08:00
Simon Glass
17903c06e8 x86: Add common Intel code for SPL
Add an implementation of arch_cpu_init_f() so that the x86 SPL code builds
and identifies the CPU.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:14 +08:00
Simon Glass
c0052b6efd x86: broadwell: Select refcode and CPU code for SPL
Allow broadwell to build for SPL and include the reference code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:14 +08:00
Simon Glass
43294e67d6 x86: broadwell: Allow booting from SPL
At present broadwell only supports booting straight into U-Boot proper.
Add a separate init file to boot from SPL into U-Boot proper, and select
it when SPL is in use.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:13 +08:00
Simon Glass
d68574a72d x86: Allow 16-bit init to be in TPL
At present we support having 16-bit init be in SPL or U-Boot proper, but
not TPL. Add support for this so that TPL can boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:13 +08:00
Simon Glass
051c31b7a4 x86: Add support for starting from SPL/TPL
When a previous phase of U-Boot has run we need to adjust the init of
subsequent states to avoid messing up the CPU state.

Add a new version of the start logic for SPL, when it boots from TPL
(start_from tpl.c) and a new version for U-Boot when it boots from SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:13 +08:00
Simon Glass
9231206b73 x86: broadwell: Split CPU init
Split the CPU init into two parts - the 'full' init which happens in the
first U-Boot phase, and the rest of the init that happens on subsequent
stages.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:13 +08:00
Simon Glass
6b83b29578 x86: broadwell: Move init of debug UART to cpu.c
At present the debug UART is set up in sdram.c which is not the best place
since it has nothing in particular to do with SDRAM. Since we want to
support initing this in SPL too, move it to a common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: added 'broadwell' tag in the commit title]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:12 +08:00
Simon Glass
4eabf1e54b x86: broadwell: Allow SDRAM init from SPL
At present, for broadwell, SDRAM is always set up in U-Boot proper since
the 64-bit mode (which uses SDRAM init in SPL) is not supported.

Update the code to allow SDRAM init in SPL instead so that U-Boot proper
can be loaded into SDRAM and run from there. This allows U-Boot to be
compressed to reduce space, since it is not necessary to run it directly
from flash. It could later allow us to support 64-bit U-Boot on broadwell.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:12 +08:00
Simon Glass
9f6486bff4 x86: broadwell: Improve SDRAM debugging output
Add debugging during SDRAM init so that problems are easier to
diagnose.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:12 +08:00
Simon Glass
62be5dd885 x86: Add a handoff header file
Add an arch-specific handoff header so that we can use the HANDOFF feature
on x86 devices.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:12 +08:00
Simon Glass
7c2ca877fe x86: Support booting with TPL
Some boards want to use TPL as the first phase of U-Boot. This allows
selection of A or B SPL phases, thus allowing the memory init to be
upgraded in the field.

Add a new Kconfig option for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:12 +08:00
Simon Glass
9898790247 x86: Support SPL and TPL
At present only chromebook_link64 supports SPL. It is useful to eb able to
support both TPL and SPL to implement verified boot on x86.

Enable the options for both along with some suitable default options
needed to boot through these phases.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:11 +08:00
Simon Glass
20d97f33f0 x86: dts: Add device-tree labels for rtc and reset
Add labels for these nodes so that board DT files can reference them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:11 +08:00
Simon Glass
c0069e9a8a x86: Add a way to reinit the cpu
We cannot init the CPU fully both than once during a boot. Add a new
function which can be called to figure out the CPU identity, but which
does not change anything. For x86_64, this is empty for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:11 +08:00
Simon Glass
7b14023880 x86: mp_init: Use proper error numbers
At present many of the functions in this file return -1 as an error
number. which is -EPERM. Update the code to use real error numbers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:11 +08:00
Simon Glass
11b7cc37f1 x86: Update a stale comment about ifdtool
We use binman to build the x86 image now. Update a comment which still
refers to ifdtool.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:10 +08:00
Simon Glass
4a5fc6a069 x86: start64: Fix copyright message
There is a typo in this header. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:10 +08:00
Neil Armstrong
51e4e3e5d0 x86: dts: switch spi-flash to jedec, spi-nor compatible
The x86 code and DT uses "spi-flash" to detect a flash node, switch to
"jedec,spi-nor" in the DTS files and in fdtdec by switching the
GENERIC_SPI_FLASH value to to jedec,spi-nor.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-04-12 10:54:27 +05:30
Bin Meng
3592965aff x86: crownbay: Enable the beeper sound driver
Use the i8254 sound driver to support creating simple beeps.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-03-11 22:55:01 +08:00
Bin Meng
8edaf34cfe x86: coreboot: Add the missing pc speaker node in the device tree
This is currently missing and without it the i8254 beeper driver
won't work.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-03-11 22:55:01 +08:00
Bin Meng
9b2c8c3066 x86: Add a dtsi file for the pc speaker
The pc speaker driven by the i8254 is generic enough to deserve
a single dtsi file to be included by boards that use it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-03-11 22:55:01 +08:00
Bin Meng
7d0a53a40c x86: Make sure i8254 is setup correctly before generating beeps
The i8254 timer control IO port (0x43) should be setup correctly
by using PIT counter 2 to generate beeps, however in U-Boot other
codes like TSC driver utilizes PIT for TSC frequency calibration
and configures the counter 2 to a different mode that does not
beep. Fix this by always ensuring the PIT counter 2 is correctly
initialized so that the i8254 beeper driver works as expected.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-03-11 22:55:01 +08:00
Andy Shevchenko
d9b59fc9ae x86: edison: Add the rest of UARTs present on board
Intel Edison has three UART ports, i.e.
 port 0 - Bluetooth
 port 1 - auxiliary, available for general purpose use
 port 2 - debugging, usually console output is here

Enable all of them for future use.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-10 08:17:00 +08:00
Andy Shevchenko
ab83e5c1a2 x86: edison: Use proper number of serial interface
The console is actually serial #2. When we would like to enable other ports,
this would be not okay to mess up with the ordering.

Thus, fix the number of default console interface to be 2.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-10 08:17:00 +08:00
Andy Shevchenko
edf18a83f8 x86: acpi: Not every platform has serial console a first device
We may not do an assumption that current console device is always a first
of UCLASS_SERIAL one.

For example, on properly described Intel Edison board the console UART
is a third one.

Use current serial device as described in global data.

Fixes: a61cbad78e ("dm: serial: Adjust serial_getinfo() to use proper API")
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-10 08:17:00 +08:00
Andy Shevchenko
c652dd1557 x86: acpi: Add DMA descriptors for I2C1 on Intel Tangier
Intel Tangier SoC has a general purpose DMA which can serve to speed up
communications on SPI and I2C serial buses.

Provide DMA descriptors to utilize this capability in the future.

Note, I2C6, which is available to user, has no DMA request lines connected.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-10 08:17:00 +08:00
Andy Shevchenko
1d2825aa30 x86: acpi: Add DMA descriptors for SPI5 on Intel Tangier
Intel Tangier SoC has a general purpose DMA which can serve to speed up
communications on SPI and I2C serial buses.

Provide DMA descriptors to utilize this capability in the future.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-10 08:17:00 +08:00
Simon Glass
e2c901c99e x86: Add sound support for samus
Enable sound on samus using the broadwell I2S and an RT5677 audio codec.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-02-20 15:27:11 +08:00
Simon Glass
3f3411ebf8 x86: broadwell: Add support for serial I/O devices
Add support for initing the I2C device and ADSP on broadwell. These are
needed for sound to work.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:10 +08:00
Simon Glass
c692f82240 x86: broadwell: Don't bother probing the PCH for pinctrl
At present the pinctrl probes the PCH but since it only uses it to obtain
a PCI address, this is no necessary. Avoiding this fixes one of the two
co-dependent loops in broadwell.

This driver really should be a proper pinctrl driver, but for now it
remains a syscon device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:10 +08:00
Simon Glass
23e8bd7e49 x86: broadwell: Add support for the ADSP
The Application Digital Signal Processor is used for sound processing with
broadwell. Add a driver to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:10 +08:00