This patch adds lpuart support for Vybrid VF610 platform.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
This patch adds FEC support for Vybrid VF610 platform.
In function fec_open(), RCR register is only set as RGMII mode. But RCR
register should be set as RMII mode for VF610 platform.
This configuration is already done in fec_reg_setup(), so this piece of
code could just leave untouched the FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
FEC_RCNTRL_MII_MODE bits.
Signed-off-by: Alison Wang <b18965@freescale.com>
Reviewed-by: Benoit Thebaudeau <benoit.thebaudeau@advansee.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
This patch does a similar code reogranzation from
http://patchwork.ozlabs.org/patch/132179/
which is based on an old version of code (fdt support and bus selection
still not in). It merges this tidy-up on top of the recent code. It does
not make any logical change.
tpm.c implements the interface defined in tpm.h based on underlying
LPC or I2C TPM driver. tpm.c and the underlying driver communicate
throught tpm_private.h.
Note: Merging the LPC driver with tpm.c is left to future patches.
Change-Id: Ie1384f5f9e3935d3bc9a44adf8de80c5a70a5f2b
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add support for Infineon's new SLB 9645 TT 1.2 I2C TPMs,
which supports clockstretching, combined reads and a bus speed of
up to 400khz. The device also has a new device id.
This is based on the kernel patch provided by Infineon :
https://gerrit.chromium.org/gerrit/42332
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Luigi Semenzato <semenzato@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Tom Wai-Hong Tam <waihong@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
The new name is more aligned with Linux kernel's naming of TPM driver.
Signed-off-by: Peter Huewe <peter.huewe@infineon.com>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Wai-Hong Tam <waihong@chromium.org>
This patch adds a print messages while using 'sf read' and
'sf write' commands to make sure that how many bytes read/written
from/into flash device.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Tom Rini <trini@ti.com>
This patch adds a print messages while using 'sf erase' command
to make sure that how many bytes erased in flash device.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Tom Rini <trini@ti.com>
Missing return after memcpy is done for memory-mapped SPI flashes,
hence added retun 0 after memcpy done.
The return is missing in below patch
"sf: Enable FDT-based configuration and memory mapping"
(sha1: bb8215f437)
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Simon Glass <sjg@chromium.org>
Support interfaces with a preamble before each received message.
We handle this when the client has requested a SPI_XFER_END, meaning
that we must close of the transaction. In this case we read until we
see the preamble (or a timeout occurs), skipping all data before and
including the preamble. The client will receive only data bytes after
the preamble.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
This patch is essentially an update of u-boot MTD subsystem to
the state of Linux-3.7.1 with exclusion of some bits:
- the update is concentrated on NAND, no onenand or CFI/NOR/SPI
flashes interfaces are updated EXCEPT for API changes.
- new large NAND chips support is there, though some updates
have got in Linux-3.8.-rc1, (which will follow on top of this patch).
To produce this update I used tag v3.7.1 of linux-stable repository.
The update was made using application of relevant patches,
with changes relevant to U-Boot-only stuff sticked together
to keep bisectability. Then all changes were grouped together
to this patch.
Signed-off-by: Sergey Lapin <slapin@ossfans.org>
[scottwood@freescale.com: some eccstrength and build fixes]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Add support for Winbond's W25PXX SPI flash.
These devices is used on Faraday A369 evaluation board.
Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
CC: Tom Rini <trini@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Add support for Winbond W25Q256 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
This is a S25FL064A successor. It supports up to 104MHz bus
speed.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
SPANSION recommend S25FL128S supersedes S25FL129P, and the two flash
memory have the same device ID and Memory architecture. So they can
use the same config parameters.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
- Added SERDES2 PRTCLs = 0x98, 0x9E
- Default Phy Addresses for Teranetics PHY on XAUI card
The PHY addresses of Teranetics PHY on XAUI riser card are assigned
based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on
AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1
and slot2
- Configure MDIO for 10Gig Mac
Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
TN80xx has same PHY ID as TN2020, but it needs different setting to register
30.93 which used to select line, so we read register 30.32 which has
bit 15:12 to indicate PHY hardware version, for TN20xx we will get 3 or 2,
for TN80xx we will get 5 or 4.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
When base address given was out of valid flash address ranges,
flash_get_info() function returned the pointer to the last
element of flash_info[i] array.
This patch changes this function to return NULL pointer
in such a case, which is more correct behaviour.
The function flash_protect_default() calls flash_protect()
immediately after flash_get_info() invocation.
With this correction, flash_protect() function would be
able to return soon, for NULL flash_info.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Linux Kernel Documentation/CodingStyle says:
Do not add a space after unary operators such as &, *, ...
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Packed structure cfi_qry contains unaligned 16- and 32-bits members,
accessing which causes problems when cfi_flash driver is compiled with
-munaligned-access option: flash initialization hangs, probably
due to data error.
Since the structure is supposed to replicate the actual data layout
in CFI Flash chips, the alignment issue can't be fixed in the structure.
So, unaligned fields need using of explicit unaligned access macros.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Reviewed-By: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Stefan Roese <sr@denx.de>
When a all 0xFF buffer is passed to drop_ffs, the no-0xFF check loop
will loop forever.
After the fix, If ssize_t i = -1 and size_t l = i + 1, the value of l
will still be 0 as expected.
Signed-off-by: Tao Hou <hotforest@gmail.com>
Cc: Ben Gardiner <bengardiner@nanometrics.ca>
Cc: Scott Wood <scottwood@freescale.com>
When writelen is mtd->writesize - 1, it is still a partial page write
Signed-off-by: Tao Hou <hotforest@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
This avoids needing a separate U-Boot config when some revisions
of a board have small-page NAND and other revisions have large-page
NAND (except for NAND SPL targets).
CONFIG_FSL_ELBC_FMR is removed -- it was never used nor documented, and
it gets in the way of this change.
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch enables the uart tx/rx fifo. Now that fifo is enabled,
the uart read/write functions are modfied to check the UFSTAT register
for fifo status instead of UTRSTAT (as required with fifo's enabled).
Tested by booting linux kernel. Before enabling tx/rx fifo
"Uncompressing linux" message is garbled and after enabling it is proper.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds driver for the gigabyte devices
GD25LQ and GD25Q64B required for Snow Board.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@ti.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Currently the mxsfb driver takes the display timings from the 'videomode'
environment variable.
Provide an example on how to set 'videomode' for using splash screen on
mx23evk and mx28vk boards.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Marek Vasut <marex@denx.de>
The logic for the whether to configure for polling or DMA
was mistakenly reversed in this patch:
Commit 7b43db9211
drivers/mmc/fsl_esdhc.c: fix compiler warnings
Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
CC: Sun Yusong-R58495 <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Faraday FTSDC010 is a MMC/SD host controller.
Although there is already a driver in current u-boot release,
which is modified from eSHDC and contributed by Andes Tech.
Its performance is too terrible on Faraday A36x SoC platforms,
so I turn to implement this new version of driver which is
10+ times faster than the old one.
It's carefully designed to be compatible with Andes chips,
so it should be safe to replace it.
Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Andy Fleming <afleming@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The Freescale MPC8220 Power Architecture processors have long reached
EOL; Freescale does not even list these any more on their web site.
Remove the code to avoid wasting maitaining efforts on dead stuff.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
The mpc85xx repuires a special layout on the memory device that is
connected to the eSDHC controller interface. But the file spl_mmc.c
didn't handle this specfic case, there needs a special treatmen, in
the powerpc drictory. So, there is no longer to keep spl_mmc.c on
mpc85xx, CONFIG_SPL_FRAMEWORK is not set.
When CONFIG_SPL_MMC_SUPPORT is set and CONFIG_SPL_FRAMEWORK is not
set, there was an error in drivers/mmc/spl_mmc.c:
drivers/mmc/libmmc.o:(.got2+0x8): undefined reference to `spl_image'.
Now, the solution is to move the file "spl_mmc.c" to directory "common/spl".
Signed-off-by: Ying Zhang <b40530@freescale.com>
This is what we have done for the UTMI PHY on P3041/P5020. Then the PHY
initialization can be reused in kernel without “usb start” command.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes
interfaces for quad-port dual media capability. This driver supports SGMII
and QSGMII MAC mode. For now SGMII mode is tested.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
- set proper compatible property name for mEMAC.
- fixed ft_fixup_port for dual-role mEMAC, which will lead to
MAC node disabled incorrectly.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
T4160 SoC is low power version of T4240. The T4160 combines eight dual
threaded Power Architecture e6500 cores and two memory complexes (CoreNet
platform cache and DDR3 memory controller) with the same high-performance
datapath acceleration, networking, and peripheral bus interfaces.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
T4240 internal UTMI phy is different comparing to previous UTMI PHY
in P3041.
This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for
T4240.
The phy timing is very sensitive and moving the phy enable code to
cpu_init.c will not work.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
1. fix 10G mac offset by plus 8;
2. add second 10G port info for FM1 & FM2 when init ethernet info;
3. fix 10G lanes name to match lane protocol table;
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Added the LAN9730 to list of supported devices. This chip is used
in the sEVM, uEVM and som5_evb. Tested on the som5_evb with dhcp
and ping.
Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
The gpio spec for bf54x and bf60x differ a lot from the old gpio driver for bf5xx.
A lot of machine macros are used to accomodate both code in one gpio driver.
This patch split the old gpio driver and move new gpio2 support to the generic
gpio driver folder.
- To enable gpio2 driver, macro CONFIG_ADI_GPIO2 should be defined in the board's
config header file.
- The gpio2 driver supports bf54x, bf60x and future ADI processors, while the
older gpio driver supports bf50x, bf51x, bf52x, bf53x and bf561.
- All blackfin specific gpio function names are replaced by the generic gpio APIs.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
- Move blackfin serial driver to the generic driver folder.
- Move blackfin serial headers to blackfin arch head folder.
- Update the include path to blackfin serial header in start up code.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
There may be dirty data in RDBR, so we should discard invalid data.
This operation also clears RXS bit in STAT register.
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
BF5xx rx dma causes spi flash random read error.
Accually spi controller has problems both on tx and rx dma.
So remove spi dma support in u-boot.
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
add mmc card support with atmel mci driver
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Using IP version for different setting
- Higher version supports 8bit mode
- Higher version bus width setting is different
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Using IP version to check whether it has wdrbt bit in mode register
Tested in at91sam9x5ek and at91sam9n12ek.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[fix warning about incompatible parameter]
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The manual resolution in commit ec7023db wrongly removed functions
nand_init and nand_deselect from file drivers/mtd/nand/mxc_nand_spl.c.
Revert this removal.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Stefano Babic <sbabic@denx.de>
commit 21144298 (power: twl6035: add palmas PMIC support)
introduced twl6035_i2c_[read|write]_u8
Then, commit dd23e59d (omap5: pbias ldo9 turn on)
introduced palmas_[read|write]_u8 for precisely the same access
function. TWL6035 belongs to the palmas family, so instead of having
an twl6035 API, we could use an generic palmas API instead.
To stay consistent with the function naming of twl4030,6030 accessors,
we use palmas_i2c_[read|write]_u8
Cc: Balaji T K <balajitk@ti.com>
Cc: Sricharan R <r.sricharan@ti.com>
Reported-by: Ruchika Kharwar <ruchika@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Since TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs,
rename twl6035_mmc1_poweron_ldo by a more generic palmas_mmc1_poweron_ldo
function.
Signed-off-by: Nishanth Menon <nm@ti.com>
Since TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs,
rename twl6035_init_settings with an more generic palmas_init_settings
Signed-off-by: Nishanth Menon <nm@ti.com>
TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs
Rename twl6035 to palmas to allow reuse across multiple current and
future platforms
As part of this change, change the CONFIG_TWL6035_POWER to
CONFIG_PALMAS_POWER and update usage of header file accordingly.
Signed-off-by: Nishanth Menon <nm@ti.com>
twl6030_i2c_[read|write]_u8 can be used else where to access
multi-function device such as twl6030, so move the register access
functions to the common twl6030.h header file.
Signed-off-by: Nishanth Menon <nm@ti.com>
u-boot standard i2c read prototype is
i2c_read(addr, reg, 1, &buf, 1)
twl4030_i2c_read_u8(u8 addr, u8 *val, u8 reg)
does not provide consistency, so switch the prototype to be
consistent with rest of u-boot i2c operations:
twl4030_i2c_read_u8(u8 addr, u8 reg, u8 *val)
Signed-off-by: Nishanth Menon <nm@ti.com>
u-boot standard i2c register write prototype is
i2c_reg_write(u8 addr, u8 reg, u8 val)
twl4030_i2c_write_u8(u8 addr, u8 val, u8 reg)
does not provide consistency, so switch the prototype to be
consistent with rest of u-boot i2c operations:
twl4030_i2c_write_u8(u8 addr, u8 reg, u8 val)
Signed-off-by: Nishanth Menon <nm@ti.com>
Adds an ET1011C PHY driver which is derived from the
Linux kernel PHY driver (drivers/net/phy/et1011c.c)
from the v3.9-rc2 tag. Note that an errata workaround
config option is implemented to allow for TX_CLK to be
enabled even when gigabit mode is negotiated. This
workaround is used on the PG1.0 TI814X EVM.
Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
TI814x's version 1 CPSW has a different slave_regs layout.
Add support for the differing registers.
Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Microblaze uses gpio which is connected to the system reset.
Currently gpio subsystem wasn't used for it.
Add gpio driver and change Microblaze reset logic to be done
via gpio subsystem.
There are various configurations which Microblaze can have
that's why gpio_alloc/gpio_alloc_dual(for dual channel)
function has been introduced and gpio can be allocated
dynamically.
Adding several gpios IP is also possible and supported.
For listing gpio configuration please use "gpio status" command
This patch also remove one compilation warning:
microblaze-generic.c: In function 'do_reset':
microblaze-generic.c:38:47: warning: operation on '*1073741824u'
may be undefined [-Wsequence-point]
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
A malloc() followed by memset() can be simply replaced by calloc().
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
If failed the add_host(), it is reasonable that return value of
add_sdhci().
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Without this additional delay, some eMMC don't negotiate properly bus width
Tested on:
- Toshiba THGBM2G8D8FBAIB
- Toshiba THGBM4G4D1HBAR
- Micron MTFC4GMVEA (the one giving the problem)
- Hynix H26M64002BNR
- SanDisk SDIN5E1-32G
Signed-off-by: Davide Bonfanti <davide.bonfanti@bticino.it>
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Most of time that MMC driver spends on initializing a device is polling
OCR (operation conditions register). To decouple this polling loop,
device init is split into two parts: The first part fires the OCR query
command, and the second part polls the result. So the caller is now no
longer bound to the OCR-polling delay; he may fire the query, go
somewhere and then come back later for the result.
To use this, call mmc_set_preinit() on any device which needs this.
This can save significant amounts of time on boot (e.g. 200ms) by
hiding the MMC init time behind other init.
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Removed internal cache_flush operations and placed a flush of the
entire frame-buffer at the end of each public function.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Ensure that wrong bitstream won't be loaded
to current device.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
Devcfg device requires to load bitstream in binary format.
But u-boot also has an option for loading bitstream in bit
format. Let's handle both cases by zynqpl driver.
Also add suport for loading partial bitstreams.
The first driver version was done by:
Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
All fpga functions use devnum as int. Only fpga_loadbitstream
is using it as unsinged long dev.
This patch synchronize it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
In bitstream decoding you can directly check device
which you want to load and in fpga.c are fpga_validate
and fpga_dev_info functions which should be used for it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
CONFIG_FPGA in past was a bitfield where bits
were use for vendor identification.
This fix should be the part of this commit:
"Improve configuration of FPGA subsystem"
(sha1: 0133502e39)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
We can use a common global method for calculating minimum of
3 numbers. Put the same in 'common header' and let 'ehci'
use it.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Acked-by: Tom Rini <trini@ti.com>
This patch adds a new 'usb test' command, that will set a port to a USB
2.0 test mode (see USB 2.0 spec 7.1.20). It supports all five test modes
on both downstream hub ports and ordinary device's upstream ports. In
addition, it supports EHCI root hub ports.
Signed-off-by: Julius Werner <jwerner@chromium.org>
This patch adds a driver for the diskonchip G4 nand flash device. It is based
on the driver from the linux kernel.
This also includes a separate SPL driver. A separate SPL driver is used because
the device operates in a different mode (reliable mode) when loading a boot
image, and also because the storage format of the boot image is different from
normal data (pages are stored redundantly). The SPL driver basically mimics how
a typical IPL reads data from the device. The special operating mode and
storage format are used to compensate for the fact that the IPL does not contain
the BCH ecc decoding algorithm (due to size constraints). Although the u-boot
SPL *could* use ecc, it operates like an IPL for the sake of simplicity and
uniformity, since the IPL and SPL share the task of loading the u-boot image.
As a side benefit, the SPL driver is very small.
[port from linux kernel 3.4 commit 570469f3bde7f71cc1ece07a18d54a05b6a8775d]
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
If CONFIG_USB_DEV_PULLUP_GPIO is defined, a link error occurs because the
set_GPIO_mode() helper function is not implemented. This function doesn't do
much except make the code a little more readable, so I just manually coded its
equivalent and removed the prototype from the header file. It is invoked no
where else in the code.
While I was at it, I noticed that two other function prototypes in the same
header file are also neither implemented nor invoked anywhere, so I removed them
as well.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Make lcd_init() a weak pointer so that boards can overload it if necessary. The
palmtreo680 board needs to wiggle some gpios and configure the pwm controller in
order to get the lcd and its backlight working.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Legacy iomux support is no longer needed now that all boards have been converted
to iomux-v3.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Add support for generic NAND SPL via the SPL framework into the
mxc_nand_spl driver. This is basically just a simple rename and
publication of the already implemented functions. To avoid the
bare-bones functions getting in the way of the NAND_SPL, build
them only if CONFIG_SPL_FRAMEWORK is not defined.
Also make sure the requested payload is aligned to full pages,
otherwise this simple driver fails to load the last page.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Some legacy RGMII phys don't have in band signaling for the
speed information. so set the RGMII MAC mode according to
the speed got from PHY.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Reported-by: John Traill <john.traill@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Delete all occurrences of hang() and provide a generic function.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
[trini: Modify check around puts() in hang.c slightly]
Signed-off-by: Tom Rini <trini@ti.com>
log2 of the device block size serves as the shift value used to calculate
the block number to read in file systems when implementing avaiable block
sizes.
It is needed quite often in file systems thus it is pre-calculated and
stored in the block device descriptor.
Signed-off-by: Egbert Eich <eich@suse.com>
The number 512 appears quite a bit in the mmc code. Add a constant for this
so that it can be used here and in other parts of the code (e.g. SPL code
which loads from mmc).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
block_read returns unsigned long, so it doesn't make sense to check for
< 0. and neither does marking the header structure as const and then
casting away the constness to load data into it.
Also cleanup some unneeded pointer casting while we're at it.
Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
Reviewed-by: Tom Rini <trini@ti.com>
Avoid overwriting GEMx_RCLK_CTRL and GEMx_CLK_CTRL
if the Ethernet interface is connect on EMIO
Do not enable emio for this standard board configuration for now.
Signed-off-by: David Andrey <david.andrey@netmodule.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
Pass the PHY address to the driver init to
allow parallel use of both interfaces
Signed-off-by: David Andrey <david.andrey@netmodule.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
The whole driver used 100Mbps because of zc702 rev B.
Fix problem with not setup proper clock for gem1.
This is generic approach for clk setup.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
BDs can be correctly setup just once and init function
performs only phy autodetection and enabling RX/TX.
RX/TX are disabled in halt function.
This patch solves the problem with repeatable tftp transfers.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
Removing this bit causes that frame is sent only once.
(With wrap big one packet has been sent several times
which dramatically decrease throughput)
TRM: (Table 16-3: Tx Buffer Descriptor Entry)
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
This phy is used on zedboard (xilinx zynq platform).
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
Watchdog can be used on Microblaze, PPC and Zynq hw designs.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
This will be used by the i.MX6 NAND support.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
The following headers are moved to a i.MX common location:
- regs-common.h
- regs-apbh.h
- regs-bch.h
- regs-gpmi.h
- dma.h
This way this header can be re-used also by other i.MX platforms.
For example the i.MX6 which will need it for the upcoming NAND
support.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Support to check whether the SD3.0 or not.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Rommel Custodio <sessyargc@gmail.com>
eMMC vesrion is supported up to v4.5.
But bootloader isn't saw the exact eMMC version.
After applied this patch,
if use the mmcinfo command, then can see the exactly mmc version.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Rommel Custodio <sessyargc@gmail.com>
Rework the waiting for transfer completion loop condition
to continue waiting until both Transfer Complete and DMA End
interrupts occur. Checking of DLA bit in Present State register
looks not needed in addition to interrupts status checking,
so it can be removed from the condition. Also, DMA Error
condition is added to the list of data errors, checked in the loop.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
The cache should invalidate the read buffer for
the SD card interface after the transfer complete,
not command-complete.
Tested-by: Andrew Gabbasov <Andrew_Gabbasov@mentor.com>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi
clock glitch durant reset) solved, is back now and itwas re-introduced by
commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling).
Actually the glitch is happening due to always toggling between slave mode
and master mode by configuring the CHANNEL_MODE bits in this reset function.
Since the spi driver only supports master mode, set the mode for all channels
always to master mode in order to have a stable, "glitch-free" SPI clock line.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Add a driver for the I2C TPM from Infineon.
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Rong Chang <rongchang@chromium.org>
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
When building for the Sandbox version, the casts in this change are
necessary to avoid compilation issues.
Signed-off-by: Taylor Hutt <thutt@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
If CONFIG_NAND_ECC_BCH is set use 4-bit error correction code instead of
the 1-bit error correction code on the NAND device.
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Following the removal of the smdk6400 board, the s3c64xx SoC becomes unused, so
remove associated code. It will still be possible to restore it later from the
Git history if necessary.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
This also fixes support for mx31pdk and tx25, which had been broken by commit
e05e5de7fa.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
The syndrome functions should use the page number passed as argument instead of
the page number saved upon NAND_CMD_READ0.
This does not make any difference if the NAND_NO_AUTOINCR option is set, but
otherwise this fixes accesses to the wrong pages.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Scott Wood <scottwood@freescale.com>
The page number indicated in the debug trace of mxc_nand_read_oob_syndrome() did
not match the page being worked on.
By the way, replace the GCC-specific __FUNCTION__ with __func__.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Add some abstraction to NFC definitions so that some parts of the current code
can also be used for future i.MX5 code.
Clean up a few things by the way.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Currently is_16bit_nand() is a per SoC function and it decides the bus nand
width by reading some boot related registers.
This method works when NAND is the boot medium, but does not work if another
boot medium is used. For example: booting from a SD card and then using NAND
to store the environment variables, would lead to the following error:
NAND bus width 16 instead 8 bit
No NAND device found!!!
0 MiB
Use CONFIG_SYS_NAND_BUSWIDTH_16BIT symbol to decide the bus width.
If it is defined in the board file, then consider 16-bit NAND bus-width,
otherwise assume 8-bit NAND is used.
This also aligns with Documentation/devicetree/bindings/mtd/nand.txt, which
states:
nand-bus-width : 8 or 16 bus width if not present 8
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Introduce CONFIG_SYS_NAND_BUSWIDTH_16BIT option so that other NAND controller
drivers could use it when a 16-bit NAND is deployed.
drivers/mtd/nand/ndfc has CONFIG_SYS_NDFC_16BIT, so just rename it, so that
other NAND drivers could reuse the same symbol.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
The unwind code was not reversing operations correctly and was causing
a hang on any error condition.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Support for NAND storage devices to work with the DFU framework.
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Scott Wood <scottwood@freescale.com>
We make these two functions take a size_t pointer to how much space
was used on NAND to read or write the buffer (when reads/writes happen)
so that bad blocks can be accounted for. We also make them take an
loff_t limit on how much data can be read or written. This means that
we can now catch the case of when writing to a partition would exceed
the partition size due to bad blocks. To do this we also need to make
check_skip_len count not just complete blocks used but partial ones as
well. All callers of nand_(read|write)_skip_bad are adjusted to call
these with the most sensible limits available.
The changes were started by Pantelis and finished by Tom.
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: Tom Rini <trini@ti.com>
Previously we didn't support upload/download larger than available
memory. This is pretty bad when you have to update your root filesystem
for example.
This patch removes that limitation (and the crashes when you transfered
any file larger than 4MB) by making raw image writes be done in chunks
and making file maximum size be configurable.
The sequence number is a 16 bit counter; make sure we handle rollover
correctly. This fixes the wrong transfers for large (> 256MB) images.
Also utilize a variable to handle initialization, so that we don't rely
on just the counter sent by the host.
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: Tom Rini <trini@ti.com>
Following commit:
"cmd_ext4: BREAK and correct ext4write parameter order"
SHA1:0171d52c410cbaa9290b1b214e695697c835bfe5
introduced cleanup of ext4write semantics to be consistent with other
filesystem's writing commands (e.g. fatwrite).
This commit provides correct ext4write command generation at DFU eMMC
code.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
The kernel states:
---8<---
The OMAP3 GPMC hardware BCH engine computes remainder polynomials, it does not
provide automatic error location and correction: this step is implemented using
the BCH library.
--->8---
And we do so in u-boot.
This implementation uses the same layout for BCH8 but it is fix. The current
provided layout does only work with 64 Byte OOB.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Ilya Yanok <ilya.yanok@cogentembedded.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Mansoor Ahamed <mansoor.ahamed@ti.com>
Cc: Thomas Weber <thomas.weber.linux@googlemail.com>
With uppcoming BCH support on OMAP devices we need to decide between differnt
algorithms when switching the ECC engine. Currently we support 1-bit hammign
and 8-bit BCH on HW backend.
In order to switch between differnet ECC algorithms we need to change the
interface of omap_nand_switch_ecc() also.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Thomas Weber <thomas.weber.linux@googlemail.com>
arch/arm/include/asm/arch-am33xx/omap_gpmc.h and
arch/arm/include/asm/arch-omap3/omap_gpmc.h are almost the same, consolidate
the common parts into a new header.
Introduce a new asm/omap_gpmc.h which defines the command part and pulls in
the architecture specific one.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Flush UART3 xmit on enable if TEMT is broken
On some OMAP3 devices when UART3 is configured for boot mode before SPL starts
only THRE bit is set. We have to empty the transmitter before initialization
starts. This patch avoids the use of CONFIG_SYS_NS16550_BROKEN_TEMT.
Signed-off-by: Manfred Huber <man.huber@arcor.de>
Tested-by: Javier Martinez Canillas <javier@dowhile0.org>
Tested-by: Andreas Bießmann <andreas.devel@googlemail.com>
Do not config MUSB to highspeed mode if CONFIG_USB_GADGET_DUALSPEED
is not set, in which case Ether gadget only operates in fullspeed.
Reviewed-by: Tom Rini <trini@ti.com>
Signed-off-by: Bin Liu <b-liu@ti.com>
On TI AM335x devices, MUSB has bulk split/combine feature enabled
in the ConfigData register, but the current MUSB driver does not
support it yet. Therefore, disable the feature for now, until the
driver adds the support.
One usecase which is broken because of this feature is that Ether
gadget stops working in Fullspeed mode (by un-defining
CONFIG_USB_GADGET_DUALSPEED)
After desabled this feature, MUSB driver send packets in proper size
(no more than 64 bytes) in Fullspeed mode.
This has been validated with Ether gadget in Fullspeed mode on AM335x
EVM.
Signed-off-by: Bin Liu <b-liu@ti.com>
Reviewing the ECSPI reset handling shows two issues:
1. For the enable/reset bit (MXC_CSPICTRL_EN) in the control reg
(ECSPIx_CONGREG) the i.MX6 technical reference manual states:
-- cut --
ECSPIx_CONREG[0]: EN: Writing zero to this bit disables the block
and resets the internal logic with the exception of the ECSPI_CONREG.
-- cut --
Note the exception mentioned: The CONREG itself isn't reset.
Fix this by manually writing the reset value 0 to the whole register.
This sets the EN bit to zero, too (i.e. includes the old
~MXC_CSPICTRL_EN).
2. We want to reset the whole SPI block here. So it makes no sense
to first read the old value of the CONREG and write it back, later.
This will give us the old (historic/random) value of the CONREG back.
And doesn't reset the CONREG.
To get a clean CONREG after the reset of the block, too, don't use
the old (historic/random) value of the CONREG while doing the reset.
And read the clean CONREG after the reset.
This was found while working on a SPI boot device where the i.MX6 boot
ROM has already initialized the SPI block. The initialization by the
boot ROM might be different to what the U-Boot driver wants to configure.
I.e. we need a clean reset of SPI block, including the CONREG.
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Apparently, CONFIG_SYS_HZ must be 1000. Change this, and fix the timer
driver to conform to this.
Have the timer implementation export a custom API get_timer_us() for use
by the BCM2835 MMC API, which needs us resolution for a HW workaround.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
This fixes this build warning:
Configuring for qemu_mips64 - Board: qemu-mips64, Options: SYS_BIG_ENDIAN
text data bss dec hex filename
215344 13082 218720 447146 6d2aa qemu_mips64/u-boot
cfi_flash.c: In function 'flash_map':
cfi_flash.c:217:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
Maximum bus width supported by some i.MX6 boards is not 8bit like
others. In case where both host controller and card support 8bit transfers,
they agree to communicate on 8bit interface while some boards support only 4bit interface.
Due to this reason the mmc 8bit default mode fails on these boards. To rectify this,
define maximum bus width supported by these boards (4bit). If max_bus_width is not
defined, it is 0 by default and 8bit width support will be enabled in host
capabilities otherwise host capabilities are modified accordingly.
It is tested with a MMCplus card.
Signed-off-by: Abbas Raza <Abbas_Raza@mentor.com>
cc: stefano Babic <sbabic@denx.de>
cc: Andy Fleming <afleming@gmail.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
This makes sure we have inline functions such as inb/outb that
are used in these two files by including the arch-specific
<asm/io.h> header. However the ARM version does not provide the
accessors unless the config symbol __io is also defined so add
that in front of the include.
After this the bios emulator will compile on ARM systems.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch addjusted the write buffer size for M29EW devices those
are operated in 8-bit mode.
The M29EW devices seem to report the CFI information wrong when
it's in 8 bit mode.
There's an app note from Numonyx on this issue and there's a patch
in the open source as well for Linux, but it doesn't seem to be in mainline.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Tested-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This commit is based on that patch from aaron.williams@caviumnetworks.com
with same commit title. pulled the same code changes into current u-boot tree.
http://patchwork.ozlabs.org/patch/140863/http://lists.denx.de/pipermail/u-boot/2011-April/089606.html
This patch corrects the addresses used when working with Spansion/AMD FLASH chips.
Addressing for 8 and 16 bits is almost identical except in the 16-bit case the
LSB of the address is always 0. The confusion arose because the addresses
in the datasheet for 16-bit mode are word addresses but this code assumed it was
byte addresses.
I have only been able to test this on our Octeon boards which use either an 8-bit
or 16-bit bus. I have not tested the case where there's an 8-bit part on a 16-bit
bus.
This patch also adds some delays as suggested by Spansion.
If a part can be both 8 and 16-bits, it forces it to work in 8-bit mode if an
8-bit bus is detected.
Apart from the pulled changes, fixed few minor code cleanups and tested
on 256M29EW, 512M29EW flashes.
Before this fix:
---------------
Bank # 1: CFI conformant flash (8 x 8) Size: 64 MB in 512 Sectors
AMD Standard command set, Manufacturer ID: 0xFF, Device ID: 0xFF
Erase timeout: 4096 ms, write timeout: 2 ms
Buffer write timeout: 5 ms, buffer size: 1024 bytes
After this fix:
--------------
Bank # 1: CFI conformant flash (8 x 8) Size: 64 MB in 512 Sectors
AMD Standard command set, Manufacturer ID: 0x89, Device ID: 0x7E2301
Erase timeout: 4096 ms, write timeout: 2 ms
Buffer write timeout: 5 ms, buffer size: 1024 bytes
Signed-off-by: Aaron Williams <aaron.williams@caviumnetworks.com>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Tested-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.
All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.
Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.
Signed-off-by: York Sun <yorksun@freescale.com>
After merging LCD patches for v2013.04 the bcm2835 video
driver building is broken due to removal of many global
variables. Fix the driver.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Enclosing process_nodes() and spi_get_config() inside
CONFIG_OF_CONTROL, since they are compiled only for DT systems.
This fixes following warning:
exynos_spi.c:391:12: warning: 'process_nodes' defined but not used [-Wunused-function]
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add function to parse the required platform data fron DP DT node
and fill the edp_info structure.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
dp_regs variable was redundantly defined across all the functions in
the driver even though it contains just the same address. We make it
global and initialize it once using exynos_dp_set_base_addr().
>From then on, other funtions can use the address stored in the global variable.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add function to parse FIMD data from device tree.
The driver still supports non-DT case.
Define panel_info statically in some file if you are not using DT.
If you have defined DT node for FIMD, panel_info will be filled
using the bindings of FIMD DT node.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
fimd_ctrl variable was redundantly defined across all the functions in
the driver even though it contains just the same address. We make it
global and initialize it in exynos_fimd_lcd_init. From then on, other
funtions can use the data in the global variable.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Replaced the functionality of callbacks by using a standard set of functions.
Instead of implementing and hooking up a callback, put the same code in one of
the standard set of functions by overriding it.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Replaced the functionality of callbacks by using a standard set of functions.
Instead of implementing and hooking up a callback, put the same code in one of
the standard set of functions by overriding it.
This patch is tested only on SMDK5250.
For Trats and universal_c210 board, it is only compile tested.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add driver for tegra114 SPI controller. This controller is not
compatible with either the tegra20 or tegra30 controllers, so it
requires a new driver.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Add support for Winbond W25Q32DW 32Mbit part
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Add a common interface to fdt based SPI drivers. Each driver is
represented by a table entry in fdt_spi_drivers[]. If there are
multiple SPI drivers in the table, the first driver to return success
from spi_init() will be registered as the SPI driver.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Make the tegra20 SPI driver similar to the tegra30 (and soon to be
tegra114) SPI drivers in preparation of common fdt SPI driver front
end.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Move register structs from headers into .c files and use common name.
This is in preparation of making common fdt front end for SPI
drivers.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Remove non fdt support from tegra20 and tegra30 SPI drivers in
preparation of new common fdt based SPI driver front end.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Rename tegra SPI drivers to tegra20_flash and tegra20_slink in
preparation for commonization and addition of tegra114_spi.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
This feature was only used for tegra20 seaboard that had a pinmux
conflict on the SPI pins. These boards were never manufactured, so
remove this support to clean up SPI driver.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Gets rid of warnings from omap_gpio:
ERROR : check_gpio: invalid GPIO -1
(and undefined behaviour as the -1 error code is interpreted as gpio value)
Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
Let mmc_getcd() return true and mmc_getwp() false if mmc driver doesn't
provide handlers for them.
Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
[trini: Add braces around first if test in each case to fix warning]
Signed-off-by: Tom Rini <trini@ti.com>
- In arch/arm/cpu/armv7/omap-common/timer.c,
drivers/mtd/nand/omap_gpmc.c and drivers/net/cpsw.c add #include files
that the driver needs but had been relying on <config.h> to bring in.
- In arch/arm/cpu/armv7/omap-common/lowlevel_init.S add <config.h>
- In am335x_evm.h and pcm051.h don't globally include
<asm/arch/hardware.h> and <asm/arch/cpu.h> but just <asm/arch/omap.h>
as that is the only include which defines things the config uses.
Cc: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: Tom Rini <trini@ti.com>
commit d484b52 "video: Skip bitmaps which do not fit into the screen in
cfb_console" breaks splash screen alignment which is passed in as magic
(BMP_ALIGN_CENTER) x/y coordinates. Moving the check after the alignment block
fixes this.
Signed-off-by: Matthias Weisser <weisserm@arcor.de>
Acked-by: Simon Glass <sjg@chromium.org>
lcd_base is available as gd->fb_base as well, there is no need
to keep a seperate copy.
For completeness the ack of Bo Shen is for the atmel part.
Cc: Alessandro Rubini <rubini@unipv.it>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stelian Pop <stelian@popies.net>
Cc: Tom Warren <twarren@nvidia.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
[agust: also fix cm_t35 board while rebasing]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
console_col, console_row, lcd_line_length, lcd_console_address had
to be declared in board / driver specific code, but were not actually
used there on many boards. Get rid of the global variables.
for completeness, the ack of Bo Shen is for the atmel part
Cc: Alessandro Rubini <rubini@unipv.it>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stelian Pop <stelian@popies.net>
Cc: Tom Warren <twarren@nvidia.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
[agust: rebased and fixed cm_t35 board]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Since the lcd code was compiled unconditionally for pxa also add
CONFIG_PXA_LCD to the boards using this framebuffer. Since
driver/video contains video and lcd drivers, add lcd to the name
to make clear it belongs to common/lcd.c.
cc: Anatolij Gustschin <agust@denx.de>
cc: Cliff Brake <cliff.brake@gmail.com>
cc: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Since the lcd code was compiled unconditionally in arch also
add CONFIG_MPC8XX_LCD to the boards using this driver.
cc: Anatolij Gustschin <agust@denx.de>
cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Since CONFIG_VIDEO_AMBA is not set by any board, it does not seem
to be used, so remove it since there is no way to (compile) test it.
cc: Alessandro Rubini <rubini@unipv.it>
cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Alessandro Rubini <rubini@unipv.it>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
lcd_color_fg and lcd_color_bg had to be declared in board specific
code, but were not actually used there; in addition, we have getter /
setter functions for these, which were not used either.
Get rid of the global variables, and use the getter function where
needed (so far no setter calls are needed).
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Alessandro Rubini <rubini@unipv.it>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stelian Pop <stelian@popies.net>
Cc: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Jeroen Hofstee <jeroen@myspectrum.nl>
[agust: also fixed cm_t35 board while rebasing]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
This adds a simple driver for the BCM2835's SD controller.
Workarounds are implemented for:
* Register writes can't be too close to each-other in time, or they will
be lost.
* Register accesses must all be 32-bit, so implement custom accessors.
This code was extracted from:
git://github.com/gonzoua/u-boot-pi.git master
which was created by Oleksandr Tymoshenko.
Portions of the code there were obviously based on the Linux kernel at:
git://github.com/raspberrypi/linux.git rpi-3.6.y
commit f5b930b "Main bcm2708 linux port" signed-off-by Dom Cobley.
swarren changed the following for upstream:
* Removed hack udelay()s in bcm2835_sdhci_raw_writel(); setting
SDHCI_QUIRK_WAIT_SEND_CMD appears to solve the issues.
* Remove register logging from read*/write* functions.
* Sort out confusion with min/max_freq values passed to add_sdhci().
* Use more descriptive variable names and calculations in IO accessors.
* Simplified and commented twoticks_delay calculation.
* checkpatch fixes.
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Oleksandr Tymoshenko <gonzo@bluezbox.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Andy Fleming <afleming@gmail.com>
The firmware running on the bcm2835 SoC's VideoCore CPU manages the
display controller. Add a simple "LCD" driver that communicates with the
firmware using the property mailbox protocol. This configures the
display and frame-buffer to match whatever physical resolution the
firmware chosen when booting, which is typically the native resolution
of the attached display device, presumably unless otherwise specified
in config.txt on the boot media.
Enable this driver in the Raspberry Pi board configuration.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Enable device tree control of SPI flash, and use this to implement
memory-mapped SPI flash, which is supported on Intel chips.
Signed-off-by: Simon Glass <sjg@chromium.org>
This SPI controller can only write 64 bytes at a time. Add this restriction
in so that 'sf write' works correct for blocks larger than 64 bytes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some SPI flash controllers (e.g. Intel ICH) have a limit on the number of
bytes that can be in a write transaction. Support this by breaking the
writes into multiple transactions.
Signed-off-by: Simon Glass <sjg@chromium.org>
This supports Intel ICH7/9. The Intel controller is a little unusual in
that it is mostly intended for use with SPI flash, and has some
optimisations and features specifically for that application. In
particular it is not possible to support ongoing transactions that
continue over many calls with SPI_XFER_BEGIN and SPI_XFER_END.
This driver supports writes of up to 64 bytes at a time, the limit
for the controller. Future work will improve this.
Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
